SU763920A1 - Linear interpolator - Google Patents

Description

the equalizer is made on two MOS transistors, the sources and gates of which are connected respectively to the information and control inputs of the controlled one; adder, and the drains are combined and are its output. FIG. 1 shows the block diagram of the proposed linear interpolator; in fig. 2 - time diagrams we, explaining the principle of its work. The linear interpolator contains a block of delay 1, a generator of linearly varying voltage 2, controlled by the adder 3, performed on. , two MOS transistors 4 and 5.

Interpol torus works as follows.

The input step signal is fed to the input of the delay unit 1, which provides a signal delay for the interpolation time T, which is equal to the period following the levels of the input step signal. At the same time, the input signal is fed to the source of the MOS transistor 4, which is part of the adder 3. A delayed T signal from the output of the delay unit 1 is fed to the source of the MOS transistor 5 of the adder 3. The resistance of the channels of the MOS transistors 4 and 5 is Two antiphase voltages varying according to the interpolation law. These voltages are applied to the gates of the corresponding transistors of the adder 3 from the outputs of the generator 2 of the linearly varying voltage, where they are produced from the clock generator. period equal to T.

The interpolation process of the stepped signal using the interpolator is as follows. At the time point c (Fig. 2 a, b), corresponding to the first interpolation point, the current input level and the level delayed by the interpolation time T, are applied to the sources of the MOS transistors 3. The resistances of the MOS transistors 4 and 5 at time t have the values determined by the antiphase control voltages (Fig. 2c, d) applied to the gates of these transistors and vary according to the interpolation law. The resistance of the transistor 4 is large, and transistor 5, respectively, is small, since the gate of transistor 4 has voltage O, and the gate of transistor 5 has a maximum opening potential. With this ratio of the resistances of the channels of the transistors 4 and 5, the voltage at the output of the controlled adder 3 is equal to the delayed sampling of the input step signal. As the control voltage U (t) at the gates of the MOS transistors changes, the ratio of the resistances of the channels changes. Channel resistance transistor 4

decreases as the voltage across its gate increases, and transistor 5 increases as the voltage across its gate decreases. Such a change in the resistance ratios of the 5 channels of transistors 4 and 5 leads to an increase in the voltage at the output of the controlled adder 3, which is proportional to the interpolation law. At the time tj / corresponding to the second interpolation point, the voltage at the output of the controlled adder 3 is almost equal to the value of the current sample of the input step signal, and the interpolation process of the first section ends. At the same time, in the generator 2, the signals are reset to the initial state and the interpolation of the second segment begins, and so on.

As a result, a piecewise linear voltage appears at the output of the interpolator, interpolating the value of the function between successive readings, regardless of the frequency of their tracing (Fig. 2e).

3 The proposed interpolator differs from the prototype in its circuit simplicity, and the simplification of the circuit is combined with the enhanced functionality while maintaining Q high interpolation accuracy.

The interpolator makes it possible to accurately reproduce functions in a wide range of sampling frequencies without additional adjustment, the need for selecting a constant integrator time has disappeared, it has become possible to interpolate functions defined by samples with a variable tracking frequency.

Claims (2)

Invention Formula 0 1. A linear interpolator containing a controlled adder, the information inputs of which directly and through a delay unit are connected to the interpolator input, and the output is an interpolator output, characterized in that, in order to simplify the interpolator, it contains variable voltage, two anti-phase 0 outputs of which are connected to the control inputs of the controlled adder. 2. The interpolator of claim 1, which is based on the fact that in it the controlled adder is made on two MOS transistors, the sources and gates of which are connected respectively to the information and control inputs of the controlled adder, and the drains are combined and are its output, 60 Sources of Information, taken into account in the examination 1. Markus J., Discretization and Quantization. M., Mir, 1968, pp.39-40. 2. USSR author's certificate In 452011, class, q About Q 7/30, 1972. 7-4 I1 1 1I I a