SU754567A1 - Power factor regulator - Google Patents

Description

The invention relates to devices for automatic balancing of currents and stabilization of a given power factor in electrical networks.

Automatic power factor control devices are known, where one relay switches on its capacitor set with its contacts when the load current increases relative to the setpoint and turns it off when the load current decreases relative to the setpoint [].

However, such devices do not provide the required accuracy of power factor regulation, since their principle of operation is not configured directly from the power factor sensor, but to current and voltage levels by turning off or on the capacitor unit.

The closest to the proposed controller is the power factor controller, which contains the power factor sensor 25, the switching unit of the minimum power capacitor bank, and the switching units of the capacitor battery, the control circuits of which through connectors 2

with the outputs of the first coincidence schemes [2].

The aim of the invention is to improve the accuracy of regulation.

5 This is achieved by the fact that the power factor regulator, which contains the power factor sensor, the minimum power capacitor bank switching unit and the capacitor battery switching units, whose control circuits are connected to the outputs of the first coincidence circuits through the formers, have been used to form the leading edge pulses of positive and negative half-periods phase voltages, two reverse binary counters, two binary counters, six triggers, five coincidence circuits, OR circuit, continuous control units20 A signal for each phase, a generator, the output of the power factor sensor is connected via the first input of the second and third matching circuits to the inputs of the first and second binary counters, the outputs of the first binary counter are connected to the inputs of the OR circuit, to one of the inputs of the fourth and fifth matching circuits, outputs which are connected to one of the inputs of the second and 30 third triggers, the outputs of which

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connected to the inputs of the first reversible binary counter, the outputs of which are connected to the inputs of the smooth adjustment blocks, the output of the OR circuit is connected to the input of the first counter and one of the inputs of the first trigger, the outputs of the first and fourth triggers are connected to the second inputs of the second and third coincidence circuits, generator output connected to the inputs of reversible binary meters and stepless adjustment blocks, the outputs of which are connected to the control input of the switching unit of the minimum power battery To the leading edge of the positive half-cycles of the voltage of the first phase is connected to the second input of the first trigger and the input of the smooth adjustment block of the first phase, the output of the formation of the first-phase negative half-cycles of the voltage of the first phase is connected to the first input of the fifth and second inputs of the second and third triggers, the first input the sixth coincidence circuit and with the input of the smooth adjustment unit of the first phase, the output of the second binary counter is connected to the second inputs of the fourth trigger and the sixth circuit of the same eniya,

The first input of the sixth trigger, the output of the sixth coincidence circuit is connected to the second input of the fifth and sixth triggers, the outputs of which are connected to the inputs of the second reversible binary counter, the outputs of which are connected to the second inputs of the fourth and fifth coincidence circuits.

FIG. 1 shows the general scheme of the power factor regulator; in fig. 2 -. timing diagrams of the formation of the leading edge pulses of positive IAP + and negative IAP-half-periods of phase voltage and the principle of operation of the regulator; Fig. Power factor sensor, the frequency of the output pulses of which is proportional to the phase shift of the current and voltage.

The regulator includes circuits for forming 1, 2, 3 pulses of the leading edge of positive IAP + and negative IAP-voltage half-periods for phases A, B, C, load 4, sensor 5 of power factor, even-lasting trigger 6, the output of which is connected to the input of the third coincidence circuit 7, its output is connected to the input of the second binary counter 8, the sixth coincidence circuit 9, its output is connected to the inputs of the fifth and sixth trigger 10, 11, their outputs are connected to the inputs of the second reversing binary counter 12, generator 13, switching units 14 condensate GOVERNMENTAL batteries (units) 15, the first coincidence circuit 16 switching capacitor banks, which outputs through the conditioners 17 are connected to the control electrodes

thyristors 18 switch on capacitor blocks, smooth adjustment blocks 19, turn on thyristors 20 of the minimum power capacitor block 21, first trigger 22, its output is connected to the input of the second coincidence circuit 23, its output is connected to the first input of the binary counter 24, fourth coincidence circuit 25, output it is connected to the input of the second trigger 26, the second reversible binary counter 27, the fifth coincidence circuit 28. its output is connected to the input of the third trigger 29, OR circuit 30, its output is connected to the trigger input 31, its output is connected to the circuit input matches 32, its output is connected to the input of a binary counter 33, matching circuits 34, their outputs are connected to the inputs of the OR circuit 35, its output is connected to the inputs of the matching circuits 36, 37, their outputs are connected to the inputs of the flip-flops 38, 39, and their outputs are connected with inputs. Formers 40, 41, the OR circuit 42, stationary coils 43, 44 of the phase meter current, stationary voltage coil 45, moving core 46, axis 47, arrow 48, capacitor plates 49, 50, generator 51.

The power factor controller works as follows.

Due to the symmetry of the load in phases, the phase shift of the current and voltage is measured in phase A.

Formation schemes 1, 2 and 3 (Fig. 1) form the leading edge pulses of positive IAP + and negative IAP-half-periods of voltage for phases A, B, C, as shown in FIG. 2 for phase A. A load 4 is included in the line, at which the current leads the voltage, which is controlled by the sensor 5.

In each period of the voltage of the phase A line, an IPF + pulse sends trigger b, which permits the coincidence circuit 7 to skip the pulses of sensor 5 to the input of binary counter 8, which counts a certain number of pulses from the IPF + pulse to the IPF- pulse with zero current and voltage phase shift ( Fig. 2a). In this case, the output pulse of the counter 8 coincides with the pulse of the IAP- at the input of the coincidence circuit 9, the output pulse of which keeps the triggers 10, 11 in the reset state, and the reversible binary counter 12 does not change its state.

With decreasing load 4, the current advances the voltage in phase, the frequency of the output pulses of sensor 5 increases, counter 8 more quickly counts the required number of pulses (FIG. 26), its output pulse resets triggers 6, 10 and flips trigger 11 which conducts the addition of generator pulses 13 to reversible two

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A counter meter 12, which, through the switching units 14, switches on a series of capacitor banks 15, which will delay the current relative to the voltage phase. _;

With increasing load 4, the current is delayed relative to the voltage phase, the frequency of the output pulses of sensor 5 decreases, counter 8 does not have time to count the required number of pulses to the arrival of the IAP pulse (Fig. 2c), resetting trigger 11 and throwing trigger 10, which deducts pulses from generator 13 from counter 12, which at the same time disconnects a number of capacitor batteries 15, the phase shift of the current decreases. At zero phase shift counter 12 does not change the number of connected capacitor banks 15.

Switching blocks of capacitor batteries 15 (the unit may consist of several capacitor batteries) counter 12 as follows. The voltage of the single output of the discharge trigger, for example, 2, the counter 12 permits logic matching schemes. 16 transmit pulses of the IAP +, IAP-circuits 1, 2, 3 through the formers (inhibited blocking generators) 17 to the control electrodes of the thyristors 18 on switching on the block 2 of capacitors. The selection of pulses IAP +, IAP- with a delay of 3-5 μs schemes 1,

2, 3 in each phase allows you to turn on the capacitor blocks of high reactive power without voltage cutoffs, which eliminates the power surges in the line. For a smooth adjustment of the phase shift, the smooth adjustment blocks 19 are used for phases A, B, C, which include through block thyristors 20 a block 21 (battery) of minimum power 21 with a voltage cutoff proportional to the minimum phase shift of the current and voltage.

Suppose that the counter 12 has included a number of blocks 15, including block 2, but the phase of the current is somewhat ahead; the phase of the voltage and to match the output impulse of the counter 8 with the impulse IAP-on circuit 9 lack one impulse (n + 1; fig. 2d), so that the counter 12 stops switching the blocks by the output impulse of circuit 9.

Suppose that the counter 12 has turned off a certain number of blocks 15, including the 2 ° block, but the current phase lags slightly behind the voltage phase, and to match the output pulse of the counter 8 with the IAP-pulse in circuit 9, one pulse will be superfluous (p-1 ; fig.2d) to stop switching blocks. For this, the IAP + pulse sends the trigger 22, which allows the coincidence circuit 23 to skip the impulses of the sensor 5 to the input of the counter 24, which is 10

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ry counts the number of pulses (n + 1) or (n-1) and outputs pulses to the coincidence circuit 25, which, with the permission of the voltage of the unit output of the discharge trigger 2® of the counter 12, generates a pulse to flip the trigger 26, conducting the sum of the number of pulses of the generator 13 to reversing the counter 27 and 28, which, with the permission of the voltage of the zero output of the discharge trigger 2 ^{0 of the} counter 12, generates a pulse to transfer the trigger 29, which deducts the pulses of the generator 13 from the counter 27 of the number of pulses. Pulses IAP +, IAP - through the circuit OR 30 trigger trigger 31, allowing the coincidence circuit 32 to pass the generator pulses 13 to the input of the counter 33, which counts the number of pulses specified by the counter 27 on the coincidence circuit 34, the output potential of which through the circuit OR 35 resolves the circuits matches 36, 37 with the permission of the respective triggers 38, 39 to generate pulses of the generator ^{1 of the} torus 13 through the formers 40, 41 to the control electrodes of the thyristors 20.

Thus, the counter 27 sets the desired cut-off program with numbers for the counters 33 for each phase, which, at the command of IAP +, IAP-corresponding phase, carry out a program cut-off voltage on the minimum power unit (battery) 21 by switching on the thyristors 20 with cut-offs (Fig. 2). Blocks 19 for phases A, B, C work analogously.

In the initial state, the counter 8 is reset by its own output pulse on the waste tire, which also resets the trigger 6.

The counter 24 is reset to the initial state by pulses from the outputs (n + 1), (n-1) through the OR circuit 42 through the waste bus, which also resets the trigger 22. The counter 27 is reset to the initial state by the potential of the circuit 35, which also resets the trigger 31.

Triggers 26, 29 are reset, and triggers 38, 39 are thrown by pulses of IAP +, IAP-, respectively.

• Sensor 5 (Fig. 3) consists of two stationary current coils 43, 44 and one stationary voltage coil 45, a movable core 46 rotating in the direction of the rotating field induction vector at the time of maximum induction of the pulsating field on axis 47 along with arrow 48 of three-phase electromagnetic phase meter On axis 47, one of the figured plates 49 of the capacitor is fixed, the second plate 50 of which is fixed. The capacitor enters the phasing circuit of the generator 51, the frequency of the output pulses of which varies relatively zero. At zero phase shift current and voltage7

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This generator 51 emits zero frequency pulses.

Claims (1)

Claim The power factor controller containing a power factor sensor, a minimum power capacitor bank switching unit and capacitor battery switching units, the control circuits of which are connected to the outputs of the first coincidence circuits through the drivers, characterized in that the formation of the leading edge of the positive and negative half-periods of the voltage phase, two reverse binary counter, two binary counter, six triggers, five circuits matches, OR circuit, smooth adjustment blocks for each phase, a generator, the output of the power factor sensor connected via the first inputs of the second and third matching circuits to the inputs of the first and second binary counters, the outputs of the first binary counter connected to the inputs of the OR circuit, with one of the inputs the fourth and fifth coincidence circuits, the outputs of which are connected to one of the inputs of the second and third triggers, the outputs of which are connected to the inputs of the first reversible binary counter, the outputs of which are connected to the inputs of the blocks hydrochloric adjustment, output of OR circuit is connected to the input of the first counter and one of the inputs of the first flip-flop, the outputs of the first and fourth flip-flops are connected to second inputs of the second and third circuits (coincidence, the generator output is connected to the inputs of reversible binary meters and smooth adjustment blocks, the outputs of which are connected to the control input of the minimum power switching unit, one output of the formation of the voltage of the first front of the positive half-cycles of the first phase by the pulses of the leading edge, the first input the fourth trigger and the input of the smooth adjustment block of the first phase, the output of the formation circuit of the voltage pulses of the leading edge of the negative half cycles of the first Phase I is connected to the first input of the fifth and second inputs of the second and third triggers, the first input of the neck of the coincidence circuit and the input of the smooth control unit of the first phase, the output of the second binary counter is connected to the second inputs of the fourth trigger and the sixth coincidence circuit, the first input of the sixth trigger, the output of the sixth coincidence circuit is connected to the second input of the fifth and sixth flip-flops, the outputs of which are connected to the inputs of the second reversible binary counter, the outputs of which are connected to the second inputs of the fourth and fifth circuits coincidence.