SU738070A1 - Adjustable inverter - Google Patents

Description

(54) ADJUSTABLE INVERTER

one

The invention relates to the field of power conversion technology and can be used as a secondary power source for electronic equipment and automation devices. Inverters are known in which the end-to-end closure mode is eliminated by introducing into the control circuits devices that delay the leading edge of pulses that unlock the power switches.

Adjustable inverters are also known, in which the pulse-width control of the transistor power amplifier is carried out, the control signal being 15 generated as a result of the logical multiplication of the width-modulated and clock signal. Structurally, they are a power amplifier controlled from 20 logic elements and, The inputs of which are fed from the counting trigger and the pulse duration modulator.

Of the known devices, the most 25 closest to the technical essence are inverters, in which for the control of each key device RC circuits are installed that delay the leading edge of the control 30

pulses. As a threshold element in series with control transitions are included zener diodes.

The disadvantages of this device include the following.

A delay is formed in the control circuit of each key by various delay devices. For example, for a bridge amplifier, a delay unit is used, which includes four different delay devices included in the control circuits of each of the key devices. Due to the scatter of the parameters of the RC circuit, the stabilization voltages of old-timers, their different temperature; Drift time delays in adjacent yields may vary. This will cause an asymmetry of the output voltage, which will lead to the magnetization of the output transformer cores.

Control fronts: the signals depend on the dicatomic properties of the stabons, which are high frequency elements, the dynamic parameters of which are controlled during manufacture. Therefore, in the known device can not be formed738070

We are steep fronts of control signaling 5TOTB - .. - --- ---------...- .- "- ..: .C --..-. i .....

Since the delay time in a known device is determined by the stabilization voltage of the Zener diode used, and the latter has a large variation from sample to sample, it will be necessary to introduce a large amount of time into the circuit. This results in a reduction in the adjustment range.

The delay is entered at the beginning; each half period. For non-iffipye fiir ınseim5pai 3to; The efficiency of the device, controlled inverter, with pulse durations shorter than the maximum, the introduction of such a delay does not create an additional effect, since there is a natural time interval defined by the duration modulator between turning off one switches and turning on. Therefore, delaying the switch-on delay only leads to a reduction in the adjustment range.

The disadvantage is the restriction of the range control and the known method of restriction; , maximum pulse duration, given by the modulator. For example, with vertical regulation of the Chdav a1 | te boundary - 5yr1 syyaMyyoeNaNa tion of the control signal. Due to the scatter of the parameters of the circuit elements, their temperature-time drifts, it is necessary to introduce large stocks, which reduce the control range. This becomes especially significant when the inversion frequency is increased.

The purpose of the invention is to expand the dcapazone regulating and improving the symmetry of the output voltage.

This goal is achieved by the fact that in an adjustable inverter, containing key devices, a master oscillator and a control device, including, in particular, a counting trigger, a delay unit, and

the pulse duration, the input of the delay unit is connected to the output of the master oscillator, and the output of the shoton is connected to the input of the counting trigger, the synchronizing input of the duration modulator

pulses and the first inputs of the two additionally entered logical elements And, the second inputs of which are connected to the corresponding 1 output outputs of the counting trigger, and the third inputs with the output of the pulse duration modulator.

An inverter circuit diagram; shown in Fig, 1; Dray1-. The voltage grams at the characteristic points of the circuit are shown in FIG.

Adjustable inverter consists of master oscillator 1, included

.on the input of the unit 2 e aderzhkie

$) pbnt pulses, the output of which is connected to the input of the counting trigger 3,

"SS" -, .Er-s.4: r; .modulator 4 duration and logical elements 5 and b. The second input of the modulator 4 is connected to the source 7 of the control voltage. The outputs of the logic elements 5 and 6 are connected to the input of the key amplifier 8 power.

The graphs in Fig. 1 have the following meanings: 9 the voltage at the output of the master oscillator 1; 10 - voltage at the output of block 2

delay, the leading edge of pulses;

11, 12- voltages at the forward and inverse trigger 3; . 13 - voltage at the output of the modulator 4 durationJ

14, 15- output voltages of logic elements, s 5 and 6.

The dashed lines in graphs 14, 15 show the maximum possible pulse momentum.

The operation of the device is as follows.

The master oscillator 1 outputs rectangular pulses with a frequency equal to twice the frequency of the inversion. The delay unit 2 shifts the leading edge of the pulses by time 1, which is chosen equal to the resorption time of the minor nose wires in the bases of the power transistors. At the moment corresponding to the leading edge of the output voltage of the delay device, the counting trigger 3 is switched. Thus, the beginning of the half period is shifted by the time t relative to the leading edge of the voltage of the master oscillator 1. The voltage pulse from the output of the delay unit 2 enters the modulator 4 and provides its zeroing in the interval. " Therefore, before-. The SRI of the output pulse of the modulator 4 is also shifted by the time t relative to the leading edge of the pulses of the master oscillator. Thus, three voltages 10, 11 (or 12) and 13 are applied to the input of logic elements 5 and 6. Selection by half-periods is carried out by trigger 3. In the absence of voltage at the output of the trigger (level zero) there is no signal at the output of the logic element (zero). If the control voltage is such that the pulse duration of the modulator

(curve 13) is proved more (see the dotted line in FIG. 2), then it will be better in the voltage interval at the output of the delay device to switch the corresponding logic element 5 (or 6). Thus, the range of adjustment from above is limited by the angle ISO-fr ,, with t being counted from the end of the half period to the beginning.

Claims (1)

The time of the master circuit counts the interval C itself, but not the pulse interval. The fluctuations of this magnitude caused by the scatter of the element meters and their temperature-time drift rates are not related to the drift of the master oscillator and the rest of the circuit. Therefore, the need for a time margin is determined only by a relatively small device drift delay. If, however, the interval is determined by the difference in the half-period durations and the maximum permissible pulse duration, i.e. how small the difference is between two large quantities, then the total drift of this magnitude will be much larger than in the proposed device. Thus, the adjustment range in the proposed device is the highest possible. The use of a single delay device, which counts the fC interval in both half periods, ensures the symmetry of the output voltage. The greatest positive effect when using the proposed device occurs when the frequency of inversion is increased, which is necessary to reduce the size, when the half-time is comparable with the resorption time of minority carriers in the power transistor base. Claims of invention Ryogulirue (1st inverter, consisting of key devices, master oscillator and control device, containing interconnected counting trigger, delay unit and modulator of long duration pulses, and so on the purpose of expanding the control range and improving the symmetry of the output voltage, the input of the delay unit is connected to the output of the master oscillator, and the output is connected to the input of the counting trigger, the synchronizing input of the modulator of the pulse duration and the first inputs of two flax input AND gates, whose second inputs are connected to respective outputs of the flip-flop counting and third inputs - with the output pulse duration modulation of the torus.