SU547765A1 - Arithmetic unit - Google Patents

Claims (2)

This invention relates to the field of computing. Arithmetic devices are known that work with information presented in the form of vectors, intended for solving problems containing a large number of trigonometric functions jl, 2, Гз1. These arithmetic units consist of shear registers, subtractors, and switching units. A disadvantage of such devices is the absence in their set of operations of calculating the reciprocal. The arithmetic unit closest in technical terms to the invention is implemented by the Walder algorithm Y. - Y.tT.X. 1 + 1 1 and 1 X. -X.-TY2 it-f 1 M 1 9- 0.- .. 1 + -I 1) and allows the calculation (.O, (Xf05A-Y S nЛ) . R KVx + arcto LL 1 X In the previous expressions Xj, V 90-) are the coordinates and angle values at the 1st iteration; ./ is a function that shows the direction of rotation and is equal for relations 2.) .- (4) l of relations (3) 1)) 5) is the angular constant, is equal to k is the coefficient of the overall elongation of the vector, equal to the product of the coefficients of the long iterations of c. n (G) i - 2 X, Y, A - initial data; - - iteration numbers, 3, .... This arithmetic unit contains ri shift registers, three totalizers and two commuting units. The outputs of all the bits of the first and second shift registers are connected to the corresponding inputs of the first and second switching units, respectively, the control inputs of which are connected to the first input of the device, the low-order outputs of each of the shift registers to the first inputs of the respective totalizers of the counters, the outputs of which are outputs devices and are connected to the inputs of the higher bits of the same shift registers. The output of the first switching unit is connected to the second input of the second totalizer-subtractor, the second input of the third totalizer-subtractor is connected to the second input of the device, the control inputs of the totalizer-subtractors are connected to the third input of the device. However, the structure of such a device is not adapted to calculate the reciprocal, which is often encountered in solving trigonometric problems. The purpose of the invention is to extend the functionality of the operation of calculating the reciprocal. This is achieved by adding an element I to the arithmetic unit, the first input of which is connected to the output of the second switching unit, the second input to the fourth input of the device, and the output to the second input of the first adder - subtracting the bodies. The drawing shows a block diagram of an arithmetic unit, where 1, 2, 3 shift registers; 4, 5 - switching blocks; 6, 7, 8 - adders-subtractors; 9 - output X; 10 - output Y; 11 - output 0 and 2; 12 - element And; 13 - prohibition entry; 14 - input constants; 15 - entrance 7; 16 - switching input. The arithmetic unit contains three shift registers, three adders — subtracted l, two commutation blocks and element I. The register 1 outputs are connected to the corresponding inputs of the switching block 4, the output of block 4 is connected to the first input of the accumulator-adder 6. The second input of the adder — you 6 connected to the output of the youngest time in the register register 2, and the output to the input of the same register and output 10 of the device. The outputs of register 2 are connected to the corresponding inputs of the switching unit 5, the output of unit 5 to the first input of the element 12 And whose second input is the input 13 of the device. The first input of the adder-calculator 7 is connected to the output of element I 12, the second input to the output of register 1, and the output to the input of the same register and output 9 of the device. The output of the register 3 is connected to the first input of the adder-calculator 8, the second input of this adder - to the input 14 of the device. The input of Registry 3 is the output 11 of the device connected to the output of the adder-subtract 8. The control inputs of all the adders of the readers are connected to the input 15 of the device, and the control inputs of the switching blocks to the input 16 of the device. When solving relations (2) and (3), the device works but the algorithm (1), and when calculating the value, the interaction process is organized - T.T.X 2 1 and XQ-X (0.5 $ lJ (i4i) i - iteration number, -j 1, 2, 3, ..., TL, 7- is the operator, giving such a measurement X, so that when -1 - P value, Z and equal to r + H, Jx, K ,, Z - value the reciprocal of the i – i and iteration (ZQ 1 at ZQ - 1 when). When calculating the OOs (2), the proposed device works as follows. Input 13 is given a resolution signal, the X values are stored respectively in registers 1, 2, 3 From the beginning of the next iteration, e, arriving at input 16 from the control device, switching units 4, 5 connect the corresponding outputs of registers 1, 2 to the inputs of totalizers-subtractors 6, 7 so that the input is received to the input of totalizer-subtractor 7, and the input of the adder-subtractor 6 - the value of X 2). The Y-j value from the output of register 2 is fed to the second input of the totalizer 6, where, in accordance with the value of the operator .j, coming from the control unit to 15, it is summed (subtracted) c. The value from the output of adder-subtractor 6 is written to register 2. The value of X; from the output of the register 1 is applied to the second input of the adder-subtractor 7, where in accordance with, 7 is subtracted (summed) with the input from the output of the element And 12. Value. received at the output of the adder-subtractor 7 is written to register 1, the value 0 from the output of register 3 passes to the input of the adder-subtractor 8, where, in accordance with the subtracted (summed) with the angular constant L, received at input 14 from the memory to the second input of the adder-subtractor 8. The value obtained at the output of the adder-subtractor 8 is recorded in the register 3 and on output 11 enters the device, where it is used for determination. The process is repeated until a predetermined number of iterations are performed. At the end of the section, the results, Up + h 9 9nti can be derived respectively by lines 9, 10, 11. When calculating relations (3), the operation of the arithmetic unit is similar to the work in the calculation mode of relations (2) with the difference that the value of YJ is obtained as a function of the sign taken to the control unit from output 10. When calculating the Z-i value, the values YQ, X and Z are stored in registers 1, 2, 3, respectively, and the input signal 13 of the And 12 element receives a prohibition signal. With the beginning of the next iteration, the following happens. On command from the control device at input 16, the switching unit 4 connects the corresponding outputs of register 1 to the second input of the adder-subtractor 6 in such a way that the input of the adder-subtractor receives the value of Xp 2, which is in accordance with the sum of register 2. The value fj from the output of the subtractor is written to register 2 and fed to the control unit for determining the value at output 10. The value from register 3 is fed to the input of the subtractor 8, where, according to -. Avl s (subtracts) the value 2 falling into the memory device 14 at the input 14. The PP value from the output of register 1 through the adder-subtractor 7 is rewritten to register 1 without changing dreams. At this, the iteration ends and the process repeats until the specified number of iterations At the end of the operation, the result of Zn can be displayed along line 11. The effectiveness of the invention consists in extending the functionality of the arithmetic unit, achieved by slightly increasing the equipment's costs. An arithmetic unit containing three shift registers, three totalizers and two switching blocks, the outputs of all bits of the first and second shift registers are connected to the corresponding inputs of the first and second switching blocks, the control inputs of which are connected to the first input of the device, the outputs of the lower the bits of each of the shift registers are connected to the first inputs of the respective totalizer subtractors, the outputs of which are the outputs of the device and the connection to the inputs of the high-order bits of the same shift registers, the output of the first switching unit is connected to the second input of the second adder-Bitchitel, the second input of the third adder-allocator is connected to the second input of the device, the control inputs of the adder-subtract-m-switch are connected to the power input device, characterized in that, in order to expand the functionality of the device, it contains an element, the first input of which is connected to the output of the second switching unit, the second input is connected to the fourth input of devices, and the output is with the second input of the first subtractor. Sources of information taken into account in the examination: 1. USSR Author's Certificate No. 445042, cl. G 06 F 7/38, 1972. 2. Patent of Great Britain .№ 1331410, cl. G 4A, 1973. aJ.E.VoEder The CORDIC trigonometric comput-ing techn.q, Transactions onFaectron with CompLttprs, YES-8, No. 3, 1959 prototype). to i ... i 760 t t G J4 o-