SU481896A1 - Astronomical time input device in a digital computer - Google Patents

Description

(54) ASTRONOMIC TIME INPUT DEVICE IN A DIGITAL COMPUTER MACHINE

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ow (block not shown) of block 3 counters of large-scale time pulses, the contents of which correspond to seconds, minutes, hours, etc. If necessary, before switching on the digital computer to work, the contents of block 3 of counters of large-scale time pulses from the control panel 6 are installed or to some initial state, or zeroed. In the course of operation of the digital computer, the codes of the executive addresses are sent to the address input 9 of the device, which are analyzed by the address analysis block 5. If the analyzed code is not included in the number of addresses allocated for the block of 3 large-scale counters

time pulses, block 5 address analysis does not issue any control signals. Otherwise, the b; yc 5 analysis of the address issues the son l to the block 4, prohibiting the passage of the counting pulse to the block 3 of the scaling time pulse counters and to the control output 12 of the device, blocking the read pulse to the digital memory, which goes to control input 1 of the device. According to this signal, the switch 8 provides for the appearance at the information output 11 of the device the contents of that count of scaled time pulses of block 3 of counters of scaled time pulses, the number of which is specified by block 5 of address analysis.

The subject of shadows,

An astronomical time input device in a Chiz computer, containing a pulse generator, output, whose course is connected through a serially connected frequency divider and blocking node to the first input of a block of counters, large-scale time pulses, the second (the INPUT of which is connected connected to the inlet, the home of the display unit, and the second output, to the First input of the switch, the information output of which is connected to the informational tricks, of the device, is distinguished by the fact that Improving the reliability of the device, it contains an address analysis block whose input is connected to the address input, the first control output is connected to the second input of the blocking node, the second control output is connected to the second input of the switch, the third input of which is connected to the control input of the device and the third control output is the yen connection with the control output of the device.

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