SU394835A1 - DEVICE OF TELECOMMUNICATION DURING TESTING - Google Patents

Description

The invention relates to the field of telecontrol and control and can be used in the field of automation of production processes.

Devices are known that comprise sensors, logic elements, memory devices, master generators, communication channels and display units.

A disadvantage of the known devices is the low efficiency of monitoring the progress of the test NII.

The aim of the invention is to increase the efficiency and quality of monitoring the production of tests.

This goal is achieved by the fact that in the device a block of a set of numbers, code decoders are connected via logic elements to the inputs of counters (the third counter is connected with a memory device through logic elements).

The drawing shows the scheme of the proposed device.

The device contains a block of dialing numbers 1, a buffer memory register 2, a display unit

3, long-term storage device

4, counters 5-7 pulses, pulse generator 8, frequency divider 9, first, second and third logic circuits “OR 10-12, logical element“ NO 13, decoder of codes 14, input circuits “And 15, first, second, third , the fourth, fifth and sixth circuits And 16-21, output circuits And 22, the first 23 and second 24 buses record information into a memory device and the first 25 and second 26 buses reproduce information recorded in a memory device.

The device works as follows.

In the dialing block 1, the operator produces a decade set of code combinations corresponding to certain indicators characterizing the course of tests of agricultural equipment. Dialed numbers / code combinations through the scheme “OR 11, counter 4, the decoder of codes 14 and the input circuits“ AND 15, arrive every ten days in the corresponding bits of the buffer register 2. After the operator has entered into register 2 all the information relating to to one designated test machine, information is copied from register 2 to long-term memory 4. Long-term memory in the simplest form can be implemented on a dual-tape recorder.

The information from register 2 through the output circuit "AND 22, logical circuit" OR 12 is sent to the counter of the second code 6, for which the signal "And the signal" Understate, opening the last. I.mp) from generator 8 through frequency divider 9, circuit "And 18, circuit" OR 11 is fed to the input of counter 5 and then fed to a decoder of codes 14, which controls the output of information from register 2 by supplying resolving potentials to And 22. The output circuits. In addition, the pulses from the generator 8 through frequency divider 9 are fed through the circuit "AND 18 via bus 24 to the wiring device 4, where they are recorded as decadal marks used as signs of operations during playback by writing to the memory device 4 information.

From the output of the circuit "OR 12, pulses are simultaneously applied to the circuit" AND 20, while no signals are received from this counter from the counter 7, so the prohibition signal from the output of the circuit "And 20 does not arrive. The read emulsions from the generator 8 through the scheme "OR 10 arrive at the counter 6, defining information about one machine, tested at this machine test station, in the durable storage device 4 via the bus 23. Thus, the operator subsequently enters into the device 4 all the information belonging to a whole fleet of simultaneously tested machip.

In the course of work, depending on the specific situation, the operator enters a set of relevant codes in the number set block / buffer register 2 with new information about one of the machines being tested. In this way, a new information about the tested machines is introduced into the memory 4, which reflects the changes in time of all the indicators characterizing the test cycle of agricultural machines.

The information previously recorded in memory 4 is compared with the information received from the operator on each machine. The signal "Playback supplied to the device 4, previously recorded to the bus 25, is fed to the counter 7 and then to the circuit" AND 20.

At the same time, the signal “Reproduction of iHo bus 26 on the circuit“ And 21 is given pulses of sub-second marks. The < 21 < / RTI > scheme opens when a specific code combination arrives at its second input through the bus 25, which characterizes the number of the tested machine. In this case, the signals on bus 26 through the circuit “AND 21, the element“ IET 13 arrive at the counter 5 n and then to the decoder of codes 14, permitting the output from register 2 of the first three senior decades indicating the life of the tested machine, and the circuit “20. If the information derived from the first three leading decades of register 2 coincides with the information, 11stunyupl, via bus 25 through counter 7 to the input of the circuit “And 20, this circuit issues a signal that prohibits the presence of pulses from the circuit 21 and through the element“ ИЕТ 13 and allowing the passage of pulses from generator 8 through the divider Toty 9 through

the circuit “AND 19, the circuit“ OR //, counter 5 to the decoder of codes 14, which ensures the passage of pulses from register 2 to the circuit “AND 20 and counter 6. At the same time, the signal from

The And 20 circuits allow the pulses from the generator 8 to arrive at the reading of the counter 6, and also issues a command to erase the old information relating to this tested machine, which is output from the block

memory and is lost.

New information is introduced in a manner similar to that described on bus 23.

The Playback mode starts by searching for the number of the machine. When triggered

The "And 20" information from counter 7 is rewritten to register 2 through a set of numbers / (the connection of counter 7 to a set of numbers / is not shown in the figure). The erection of information is performed by sub-decadio when there is a specific command. The formation of commands is carried out by pulses on the bus 26 through the schemes "AND 21, the element" IET 13, counter 5 and the decoder of codes 14.

Subject invention

A telecontrol device for the course of a test, for example, agricultural machines, contains an impulse generator connected through a first and a second AND circuit and OR to a read input of one of the counters and a third input of the third and fourth circuits And, the buffer register of the memory, the outputs of which are connected to the display unit and to the first inputs of the output circuits "And the input - through the input circuits" And with the number set block and output codes of the code decoder, the long-term ominayun; her device, the counters and the logic element "NO, characterized in that, in order to increase and efficiency-

the reliability of the device, in it the dialing set unit is connected via the second OR “OR” circuit, the first counter and the code decoder is connected to the second inputs of the AND output circuits, whose outputs

through the third circuit "OR connected to the inputs of the second counter and the fifth circuit" And, the output of which is connected to the input of the logical element "NO n with the enable inputs of the second and fourth circuits" And, the output of which

connected to the output of the logical element "IET and to the input of the second circuit" OR, and the first output of the long-term storage device is connected via a third counter to the second input of the fifth circuit "And, and to the first input of the sixth circuit" And, the other input of which is connected to the second output of the long-term ia device, and the output of the sixth circuit “And connected to the input of the logic element“ NO, the first input of the long-term storage device is connected to the output of the third circuit “And and the input of the second circuit“ OR, the other input of the storage device CTBA connected to the output of the second

pulse counter, and the write resolution bus is connected to the second inputs of the first and

AND.

third schemes

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