SU1737499A1 - Data display device - Google Patents

Description

An analog synthesized on the basis of a pulse distributor, made either on a counter with a decoder, or a shift register with control elements on logic elements and triggers, or, as in the proposed device, on logic elements, triggers and single-oscillators.

The control and synchronization unit 24 contains elements 40,48 and 49 NOT, elements 41,43 AND, triggers 42,46,54 and 55, elements 44,45,47,50,51 and 56 AND-NONE, delay element 52, driver 53 pulses

Counter 25 contains a binary counter 69 columns, element 70 AND, a binary-decimal counter 71 rows, a binary counter 72 pages, clock input 73, information inputs 74 and 76 counters 69 and 71 columns and rows, installation input 35 counters 69 and 71 columns and lines, reset input 75 of counter 69 and transfer of counter 71 to the next state, outputs 77-79 of counters 69.71 and 72 volts, lines and pages.

The device has three modes of operation: a write mode in which the corresponding information is recorded in the memory cells of the main memory blocks 5 and 18, a display mode when periodic information is read from the memory cells of the main memory unit 5 and in accordance with it the display on the screen of the matrix indicator of 3 characters, words (commands) or histograms and information editing mode.

Consider the operation of the device in the information recording mode using the example of writing words (commands), assuming that the first word will be displayed in the upper left corner of the indicator screen, i.e. counter 25 is in the zero state. In this mode, the trigger 19 is in the cocked state and the address code of the familiarity of the matrix indicator 3 is supplied from the outputs of the counter 25 through the switch 14 to the information inputs of the register 7.

The address code of the information of the corresponding word (command) is fed to input 36 The code of the address of the information (Fig. 4a) and from the input to the address inputs of the RAM block 18, and the corresponding information code of the word (command) is fed to input 32 of the Device Information Code (Fig .4b) and from the input to blocks 22 and 23 of the permanent memory, where they are transformed, respectively, into the initial address of the memory cells of the permanent memory block 11, in which sequences of character codes constituting the corresponding words (commands) are recorded, and in the code of the number equal to the number

characters in the word (team). From the input 34 of the Device Information Record, pulses are received (Fig. 4h), tied to the synchronization frequency of the device and the control and synchronization unit 24 (input 33, Fig. 4b), i.e. the external device must be synchronized with the same frequency. For each of these pulses, the control and synchronization unit 24 removes the zeroing from the counter 15 (FIG. 4t) and generates a pulse to the gating input of the comparison unit 13 (FIG. 4p), which in turn performs a check before writing the characters of each word in block 5 RAM on

5, the capacity of the given word in the remaining lines of the familiarity by comparing the remaining characters in the line with the length of the word. As a result, the output of the comparison unit 13 is formed or does not form an impulse to set the counter 25 (fig. 4f), which is a serial connection of the column counter, the row counter and the page counter and, in the case of word length (the code from the block 23 is constant

5 memory) of the remaining number of familiarity in the row (inversion of the column counter code from block 17 of the elements NOT, fig 4u), an impulse is formed that sets the column counter to the zero state, and

0 line count translates to the following state. During the action of the pulse supplied to the gating input of comparator unit 13, pulses from input 34 Recording device information (Fig. 4b) starts and a preprogramming pulse is generated by control and synchronization unit 24 in counter 15 (Fig. 4i), which records the initial cell address of block 11 constant

0 memory storing the first character of this word. The recorded address from counter 15 is fed to the inputs of the comparison unit 12 and to the address inputs of the permanent memory unit 11, at the output of which the code of the first character appears

5 words (commands), arriving at the information inputs of the RAM 5. The second block 13 compares the code from adder 14, which represents the sum of the codes of the starting address and the number equal to the number of characters in the word (command). At the end of the time allocated for capacity (the end of the pulse supplied to the gating input of the comparison unit 13, figr), the control unit 24 and

5 synchronization produces four time-shifted pulse sequences, the number of pulses in which is equal to the number of characters in the word (command), and in time arrives at the inputs as follows (Fig. 4k, l, m, n).

The first is generated and received a pulse from the sequence fed to the increment input of the counter 25 (Fig. 4k), and in the case when the word (command) should be displayed from the beginning of the line, i.e. the column counter is in the zero state, the units from the block 17 elements do NOT go to the fourth inputs of the control and synchronization block 24, to the n-input element IS –NE (l is the number of bits of the column counter), the signal from the output which is blocked in this case, the first pulse of the sequence and it is not fed to the input of the increment counter 25.

A second pulse is generated and arrives from the sequence supplied to the recording entry of the register 7 (Fig. 4), at which the address arriving at the information inputs through the switch 14 from the counter 25 is rewritten into the register 7.

The third one generates and receives a pulse from the sequence supplied to the input of the switch 6 and to the input of the information recording of the operational memory unit 5 (FIG. 4m), through which the code of the first character of the word (command) arrives at the information inputs of the operational memory unit 5 block 11 of the permanent memory is recorded in the memory cell at the address received from register 7 via switch 6, which commutes this input to the output for the duration of the pulse at the control input.

The fourth is generated and received a pulse from the sequence supplied to the increment input of counter 15 (fig.4n), by which the counter is transferred to the next state, and the second character code from the block 11 is received on the information inputs of the RAM 5. this memory.

This completes the write cycle in the memory unit 5 of the same character of the word (command). Further, the write cycles are repeated — a second pulse is generated and received from the sequence fed to the clock input of the counter 25, etc., so many pulses are generated in each sequence, how many characters are in the word (command) and with the arrival of the last pulse from the sequence fed to the clock input of the counter 15, which is transferred to the next state, the comparison unit 12 generates a pulse

(Fig. 4c), according to which the control and synchronization unit 24 begins to generate a pulse to the input of zeroing the counter 15 (Fig. 4t). This ends the recording of the first word (command), which is displayed in the upper left corner of the screen, i.e. from the beginning of the first line.

Fig. 4 shows diagrams of the recording of three words (commands): the first of the seven characters is displayed from the beginning of the first line; the second of the five characters is displayed after the first in the first line; The third of the five characters does not fit in the first line, therefore is transferred and displayed from the beginning of the second line.

The writing to the RAM 18 is performed as follows. The address inputs receive the address code of the information cells of the external device from input 36, the information address code (FIG. 4a), and the information inputs receive the address codes of familiarity from the output of the counter 25. The synchronization frequency of the device and the control and synchronization unit 24 from the input 33 Synchronization of the device ( figv) is fed to the increment input of the counter 29, the frequency sequences from the outputs of the second, third and fourth bits.

which (the output of the first bit is not used, fig.4g, e, e, g) is fed to the inputs of the element 27 OR NOT, the output signal of which zeroes or clears the zeroing of the trigger 26 (fig.4o).

The trigger 26 is triggered by the input from the pulse recording information of the first character of the word (command) from the corresponding output of the control and synchronization unit 24 (Fig. 4m) during the zero-out at the input (Fig. 4o). As a result of this, at the inverse output of the trigger 26 a pulse of recording information is formed in the operational memory unit 18 (Fig. 4p).

When writing to blocks 5 and 18 operational

the memory of individual characters and histograms the device operates in the same way as when writing words (commands) with the following.

When writing individual characters, like

words, the control input 31 selects the recording method of the device is given a logical zero signal, and when recording histograms - a logical unit, which is achieved by switching the memory areas of the fixed memory block 11, in which information about the signs and words (commands) in one area and histograms in another.

When writing individual characters for the codes corresponding to these characters in block 23, the unit code is entered, which corresponds to the number of characters (a word from one character).

When recording histograms for all 100 values of the input value, possible to display (00-99) on the indicator screen, in block 23, a code of fifteen is entered to ensure that each new value of the input value, however small it is, displayed with a new line. On the indicator screen, tens are displayed as a number of required characters in a row, for example, letter w, equal to the number of tens of the input value, and in the following familiarity lines, numbers are displayed, the first of which corresponds to tens, i.e. the number of goals, and the second displays and corresponds to the units of the input value. The remaining free familiarity lines are filled with spaces. Such a display, clogged with the field of familiarity, gives the convenience of visual perception of the total change in the input value, and the numbers provide the convenience of reading specific values of this value.

In block 11 of the persistent memory, in the memory area allocated for histograms, sequences of clogged character codes, numbers, and spaces are included, which are the sum of all 100 values of the input quantity.

In the mode of displaying information at the control input of the switch 6, the control and synchronization unit 24 maintains the level of the logical unit, which determines the passage of the address signals from the output of the meter unit 8 through the switch 6 to the address inputs of the main memory unit 5.

The generator 9 starts a block of 8 meters that synchronizes the operation of the device in the display mode. The digital code from the third outputs of the block of 8 meters goes to the scanner 4, which in a certain sequence switches the scanning electrodes of the matrix indicator 3. The address from the fifth outputs of the block of 8 meters, coming through the switch 6 to the address inputs of the main memory unit 5, outputs from it the digital code of the character recorded in the memory block 5 earlier. Block 1 of the permanent memory converts this digital code into a graphic character code. The sequence number of the vertical fragment of the character output from the block 1 of the permanent memory at any given time is specified by the digital code with

The first output of the block is 8 counters. The clock signal from the second output of the block 8 counters records a fragment of the sign in the necessary part of the register 2, the output signals of which are control for the information electrodes of the matrix indicator 3. Each familiarity of the matrix indicator 3 corresponds to its address in the main memory unit 5.

0 Suppose that the scanning electrodes are arranged vertically and the familiarity matrix consists of 35 indicator elements (5 vertical bars of 7 indicator elements each). In this case

5, the meter block 8 controls the operation of the device as follows.

Block 4 sweep selects the first electrode of the first column of matrices familiarity. At the same time, the block of 8 counters by 0 therefore polls the block 5 of the operational memory at the addresses corresponding to the first column of the familiarity from the address of the upper one to the address of the lower sign. The information codes recorded in block 5 of the operational memory, affecting the block 1 of the permanent memory, output the graphic codes of the first fragments of all the characters of the first column, which are then written into register 2 in such a way that the first fragment

The top 0 character is in the part of register 2 that controls the indicator electrodes of the top matrix matrix 3, the first fragment of the second one is in part

5 registers 2 controlling the indicator electrodes of the second from the top of the familiarity, etc. Information output from memory block 5, its conversion in block 1 of permanent memory and filling of the register

0 2 is carried out in a time that constitutes a smaller part of the selection period of the scanning electrode of the matrix indicator 3. Most of the time, the information recorded in register 2 is static and excites

5 necessary indicator elements of the matrix indicator 3.

Next, block 8 counters using block 4 sweep selects the second vertical electrode of the first column familiarity

0 matrix indicator 3, polls the memory block 5 at the same addresses corresponding to the first column of characters. The block 1 of the permanent memory from the block of 8 counters at this time is fed the code of the second

5 fragments of characters that fill the register 2. In the same way, the third, fourth and fifth fragments of all characters are displayed when selecting the third, fourth and fifth electrodes of the familiarity column.

When displaying the second column of characters, the first, second, third, fourth, and fifth electrodes of the second column are alternately selected. The memory unit 5 is polled five times at the addresses of the second column, and each time the first, the second, third, fourth, and fifth fragments of characters, which are then recorded in register 2 and excite the necessary indicator elements of the matrix indicator 3. Thus, I scan the image frame, successively uzhdayuts dates of all display elements and familiarity on the matrix display 3 displayed information recorded in the block random access memory 5.

Consider the operation of the device in the mode of editing information on the example of editing by individual words (commands).

The device is transferred to the information editing mode by applying a pulse through the control input 37. The device marker (fig. D) causes reset of the trigger 19 and the appearance of a logic unit signal at the inverse output of the trigger 19 (fig. B), which is fed to the input of the element 28 - NOT and thus allows the passage of positive impulses of changing the address towards increasing or decreasing the address code of the information in the external device (input 36, fig.b) from the control input 38 Information address increment or from the control input 39 Address decrement Information (fig.bv) through the element 30 OR and the element 28 NAND to the input of the pulse former 21, which from the leading edges of these pulses outputs through the element 20 And the negative write pulses to the register 7. The code inputs to the information inputs of the register 7 addresses of the familiarity, corresponding to the first character of a word (command), from the memory block 18 through the switch 14. The signal of the logical unit from the inverse output of the trigger 19 through the installation input of the marker control block 10 allows it to work. The marker control unit 10 allows determining the state of the address register 7. The information inputs of the marker control unit 10 are connected to the corresponding outputs of the address register 7, and a pulse is periodically sent to the reset input. A reset from the sweep block 4 is recorded. then pulses are delivered to the clock inputs at frequencies corresponding to polling of the RAM 5 in columns and rows. From the output of the marker control unit 10, the block 1 of the permanent memory receives a logical zero signal, highlighting all points of familiarity with the address corresponding to the state of the address register 7. Thus, the marker signal on the screen of the matrix indicator 3 generated by the block 10 of the control of the marker, when the address of the information changes (FIG. B), it will move along the first characters of the names of the words (commands). After that on the setup input 35 Record mark

5, the counter 25 is given a pulse (FIG. 10), which records the address of the familiarity of the first character of the desired word (command) from the RAM block 18 and triggers trigger 11, the logic one signal from the direct output of which switches the switch 14 so that The information inputs of the register 7 are connected to the outputs of the counter 25, while the marker signal on the screen of the matrix in5 indicator 3 goes out. Then, the information information of the device information code (Fig. 56) is fed to the information inputs 32 of the code of the desired word (command) and further along the control input 34

0 pulse (FIG. 5d) g for which recording is performed in blocks 5 and 18 of the RAM, as previously described in the information recording mode.

In the same way, the recorded information is edited both in the form of individual characters and in the form of histograms. The control and synchronization unit 24 operates as follows.

The impulse from input 34 Recording information comes to the block at the input of delay element 52 (fig.4z), from which the delayed impulse is the output impulse of the block (output 62, fig.4i), recording information in counter 15, and on the rear

5, the front of the input pulse (fig. 4z) triggers 46 and 55 are triggered, zeroing (output 64 of the block) is removed from counter 15 (fig.4t) and a pulse begins (output 67 of the block) to the input

0 gating of the comparison unit 13 (FIG. 4p). Positive pulses of the clock frequency from the input 33 Synchronization of the device and the block arrive at the first inputs of the elements 41 and 43 I. And also to the clock

5, the trigger input 42, from the direct and inverse outputs of which paraphase meanders are removed to the second inputs of elements 41 and 43, respectively, at the outputs of which two shifted pulse sequences are formed, and from the output of element 41 And the sequence to the insertion input of counter 15 (output 63 blocks) is formed with the arrival of a signal from the direct output of flip-flop 54, which, in turn, is switched on according to the latch-flip-flop pattern and is transferred to a single state on the falling edge of the first one that passes through the element 47 AND IS NOT of a pulse elnosti with element 43, passing through the element 47 which AND-NOT signal to provide a straight - direct output of the trigger 46, which is inserted into a unit consisting of the rear edge of the pulse from the input terminal 34 of recording information. The first pulse from element 47 AND-NOT resets the trigger 55 via the zero input, which ensures the termination of the pulse formation (block output 67) to the strobe input of the comparison block 13 (fig.4r). The sequence of positive pulses from the output of the element 49 does not produce with each pulse the start of the imaging unit 53 of a pair of pulses delayed relative to the triggering and shifted relative to each other (FIG. 4L, outputs 66 and 65 of the block). The pulses at outputs 66 and 65 of the block, respectively, record the address in register 7 and record information at this address in block 5 of the RAM. The sequence of positive pulses from the output of element 49 is NOT also fed to the input of element 50 AND-NOT, to the second input of which a signal is sent from element 45 AND-NOT corresponding to one when at the input of this element at least one of the input signals (inputs 58-61 ) coming from the output of block 17 of the inverters is equal to zero (the column counter is not in the zero state), as a result of which the sequence through the element 50 AND-NOT and through the element 56 AND-NOT enters the output 68 of the block (the increment signal of the counter 25 ), and when the signal from the element 45 NAND is equal to zero (the column counter in the zero state), the first pulse of the sequence does not pass through the NAND element 50 to the block output 68 and the column counter entering counter 25 does not change its state. A single signal from the direct output of flip-flop 54, which occurred on the falling edge of the first pulse of the sequence from element 49 NOT, as well as the unit from element 48 does NOT allow the second pulse of the sequence to pass through element 51 AND-NOT to element 56 AND-NOT and to output 68 block, causing the column counter to change its zero state to one and the element 45 AND-NOT allow the passage of the pulses of the sequence through the element 50 AND-NOT for further work. With the end of the recording of the word (command), the comparison unit 12 begins to generate a single signal (Fig. 4c), which is fed to the input 57 of the control and signaling unit 24 and to the first input of the NAND element 44, as a result of which a zero signal is generated at the output of this element , null triggers 46,54, and from the inverse output of flip-flop 46 is removed at the output 64 of the block an nulling potential at the counter 15 (FIG. 4 t), zeroing which leads to the end of a single signal at the output of the comparator 12, as well as to the end of the nulling the signal from the output element 44 AND NOT on triggers 46 and 54.

The elements of the block were set to their original state to receive and display the next word (command). Negative pulses are received from the second and third inputs of the NAND element 44 from the NOT element 40, whose input is connected to the output of the AND element 41, and from the delay element 52, which block possible interference to the first input from the output of the comparison unit 12, which occurs in the result of transients when recording information in the counter 15 and during its increment.

The counter 25 operates as follows.

The use of binary counters as counters 69,72 columns and pages is due to the fact that in the indicator IMG-1-03 the screen has 16 columns and 4 pages of information, and the use of a binary-decimal counter as a counter of 71 rows is due to the fact that in the indicator IMG-1-03 screen has 10 lines.

In the recording mode, the corresponding counters of counter 25 carry out the counting of columns, lines and pages with recording information from the outputs of the counter 69 columns and the counter 71 lines in register 7 and information about the address of the first characters of the words (commands) in the RAM 18. In the same mode, a negative pulse from the output of the comparison block 13 on the reset input 75 of the counter 25 resets the counter of 69 columns and through the element-70 AND 71 counts the row into the next state.

In the information display mode, the counters 69,71,72 are in a static state.

In the information editing mode, after selecting the desired address of the word (command), information inputs 74 and 76 of counters 69 and 71 are set to the address code of the first character of the word (command), and the setting input 35 of the counter 25 records the code to it. Then, after applying a pulse to the input 34. Recording information of the control and synchronization unit 24, a series of pulses is fed to the input 73 of the counter 25, the number of which is equal to the number of characters in the word (command), while the counter of the counter 25 counts this number of pulses.

Claims (1)

Thus, the proposed device, by storing the necessary addresses of familiarity in the process of recording information both with individual characters and codes of the corresponding words (commands) or histograms, and then during the editing process, reading them to highlight with a marker signal on the screen of the matrix indicator allows to increase speed editing the displayed information. Claim 1. A device for displaying information containing four blocks of permanent memory, two counters, a control and synchronization block, an adder, two comparison blocks, two registers, a clock generator, a block of counters, a scanner, a display unit, the first the switch, the NOT elements, the first address input of the first block of permanent memory is the first control input of the device, the second address input is connected to the output of the first counter and the first information input of the first comparison block, and the output from The main input of the first memory block, the first address input of which is connected to the output of the first switch, the second address input to the first output of the second counter, and the control input of the first memory block is connected to the first output of the control and synchronization unit. The first input of the first switch, the output of the first memory block is connected to the first address input of the second permanent memory unit, the second address input of which is connected to the first output of the counter block, and the output is connected to The first input of the first register, the control input of which is connected to the second output of the counter block, and the outputs are connected to the first information inputs of the display unit, the second information inputs of which are connected to the first outputs of the scanner, the information input of which is connected to the third output of the counter the input of which is connected to the output of the clock pulse generator, and the fourth output - to the first information input of the first switch, the second information input of which is connected to the output v first register the input of the control and synchronization unit is connected to the first information input of the second comparison unit and with the output of the NOT elements whose inputs are connected to the second output of the second counter, the first and second control inputs of the control and synchronization unit are the second and third control inputs of the device, respectively; the information input of the control and synchronization unit is connected to the output of the first comparison unit, the second information input of which is connected to the output of the adder, the first information input of which connected to the information input of the first counter and to the output of the third block of permanent memory, the address input of which is the information input of the device and connected to the address input of the fourth block of permanent memory, the output of which is connected to the second information inputs of the adder and the second comparison unit, output which is connected to the reset input of the second counter, the setup input of which is the fourth control input of the device, the clock input of the second counter connected to the second output of the control unit synchronization, the third, fourth and fifth outputs of which are connected respectively to the installation, clock inputs and the reset input of the first counter, the sixth output of the control and synchronization unit is connected to the control input of the second comparison unit, which is the speed of editing the displayed information, a logic block, an AND element, a second switch, a marker control block whose output is connected to the third address input of the first permanent memory block, and a reset input are entered into it OC - to the second output of the scanner, clock and information inputs of the marker control unit are connected respectively to the fifth output of the counter block and to the output of the second register, the address input of the second RAM block is the address input of the device, the information input of the second RAM block is connected with the second output of the second counter and with the first information input of the second switch, the control input is connected to the first output of the logic unit, and the output to the information input of the second counter and to The second information input of the second switch, the control input of which is connected to the second output of the logic unit, and the output - to the information input of the second register, the control input of which is connected to the output of the And element, the first input of which is connected to the third output of the logical block, and the second input with the seventh output of the control and synchronization unit, the first output of which is connected to the first input of the logic unit, and the first control input - to the second input of the logical unit, the fourth output of which is connected to nym marker input control unit, and the third, fourth and fifth inputs of the logical block are respectively a fourth, fifth and sixth inputs of the gate device. 2, Device pop. 1, characterized in that the logical block contains the element AND-NOT, pulse shaper, the first trigger, the third counter, the element OR-NOT, the second trigger, the setting the input of which is the first input of the logic block, the inverse output of the second trigger is the first output of the logic block, and the reset input is connected to the output of the OR-NOT element, whose inputs are connected to the outputs of the third counter, the clock input of which is the third input of the logic block, the second the input of which is connected to the installation input the first trigger, and the fourth input to the reset input of the first trigger, the fifth input of the logic unit is connected to the first input of the NAND element, and the second output to the direct output of the first trigger, the fourth output logic block is connected to the inverse output of the first trigger and to the second input of the NAND element, and the third output is connected to the output of the pulse former, the clock input of which is connected to the output of the NAND element. , Figure 2 P 25 Fig.Z DC -ib DC fe 1JlanJLRLJShLLJ JgnAllJlshshg d e well b 2C Sc 2x: jh. / -L -w-. -0 „7U e T F Fi & 5 7GT Vi.