SU1749837A1 - Device for measuring rotational speed - Google Patents

Abstract

The invention relates to measurement technology and can be used to measure the angular velocity in monitoring and control systems. The purpose of the invention is to improve the measurement accuracy. The measurement is performed using electronic units, and using one generator as a reference, rotational frequencies are measured both below and above the threshold value of the frequency at which the number of generator pulses counted over the measured period is the base value. It is possible to change the number of measured periods & D with a step of 2K (, 1.2 ....). 1 il.

Description

The invention relates to measurement technology and can be used to measure the angular velocity in monitoring and control systems.

The purpose of the invention is to improve the measurement accuracy.

The drawing shows the functional diagram of the proposed device.

The device for measuring the rotational speed contains a sensor 1, a pulse shaper 2, a reference frequency generator 3, a frequency grid shaper 4, a frequency decrement count 5, a time interval counter 6, a result counter 7, an input pulse counter 8, a shift counter 9, multiplexers 10 -12, memory registers 13-16, trigger 17, AND circuit 18, adder 19, switch 20, difference unit 21, display unit 22, control unit 23, shift register 24.

The device works as follows.

Sensor 1 associated with the shaft generates pulses whose period is equal to the period of rotation of the shaft. On the leading edge of these pulses, the shaper 2 generates short pulses synchronized with the pulses of the generator 3. The generator 3 runs continuously, and its output pulses with a frequency of 2F arrive at the input of counter 4, at the outputs of which the frequencies F. F2, RL, Fe and t are formed .d and control unit 23, which synchronizes the operation of all frequencies of the circuit.

By the arrival of the first pulse from the sensor 1 counters 4-6. 8, 9 and the trigger 17 are in the zero state, the initial setup code is written to the shift register 24.

After the appearance of the first input pulse, zero signal levels at the control inputs of the multiplexer 10 provide the connection of the highest output frequency from the output of counter 4 to the input of counter 6.

with

WITH

2

S 00 O)

Vj

Thus, the counter 6 at the beginning of the measuring interval counts the pulses with a frequency F.

At time ti, the value of a logical unit, i.e. it overflows. This state is detected by the AND 18 circuit. The appearance of the signal at the output of the AND 18 circuit causes the trigger 17 to switch. Writing the number 1 to counter 5 and shifting the contents of the register 24 by one bit to the right, which is equivalent to decreasing its contents by 2 times. The output signal of the trigger 17 sets the value of the logical unit in the high-order bit of counter 6, and this state does not change further until the trigger is reset. The code number 1 of the output signal of the counter 5 connected to the control inputs of the multiplexer 10 connects to the counting input the counter 6, the counter 4 with the frequency of the signal F / 2; Next, the counter 6 continues to count the pulses until the bits are filled with units of all bits except the high one, which is forcibly held in one state by the trigger 17. The filling with bits of all bits The counter b outputs lead to the triggering of circuit 14–18, recording one more unit into counter 5, which leads to a decrease in the frequency of pulses at the counting input of counter 6 by another 2 times, and then the process repeats until the end of the period of the output signal of sensor 1.

If by the time of arrival of the second impulse of the sender 1 in the higher bit of the counter b the value of the logical unit does not appear, then to ensure the specified accuracy, the counter 6 continues to fill. The second pulse from the sensor 1 is fed to the counting input of the counter 8.

At the beginning of the measured interval, when logic level zero levels are supplied to the control input of the multiplexer 11 from the output of counter 9, the output of the counter 8 with the weight value 2 is connected to the counting input of counter 9.

At the end of the second period of the signal from sensor 1, one more unit is recorded in counter 8, and at its output with weight value 2 a level of logical one is set. The unit from the output of multiplexer 11 is recorded in counter 9; Setting the code number 1 on the control inputs of multiplexer 11, fed from the input of counter 9, connects to its counting input counter 8 with a weighing value of 4. Pulse From the output of multiplexer 11, shifts the contents of register 24 by one bit to the left, equivalent to its doubling. If at the moment of appearance of the pulse at the output of multiplexer 11, the highest bit of the counter b is set to a logic zero level, then the counting continues to the next

the pulse at the output of multiplexer 11, i.e. the duration of the four periods of the input signal will be measured, and the contents of the shift register will be shifted another bit to the left. So the amount

the measured periods are doubled until the level of the logical unit is established in the higher bit of counter 6.

After the higher level of the counter B is set to the level of a logical unit, with the appearance of a pulse at the output of multiplexer 11, the counting stops. Thus, 2k periods of the input signal will be measured.

On a signal from the control unit 23, the contents of the counter 6 are written to the register 13, the contents of the counters 5 and 9, having passed through the subtractive device, are written to the register 14, and the contents of the register 24 through the switch 20 will be written to the register

1 b, all the counters and trigger 17 are set to the zero state, the value of the initial setup is written to the shift register, and a new measurement cycle is started.

After the measured time interval is recorded in register 13, the difference in the number of measured periods of the input signal and the number of frequency drops is recorded in register 14, and the value of the initial setting is entered in register 16, the process of converting the measured time interval to the rotation frequency begins by converting the contents of registers 13 and 16 with the recording of amounts: l in the register

16, before the occurrence of a single level in the bit of the multiplexer 12, which is determined by the code recorded in the memory register 14. The number of these summations is counted in counter 7 and is equal to the frequency

rotation The conversion takes place according to the formula "

50

 (N - NHy) 22 2P F

where n is the frequency of rotation at the required scale;

N is a number in binary code; Mnu code the initial installation, written in the shift register;

k - the number of measured periods;

p is the number of frequency drops.

When the level of the logical unit is controlled by the multiplexer 12, the summation stops, the result of the conversion from the counter 7 is written to the memory register 15, from where it goes to the display unit 22. Counter 7 is zeroed out and the conversion part of the device is ready for operation again.

Claims (1)

An apparatus for measuring rotational speed, comprising a sensor, a reference frequency generator, a trigger, first, second and third counters, a control unit, a first multiplexer, first and second memory registers, an AND circuit, an indication unit, characterized in to improve measurement accuracy, the fourth, fifth and sixth counters, the second and third multiplexers, the third and fourth memory registers, the adder, the switch, the difference unit and the shift register, and the reference generator output are entered into it frequency is connected to the input of the first counter, the first input of the pulse former and the first input of the control unit, the second input of the pulse former is connected to the output of the sensor, and the output is connected to the second input of the control unit; the output of the first counter is connected to the first input of the first multiplexer, the second input of which is connected to the output of the second counter, and the output with the third input of the control unit, the first input of the difference unit is connected to the output of the second counter, the second input to the output of the fifth counter, and the output to the first input of the second register memory input of the fifth counter is connected to the output of the second multiplexer and the fourth input of the control unit, the first input of the second the multiplexer is connected to the output of the fourth counter, and the second input is connected to the output of the fifth counter, the second input of the second memory register is connected to the first output the control unit and the output to the first input of the third multiplexer, the second input of which is connected to the output of the adder and the first input of the switch, and the output to the fifth input of the control unit, the output of the AND circuit is connected to the sixth input of the control unit, the input of the second counter and the trigger input The output of which is connected to the first input of the third counter, the second input of which is connected to the second output of the unit control, the first output is with the seventh input of the control unit, and the second output of the third counter is connected to the first input of the first memory register and the input of the AND circuit, the second input of the first memory register connected to the third output of the control unit, and the output to the first input of the adder, the second input of which is connected to the output of the fourth memory register, the first gathering of which is connected to the fourth output the control unit, and the second input - to the output of the switch, the second input of which is connected to the input of the sixth counter and pin1 of the output of the control unit, and the third input is connected to the output of the shift register, the input which is connected to the sixth output of the control unit, the seventh output of which is connected to the input of the fourth counter, the eighth output is connected to the first input of the third memory register, the second input of which is connected to the output of the sixth counter, and the output of the third register is connected to the input of the display unit.