SU1629943A1 - Device for checking synchronizer lead time - Google Patents

Abstract

The invention relates to electrical engineering. The purpose of the invention is to improve the measurement accuracy by taking into account the real time value of the automatic shutdown response. At the time the synchronizer 1 triggers, the triggers 2 and 5 are set to one. At the outputs of the coincidence circuits 8 and 9, single pulses with a pulse frequency of the generator of 7 pulses appear. These pulses arrive at the inputs of the reverse and forward inputs of the counter 10 In the event that the synchronizer advance time coincides with the response time of the switch, there is no signal at the input of the decoder 11. If the lead time is different from the switch trigger time, a signal of the corresponding polarity 2 or less appears at the output of the decoder.

Description

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The invention relates to electrical engineering and can be used in the process of setting up synchronizers with a constant lead time.

The aim of the invention is to improve the measurement accuracy of the device by taking into account the actual value of the time of operation of the circuit breaker.

FIG. 1 shows a block diagram of the device; in fig. 2 - time dependences, explaining the principle of the proposed device.

The device (Fig. 1) contains a synchronizer 1, the first trigger 2, a beat generation voltage generating unit 3 with inputs for connecting to the mains voltage and a generator, a pulse shaper 4, a second trigger 5, a circuit breaker sensor 6, a pulse generator 7, the first 8 and the second 9 coincidence circuits, a reversible counter 10, a decoder 11, an indicator 12, a zero setting bus 13 and a key 14.

The output of synchronizer 1 is connected to the single inputs of the first 2 and second 5 triggers, the first and second inputs of the unit for measuring the voltage difference of the network voltage and the generator 3 are connected to the network voltage and the generator, the output is connected to the input of the driver 4, the output of which is connected to the zero input first trigger 2.

The output of the circuit breaker sensor 6 is connected to the zero input of the second trigger 5, the output of the first trigger 2 is connected to the first input of the first coincidence circuit 8, the output of the second trigger 5 is connected to the first input of the second coincidence circuit 9, the output of the pulse generator 7 is connected to the second inputs of the first 8 and the second 9 coincidence circuits, the output of the first coincidence circuit 8 is connected to the countdown input of the reversible counter 10, the output of the second coincidence circuit 9 is connected to the forward count input of the reversible counter 10, the outputs of which connected to the respective inputs of the decoder 11, the outputs of the decoder 11 are connected to the corresponding inputs of the indicator 12.

Bus 13 installation zero is connected to the input of the key 14, the output of which is connected to the zero input of the reversible counter 10.

The device for setting the timing advance of the synchronizer (Fig. 1) operates as follows.

The network voltage and the generator are fed to the first and second inputs of the measuring unit of the phase difference of the network voltages and the generator 3, the output of which is the voltage Us with an amplitude proportional to the phase difference of the network and generator voltages (Fig. 2).

This signal is fed to the input of the imager of 4 pulses, at the output of which a single impulse LU appears at the moment when, i.e. at the moment of equality of the phases of the mains voltage and the generator.

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These single pulses arrive at the zero input of the first trigger 2, which in the zero state and at its output is a logical zero (Lb) signal. Since the synchronizer 1 has not yet triggered, at its output - the voltage Ui of the logical zero, which is fed to the single inputs of the first 2 and second 5 triggers - at their outputs, the signals of the logical zero U2, Us. At the output of the generator 7 pulses, single pulses are generated that arrive at the second inputs of the first 8 and second 9 coincidence circuits, but since their first inputs are a logic zero signal, then the outputs of the first and second coincidence circuits are logic zero signals (Us , Uq). The up / down counter 10 and the decoder 11 do not change their state; at the output of the indicator 12, it is zero.

At the moment the synchronizer 1 triggers, a single pulse appears at its output

0 Ui, which arrives at the single inputs of the first 2 and second 5 triggers and sets them to the single state. In this case, the signal of the logical unit U2, U5 appears at the output of the first 2 and second 5 triggers. The signal of the logical unit from the outputs of the first 2 and second 5 triggers is fed to the first inputs of the first 8 and second 9 coincidence circuits, and at their outputs there appear single pulses with a frequency equal to the frequency of the pulses at the output of the generator 7 pulses

0 (voltage Us and Ug). In this case, single pulses from the output of the first circuit 8 of coincidence will be fed to the input of the counting counter of the reversible counter 10, and single pulses from the output of the second collecting circuit 9 to the input of the direct count of the reverse

5 of the counter 10, therefore the reversible counter 10 of its state does not change.

Assume that during operation, the response time of the circuit breaker is increased. Then (as shown in Fig. 2), the circuit breaker closes later than the phases of the grid and generator voltages coincide.

In this case, at the moment at the output of the driver of the 4 pulses, a signal of the logical unit W appears, which arrives at the zero input of the first trigger 2 and sets it to the zero state.

At the same time, at the output of the first flip-flop 2, a logic zero signal U2 appears, which arrives at the first time of the first coincidence circuit 8 o and the logic zero signal IJ8 is set at its output.

Single pulses do not arrive at the reverse count input of the reversible counter 10; they continue to arrive at the direct count input, therefore the reversible counter 10 begins to sum the number of pulses arriving at its direct count input.

After a time, the generator circuit breaker closes and the output

0

The sensor of the circuit breaker circuit breaker 6 appears in the signal unit Ue, which arrives at the zero input of the second trigger 5 and sets it to the zero state.

At the output of the second flip-flop 5, the logical zero signal U, which is fed to the first input of the second coincidence circuit 9, appears, at its output a logical zero signal appears, which arrives at the direct count input of the reversible counter 10, the pulse count stops.

The reversible counter 10 records the number of pulses corresponding to the on-time of the on-off switch r, which is appropriately converted by the decoder 11 and displayed by the indicator 12. Since the number of single pulses input to the direct account of the reversible counter 10 is greater than the number of single pulses, arriving at the input of the counting account, at its output a positive number, which is also recorded by the indicator.

In this way, information is obtained that the lead time of the synchronizer should be increased by the value of -c.

If the generator circuit breaker closes before the voltage of the mains and the generator coincides, the number of pulses entering the countdown input of the reversible counter 10 will be greater than the number of pulses entering the forward counting input, and its output is a signal corresponding to the value of m with a negative sign, which is also recorded by the indicator 12.

In this way, information was obtained that the advance time of the synchronizer is greater by the amount of t than is required and should be reduced.

In order to return the device to its original state, it is enough to close the key 14. In this case, the signal from the bus 13 of the zero setting goes to the zero input of the reversible counter 10 and sets it to the initial state, after the key 14 is closed, the device is again ready for operation

Claims (1)

Invention Formula A device for controlling the timing advance of a synchronizer, comprising a beat voltage shaping unit with inputs P for connecting to the network voltage and generator, pulse shaper, first and second triggers, first and second coincidence circuits, set zero bus, key, pulse generator, counter with output decoder, output indicator 5 of the decoder, the output of the voltage shaping unit is connected to the input of the pulse shaper, the setup zero bus is connected to the key input, the terminals for connecting the synchronizer are connected to the single input of the first trigger, the output of the first trigger is connected to the first input of the first matching circuit, and the output of the key is connected to the zero input of the counter, characterized in that, in order to increase the measurement accuracy by taking into account the real value of the time of operation of the circuit breaker, The switch circuit sensor is switched off and a reversible counter is used as the counter, the sensor output of the automatic switch is connected to the zero input of the second trigger, the output of the pulse generator is connected to the second inputs of the first and second coincidence circuits, the output of the first coincidence circuit is connected to the input of the reverse counter reversible counter, the output of the second coincidence circuit is connected to the input of the direct account of the reversible counter, the single input of the first trigger is connected to the single input of the second the trigger, the pulse driver output is connected to the zero input of the first trigger, the output of the second trigger is connected to the first input of the second matching circuit. ABOUT FIG. 2