SU1622885A1 - Device for checking modules of the same type - Google Patents

Abstract

The invention relates to automation and computing and can be used to control digital blocks. The aim of the invention is to simplify the device and increase informativity. The device contains a synchronization unit 2. Triggers 9, 10 a group of monitored blocks, comparison blocks, an error detector an analysis block, a test generator, a random signal generator, a group of elements And digital blocks whose inputs are divided into two are controlled. groups, which are controlled by time to reduce the inrush current; The synchronization unit, which has different delay times, eliminates the dynamic inrush current during the element tripping. ntov device. Using the trigger element, the triggers are preset to the initial state. The synchronization unit outputs square pulses to the input, which sets the binary code to the inputs of the monitored blocks. One of the triggers changes the state of information on the inputs of the monitored blocks, the other provides blocking in the presence of a failure. The device provides an indication of the malfunction of the monitored digital blocks on the same indicator, and the signal frequency on the indicator indicates which of the digital blocks is faulty. 1 з.п f-ly, 1 ill. sl C

Description

The invention relates to automation and computer technology and can be used in monitoring.

The purpose of the invention is to simplify the device, as well as increase information content.

The drawing shows a device using the example of control of three blocks of the same type (p-3).

The device contains a form of controlled digital blocks 1.1-1.3. synchronization unit 2, formed by a pulse generator 3, delay elements 4-6 and group frequency dividers 7.1 and 7.2, an error detector formed by coincidence element 8 and trigger 9. D-trigger 10, comparison blocks of groups 11.1 and 11.2. block 12 analysis of the controller, formed by elements OR 13-15, groups of elements NOT 16 and 17, groups of elements AND 18-20. and the device also contains a pseudo-random signal generator 21, a group of 22 AND elements, an indication element 23, a start element 24, a test generator 25.

The device operates as follows.

Controlled are controlled digital blocks 1, the inputs of which are divided into two groups of address (from elements 22) and information (from generator 25) inputs so that when setting the effect (changing the binary code on I inputs (t inputs)) and with a constant binary code at ΐ inputs (i inputs), the proportion of switching elements in these blocks is 0.5–0.9 and certainly less than one. When these conditions are met, it is possible to reduce the dynamic surge of the supply current, which occurs when the input influences at the inputs of the digital unit 1 are controlled, by alternately applying the action to the I and t inputs. D-flip-flops 9 and 10 are pre-set using the start element 24 the initial state, and at the outputs of the D-flip-flops, a logical unit is established that allows the operation of the coincidence element 8 and the block of 22 elements I. The 3-pulse generator generates rectangular pulses periodically sequence to the clock input of the generator 25. which is triggered on the leading edge of each of these pulses and sets a fixed binary code for I inputs of the controlled blocks. At the same time, the code does not change at their inputs. Controlled units are triggered and not all are switched in them. but only part of the logical elements (gates, triggers, etc.), i.e. significantly less than if you set the impact at the same time on all inputs (t + l) of digital blocks.

The leading edge of each of the pulses from the output of the 3-pulse generator is delayed by the delay element 4 for the time Τι and goes to the D-trigger 10 clock input, which changes or does not change the state at its outputs when the signal arrives, depending on whether the state in this ( Ι + 1) -th cycle of the device (1 + 1) -th pulse at the output of the generator 3 pulses) relative to the 1st cycle at the output of the generator 21.

If in the (ϊ + 1) -μ cycle of the pulse generator 3 at the output of the generator 21, the state changes relative to the Ι -th cycle of the generator 3, then the state at the outputs of the D-trigger 10 also changes, if not, then the state does not change. After the formation of the next code at the outputs of the D-flip-flop 10, it arrives at the inputs of the And block 22, which is gated by the inputs with the signal from the output of the delay element 5. The strobe signal at the output of the delay element 5 is generated with a delay Г2 relative to the leading edge of each positive pulse at the output of the pulse generator 3 (12> τι) for the duration of the D-trigger 10 and the switching on time of all elements of the controlled digital blocks 1.

According to the strobe signal from the output of the delay element 5, the code from the outputs of the D-flip-flop 10 arrives at the address inputs of the monitored blocks. In this case, the second part of the elements of the digital blocks is switched, and not all elements are turned on, since the inputs I and t are selected in a special way. The output reactions of the controlled blocks generated by the codes from the outputs of the generator 25 and D trigger 10. are fed to the inputs of the comparison blocks 11.1 and 11.2, each of which, if the codes do not match, gives a Log signal through the OR 15 element. 1 per element 8 matches. This signal passes through the coincidence element 8 (since the D-trigger 9 is at the output in a single state) and comes in the form of a Log. 0 to the D-input of the D-flip-flop 9. After a time gz relative to the leading edge of each positive pulse of the 3-pulse generator (g, s> g?> P), a clock signal is supplied to the C-input of the D-flip-flop 9 from the output of the delay element 6. which, in the event of a failure of one of the digital blocks, leads to switching of Trigger 9 to the Log. ”0 state and to a stop of the generator 25 tests.

In the event of a failure of the monitored digital block 1.2, the comparison blocks give a Log signal from their outputs. 1 “to both inputs of AND element 20. Signal Log. 1 from its output passes through the OR element 14 and the indication element 23, which indicates a failure. At the same time, the Log.1 signal from the output of the And 20 element through the OR element 13 passes to the frequency resolution enable inputs of frequency dividers 7.1 and 7.2 and does not allow these dividers to divide the frequency, without creating unnecessary interference. In this case, the signals from the output of the comparison blocks pass through the elements NOT and prohibit the passage of the dividers through the elements 18 and 19 respectively to the inputs of the OR 14 element. In this case, on the display element 23 a constant level failure signal indicating the failure is monitored) of digital block 1.2.

In the event of a malfunction of the digital unit 1.1, the D-flip-flop 9 generates a 'Log.O' signal to the input of the third element OR 13. To the other input there is a Log signal (G lads from the output of the And element 20. At the outputs of the comparison blocks, respectively, and Lsg 1 and Log 0. The presence of two zero signals at the inputs of the OR element 13 leads to the fact that it gives a resolution signal for dividing the frequency of the dividers often d · At the input of the And 19 element, a single signal <, the path of the element is NOT 17. On the second input signal from the output of the first frequency divider, at the other input - a single signal from the output of the bl as a comparison, which leads to the appearance at the outputs of the elements AND 19 and OR 14 and at the inputs of the element 23 of the signal indication with a frequency of the first frequency divider 7.1, since there are Log.0 signals at the second and third inputs of the element OR 14. signal with a frequency of the first frequency divider indicates a failure of the first digital block in the group.

In the event of a malfunction of the digital unit 1.3, trigger 9 generates a 'Log.’O signal to the input of the third element OR 18. The second input of which Log.0 is supplied from the output of the And element 20. At the outputs of the comparison blocks, respectively, the signals Log.0 and Log. 1. The presence of two zero signals at the inputs of the element OR 13 leads to the fact that it gives a signal to enable the division of the frequency of the frequency dividers. At the input of element And 18 is the signal from the output of the frequency divider 7.2, at the second input is a single signal from the output of the element NOT 16. at the other input is a single signal from the output of the block

11.2 comparison, which leads to the appearance at the output of the AND element 18. the first OR element 14 and at the inputs of the signal indication element 23 with a divider frequency of 7.2 parts, since there are Log.0 signals at the first and third inputs of the first OR element 14. The presence on the element 23 of the signal indication with a frequency divider 7.2 frequency indicates a failure of the digital unit 1.3.

If all three blocks are in good working order, the trigger 1 receives the signal Log.1 at the input of the OR element 13. The signal Log.0 from the output of the block 11.1 of the comparison goes to the first inputs of the second element OR 15. of the And 20 element and the inputs of the elements NOT 16 and AND 19 . Signal Log. ”0” from block output

11.2 comparison arrives at the inputs of the elements OR 13. AND 20. NOT 17 and AND 18. Moreover, at all the inputs of the element OR 14 - signal Log.O. on the element 23 of the indication there is no signal of failure, which indicates the serviceability of all blocks.

Thus, in the case of serviceability of all digital signaling units, the indicator is absent. In the event of a malfunction of the monitored digital unit, connect-> not with the error detector, and this can be any unit with a given control structure. the display element 23 provides a constant signal. In case of failure of one of the digital blocks, the indicator gives an intermittent signal, the frequency of which characterizes. which of the digital blocks is faulty.

Thus, the information ability of the device is increased, which allows to determine the malfunction of the monitored units in the group, the routine maintenance is reduced, since the frequency of checking the device for monitoring is increased. In addition, device maintenance is simplified and the cost of control is reduced by increasing the frequency of routine maintenance, and the psychological burden on maintenance personnel is reduced, since it is not necessary to analyze which of the digital units failed.

Claims (2)

Claim 1. A device for monitoring the same type of blocks, containing a synchronization block, a test generator, a group of p-1 comparison blocks (p is the number of controlled blocks in the group), a result analysis block, the first output of the synchronization block being connected to the clock input of the test generator, a group of field outputs tests of which is a group of device outputs for connecting to I inputs of monotonous sequential blocks of the same type (I number of information inputs of one monitored block with a high frequency of changing group information, excellent7 with the fact that, in order to simplify the device, as well as increase information content, it contains a pseudo-random signal generator, a D-trigger, a group of AND elements, an error detector, and the output of the 5 pseudo-random signal generator is connected to the D input of the D-trigger, the sync input of which is connected to the second output of the synchronization block, the third output of which is connected to the synchronization inputs of elements 10 AND groups, the first and second inputs of which are connected to the direct and inverse outputs of the D-trigger, respectively, the output group of the synchronization block is connected to the first group of information inputs of the result analysis block, the first output of which is connected to the input of the error detector, the output of which is connected to the first information input of the result analysis block and the lock generator test input, the outputs are equal to p-1 of the comparison blocks of the group are connected to the second group of information inputs of the block analysis of the result, the second output of which is connected to the device error output, the third 25 output of the result analysis block is connected to the input of the mode setting of the synchronization block, the outputs of the elements AND groups i are the group of device outputs for connecting to t inputs of monotonous sequential blocks of the group (t is the number of address inputs of one block with a low frequency of information change), the first inputs jx of the group comparison blocks (j- = 1 ..... p) are j- the inputs of the device for connecting to the outputs of the m-x (m = 1, η 2) monitored sequential blocks of groups and connected to the second inputs of the (t 1) -th blocks of comparison of the group, the second inputs of the first and (n-1) -th blocks of comparison groups are connected to the first and ηth inputs of the device for connecting to the output It is first and η-th controlled sequential blocks, third and fourth outputs coupled to the block synchronization clock terminal of the generator a pseudo-random signal. with the input of the D-trigger and the synchronization input of the error detector, respectively. 2. The device pop. 1, characterized in that. that the result analysis block contains three OR elements, two groups of NOT elements, three groups of AND elements, and the first group of information inputs of the block is connected to the first inputs of the AND elements of the first and second groups, outputs 20 of which are connected to the first group of inputs of the first OR element, the output which is connected to the second output of the block, the first and third outputs of which are connected to the outputs of the second and third OR elements, respectively, the first information input of the block is connected to the input of the third OR element. the other inputs of which are connected to the outputs of the AND elements of the third group and to the second group of inputs of the first OR element 30. the second group of information inputs of the block is connected to the inputs of the second OR element. with the first inputs of the AND elements of the second and third groups, with the inputs of the AND elements of the first group and through the first and second groups of elements NOT - with the second inputs of the AND elements of the second and third groups, respectively.