SU1690137A1 - Dc-to-three-phase ac voltage traction converter - Google Patents

Abstract

The invention relates to a converter technique and m. used in inverters for electric locomotives. The goal is to extend the functionality by providing switching stability in case of overloads in recovery mode. The device contains the main, reverse and distribution bridges on thyristors. The load circuit includes current sensors. The forced switching node is connected to a power source made as a single-phase diode bridge, which is connected to the main source through four protective thyristors. If the load current exceeds the current setting, the control unit turns on two protective thyristors, the reverse thyristors are turned off, and an emergency shutdown of the converter occurs. 5 il.

Description

with

WITH

The invention relates to a converter technique and can be used in a triac frequency converter, in particular, in autonomous inverters of alternating current electric locomotives.

The purpose of the invention is to enhance the functionality by providing switching stability during overloads in the recovery mode.

FIG. 1 is a schematic diagram of the device; in fig. Figure 2 shows diagrams of UV voltages and control pulses V, which explain the operation of the device in the pull mode (direct electric energy conversion mode); in fig. 3 - curves of currents I and voltages 1) φ, explaining the process of conversion of electric energy in the recovery mode (inverse transformation); in fig. 4 shows graphs of UV voltages and control pulses V, explaining the operation of the device in the mode

recuperation; in fig. 5 - control unit of the transducer.

The device contains a reversible power source 1 connected by its leads to the terminals of the inverter 2 voltage, made in the form of the main, inverse and distribution thyristor bridges 3-20, consisting of the main 3, 4, 9. 10, 15, 16, reverse 7, 8, 13, 14, 19, 20 and distribution 5, 6, 11, 12, 17, 18 thyristors, current sensors in the form of shunts 21-23 connected to the output terminals of the voltage inverter 2, load 24-26 connected to the terminals current sensors, made in the form of shunts 21-23, the power source 27 of the forced switching node, made in the form single-phase diode bridge 28-31 with filter capacitor 32, additional protective thyristors 33, 34, forced switching node 35, consisting of switching

ABOUT

yoo o

Oj vi

thyristors 36-39, charge thyristors 40-41, dnouh commuting LC circuits 42-43 and 44-45, made of series-connected commutating capacitors 42, 44 and chokes, charge thyristor 46, 47, isolation diode 48, switching transformer with two primary windings 48, 50, discharge diodes 51, 52, communication diodes 53, 54, return diodes 55-58, the secondary winding of switching transformer 59, powering diodes 60, 61. Basic protective thyristors 62, 63 and additional diodes 64, 65 connections are connected to the conclusions of the corresponding ersivnogo power source 1 and power source 27. The converter also contains a control block 66.

A control unit 66 (FIG. 5) connected by the output terminals to the thyristor control inputs and input terminals 67-73 to the current sensor terminals 21-23, and contains a frequency relay 74, the outputs of which are connected to the control pulse distributor 75.

A logic node 76 is connected to the output of the control pulse distributor, the outputs of which are connected to the control inputs of the main, reverse, and distribution thyristors, as well as to the control inputs of the switching thyristors 36 and 39.

Single-vibrators 77 are connected to the outputs of node 76, connected through amplifying-decoupling nodes 78 with their outputs to control inputs of switching thyristors 37, 38, as well as second one-vibrators 79 connected to amplifier-disconnecting nodes 80, 81.

The outputs of the current sensors 21-23 through the input terminals 67-72 and the amplifying-decoupling elements 82-84 are connected to one input of three comparators 85-87, the other inputs of which are connected to a reference voltage signal setting the setpoint current.

The device contains two additional one-shot 88.89, connected by inputs. the outputs of the logic node, and the outputs of the amplifier-decoupling nodes 90 v 91 - to the first inputs of two two-input logic elements 2I 92 and 93. Signals from the comparators are fed to the second inputs of the elements 92 and 93 through the amplifier-decoupling elements 94-96 85-87, the outputs of the elements 92 and 93 through the amplifier-decoupling nodes 81, 97 and 98 are connected to the control inputs of the charge 46 and 47 and the main protective 62 and 63 thyristors.

The control unit includes the logical elements 2I 99 and 100 connected by the inputs to the outputs of the single-oscillators 88 and 89 and amplifying

95, 96, the outputs through the auxiliary amplifying and decoupling nodes 101 and 102 - with the control inputs of the thyristors 46,47 and with one of the inputs of two two-input logic elements

0 103, 104, connected by other inputs to the output of the logic node 76. The outputs of the elements 103,104 through the amplifying-decoupling nodes 105, 106 are connected with the control inputs of the additional

5 protective thyristors 33, 34, Control inputs of two-input logic elements 2 And 107 and 108 are connected to the output of logic node 76 and to the outputs of amplifying-disengaging nodes 97 and 98. Outputs

The 0 elements 107 and 108 are connected to the control inputs of the main protective thyristors 62 and 63 through the amplifier-decoupling elements 109 and 110.

The traction converter operates as follows (Fig. 2 and 3). Suppose that in the time interval the main thyristors were switched on 3, 9, 16 and the load current flowed through the circuit: 1, 3, 21, 24, 26, 23, 16, 1; 1, 9, 23, 25, 26, 23, 16, 1. At the moment

0 time ti (figs. 2 and 3) turn on thyristors 5 and 36, as a result of which thyristor 3 is turned off by loop 42, 43, 48, 5, 3, 53, 36, 42. At the moment of equality of the current of the LC circuit 42, 43 to current load current in thyristor 3 drops to O

5 (Fig. 2). In this case, the recharge current of the capacitor 42 is closed along the circuit 42, 43.48, 51, 36, 42, as a result of which the thyristor 3 is applied the reverse voltage of the primary winding of the switching transformer 49 of the formatter 49 (Fig. 2, Kz, U49J along the circuit plus winding 49, 5, cathode 3 and minus windings 49, 51, 53, anode 3.

With a shift in time (Fig. 3), the thyristor 38 is turned on, and the LC circuit 44, 45 of the recharge 5 is connected to the loop 44, 45, 49, 51, 38. With the shift in time, the charge thyristors 40 and 47 turn on, performing a charge the capacitor 42 of the first LC circuit 42, 43 along the contour 32, 40, 42, 43, 47, 32; In addition,

In the time interval tt-t2, the reverse thyristor and the next main thyristor 4 are turned on. This is the end of the process of turning off the thyristor 3.

At time t2 (Fig. 2), the main thyristor 16 is switched in load 26. Suppose that by the time point ta the current in load 26 and thyristor 16 has increased to a value at which the switching capacity of the forced switching node is not sufficient to turn off

thyristor 10. Consider this process on the example of the diagram of currents and voltages (Fig. 2). According to the diagram (Fig. 3), to turn off the thyristor 16, switch on the thyristor 18 and the switching thyristor 39 are turned on, the capacitor 44 of the LC circuit 44, 45 is recharged along the circuit and turns off the thyristor 16 via the circuit 44, 39, 54, 16, 18, 48, 45. 44. At the same time, the voltage of the primary winding of the transformer 50 is applied to the thyristor 16 to restore its valve properties. A second LC circuit 42, 43 is switched with a time shift (Fig. 3). In this case, the switching capacitor 42 is discharged along the circuit 42, 37, 52, 50, 43. However, the load current becomes at time t3 more than the amplitude of the switching current pulse, and since the time interval t2-3 is less than the time required to restore the valve properties of the thyristor 16, the thyristor 16 is turned on again, and the current through the thyristor 18 is stopped. At time, the thyristors 46, 41 turn on, so that the capacitor 44 is charged along the circuit 32, 46, 45, 44, 41, plus 44, 45, 46, 32, 41, minus 44.

Since the thyristor 16 is turned on again, the next main thyristor 15 is banned from switching on. With a shift in time equal to the interval t4-5. control pulses are supplied to the thyristor 34 and again to the charge thyristor 47. At the same time, the capacitor 32 begins to recharge along the circuits 32, 34, 16, 18, 43, 47, 32, and the thyristor 16 is turned off.

After the thyristor 16 is turned off, the overcharging current of the capacitor 32 flows through the circuits 32, 34, 20, 18, 43, 47.32, as a result of which the thyristor 16 is applied in the opposite direction to the voltage drop across the thyristor 20. On the time interval ts-e capacitor 32 recharged by voltage of opposite polarity. However, this capacitor voltage is low, since the negative-polarity capacitor current is closed along circuit 32, 61, 52, 50, 48, 49, 51, 60, 32 or 32, 61.56, 55, 60.32 or 32, 61 , 58, 57, 60, 32. In addition, the capacitor 32 is recharged from the source of supply through the diode bridge 28-31 to the same polarity. Since the capacitance of the capacitor 32 is on an order of magnitude larger than the capacitance of the capacitors 42, 44, by selecting the capacitor capacitance 32 parameters and the inductances of the faults from the chokes 43 and 45, one can obtain the required amplitude and pulse duration of the capacitor 32 recharge, which can be several times greater than the amplitude the current pulse generated by the action of the m LC-chain 42, 43 and AL, 45, doesn’t mean enough to balance the current. about 2-3 times the load current, switched by LC circuits 4 45 Duration of 5 pulses of current created by the action of the capacitor 32 and the inductances of the taps of chokes 43. 45 should be not less than the passport time required to restore the valve properties of glave thyristors when reverse voltage 1.5-2 V.

After the valve properties of the thyristor 16 are restored, the thyristor 15 is turned on, and the inverter operability is restored. If the load current exceeds the set current, a signal is generated to increase the reference on the output frequency of the converter, and the load current decreases once the next switching, therefore at the time te switch off the thyristor 9 For this, as well as to turn off the thyristor 3, switch on 36 and distribution thyristors 11 are switched on according to the diagram (Fig. 3).

5 Let's consider the work of the converter in

recovery mode when the polarity of the sign of the voltage of the power source 1 at the input of the inverter 2 is changed. In this case, due to the fact that the input converter has one

0 a group of valves, the current at the input of the inverter maintains the same polarity and the main thyristors of the inverter (see Fig. 4) conduct part of the current opposite to the voltage sign, and reverse thyristors - part

5 current coinciding with the sign of the voltage. As a consequence, the reverse thyristors are forcibly turned off and with a shift equal to the switching interval, the main thyristors are switched on. Consider this on

0 is an example of turning off a thyristor in phase A. Suppose that, according to FIG. 4, the thyristors 8, 9, 16 were turned on at the time interval, as a result of which the load current closed along the circuit 26, 16, 1.9, 25, 26; .25,

5 26, 16, 1, 9, 25; 24, 26, 16, 8, 24. At time 1, the voltage changes in phase A by forcing the thyristor 8 to turn off. To turn off the thyristor 8, turn on the thyristor 5 and the thyristor 36 of the first

0 commuting LC circuit. In this case, the capacitor 42 begins to turn off along the circuit 42, 43, 48, 5, 8, 65, 36, 42. The current in the thyristor 8 drops to zero, as a result of which the capacitor 42 recharges along the circuit 42.43.48,

5 49, 51, 36, and the thyristor 8 is applied the reverse voltage of the primary winding of the switching transformer: plus 49 through the thyristor 5 to the cathode 8, minus 49 through 51 and 65 to the anode 8. When you turn off the thyristor 8, the load current closes through the switching circuit circuits 24, 26, 16, 65, 36, 42,43,48, 24. With a shift in time, the switching capacitor of the second LC circuit is switched on, as a result of which the load current is transferred to the second L C circuit and is closed along circuit 24 26, 16, 65, 38, 44, 45, 5, 24. The excess current of the capacitor closes on the circuit 44, 45, 49, 52, 38, 44, as a result of which laziness properties to the thyristor gate 8 applied voltage of the primary winding voltage of the switching transformer 49, then a time shift charge dnye incorporated thyristors 40 and 47 and is carried dozar d first switching LC-circuits 42, 43.

As the load voltage of the capacitor 44 is reloaded, the voltage across it will reach the supply voltage of the source 27, as a result of which the thyristor 38 turns off and the thyristor 3 turns on. When the thyristor 3 is turned on, the voltage sign in phase A changes and the load current of phase A ( 24) closes on contour 24, 26, 16. 1,3,24.

At time tz, the sign of voltage and phase C changes, as a result, reverse thyristor 19 is turned off. For this, thyristor 18 and commuting thyristor 39 are turned on, as a result of which thyristor 19 is turned off by oscillating overcharging of capacitor 44 along circuit 44, 39, 64, nineteen,

18,48, 45, 44, the load current is transferred to the circuit 26, 18, 48, 45, 44, 39, 64, 3, 24, 26. The excess current of the recharge of the capacitor 44 is closed along the circuit 44, 39, 52, 50, 48, 45, 44, so that the coil voltage of the switching transformer 50 is applied to the recovery time of the valve properties of the thyristor 19: minus 50 is applied to the anode through the thyristor 18

19, and plus through diodes 52 and 64 to cathode 19. With a shift in time, the second oscillating circuit is turned on, and the processes are repeated as previously discussed.

Consider the operation of additionally introduced protective thyristors at the time ti. Suppose that the instantaneous load current (see Fig. 4) exceeded at time ti the amount of current that the forced switching node can turn off, and the thyristor 8 does not turn off. Then, with a time shift, control pulses are applied to the additionally introduced protective thyristor 34 and charge thyristor 46. As a result, the capacitor 32 turns off the thyristor 8 along the circuit 32, 46, 45, 5, 8, 34, 32 and then the processes are repeated in a similar way. described above.

To turn off the thyristor 19 in the event of non-switching, an additional protective thyristor 33 and a charging

47. In this case, the thyristor 19 is turned off by the circuit 32, 33, 19, 18, 43, 47, 32, and then the process is repeated in a similar way.

The control unit 66 operates as follows. To the input of frequency regulator 74, a UV signal is given to set the output frequency of the converter, which also determines the reference mode T ha, a recuperation according to which a sequence of rectangular normalized and time shifted positive UJs (UA, UB, Uc) is formed from the output of frequency regulator 74 and negative Uj (Od, UB, Uc) pulses (J is the phase index).

The pulses DJ and Uj arrive at the input of the distributor 75 pulses, forming output pulses along the leading edges defined by the logical expressions Fi UA, FЈ UA, Fa Uv, F / i UB., Fs Uc, Fe Uc, which are received through the logical node 76 control to the control inputs of the main thyristors 3, 4, 9, 10И5, 16. On the falling edges of the pulses Uj and U form narrow pulses defined by the logical expressions UA °, Fg Uc °, Fio OY, FH UB, Fi2 Uc, which flow through control logic 76 to the control inputs of the distribution thyristors 5, 11, 17, 6, 12, 18, as well as to form There are wide control output pulses defined by the logical expressions Fi3 UA °°, Fi4 UB °°, Fis Uc00, Fie UA °°, Fn UB °°, Fw Uc °°, which are fed through logic node 76 to the control inputs of the reverse thyristors 8,14,20, 7,13, 19. From logic node 76 to the control inputs of commuting thyristors 36, 39 receive control pulses that implement logical expressions

Fi9 UA ° + UB ° + Uc0, F2o + UC °.

The outputs of the node 76 are also connected to the inputs of the first single-oscillators 77, which form a delay of 2/3 tons, where r is the duration of the recharging of the switching LC circuits, the outputs of which are connected to the control inputs of the switching thyristors 38, 37 sequence reload yes LC circuit. The second one-vibrators 79, which form a delay greater than m, are connected by their outputs through amplifying-decoupling nodes 80 and 81 to the control inputs of the charge thyristors 40, 41, 46, 47.

According to FIG. 4, the inputs 67 73 of the control system 66 receive signals from the current sensors 21-23, and then these signals enter the inputs of the amplifying and coupling nodes 82-84. The signals from the outputs 82-84 are then fed to the inputs of the comparators 85-87, where they are compared with the setpoint signal to the input 73 of the control system 66. The setpoint signal corresponds to the instantaneous value of the current switched by the forced switching node. If the signal corresponding to the instantaneous value of the current in the switched phase, coming from the current sensors, exceeds the setpoint current, a signal is received from the comparators 85-87 to the amplifier-disconnecting nodes 94-96, resulting in control pulses that arrive in each phase of the two-way load - second logical elements 2I 92, 93, 99, 100.

Simultaneously, the shapers 91-93 generate interdiction pulses (FOR, 3B, ES) that prohibit the switching on of the next main or reverse thyristors (for example, if in phase 24 thyristor 3 is in operation, prohibition is generated on thyristor 4, if thyristor 10 is in operation, the inhibition is applied to thyristor 9 if the thyristor 8 is working, the prohibition is applied to the thyristor 7, etc. On the leading edges of the pulses coming from the logical node 76 to the control inputs of the switching thyristors 36 and 39, the single vibrators 88 and 89 form pulses that are equal in duration to the time intervals. -5 (see fig. 3), the formers 90 and 91 over the back edges of one-shot pulses generate pulses arriving at the inputs of logic elements 2Y, 92, 94. From the outputs of these nodes, the signals are fed to the amplifying-decoupling nodes 97, 98 and 81, which ensure the inclusion of the main thyristors 62 and 63 and repeated switching on of charge thyristors 46, 47. The signals from outputs 97, 98 are sent to the elements 21/1 107, 108; The signals from the logical node 76 receive the signal corresponding to the operating mode (T ha) to the second inputs of these elements, and with the coincidence of these signals through u The elements 109 and 110 control pulses are applied to the main protective thyristors 62, 63.

The signals of the prohibitions coming from nodes 94-96 also generate pulses for switching on the corresponding reverse thyristors with a delay for switching on the next main thyristor.

In the recovery mode, the signal from the logical node 76, corresponding to the recovery, enters the elements 2I 103 and 104,

where it is compared, by coincidence, with lottery quivers arriving from elements 2 and 99, 100 whose input terminals are connected to the outputs of one-shot 88

5 and 89 and to the outputs of the nodes 94 Q6 When the signals P and the signal exceed the load current in recovery mode, control pulses are generated through the elements 105, 106 to the control by-pass

0 thyristors 33 and 34 and through elements 101 and 102 to the control inputs of thyristors 46, 47

The use of the device allows for the change of sign voltage

5 of the filter capacitor, turning off the thyristors of the reverse thyristor bridge 7, 8. 13, 14, 19, 20, as well as in the case when the load current exceeds the current setting corresponding to the maximum switching

0 the capacity of the forced switching node, turn off the reverse thyristors with additional protective thyristors and thus eliminate the closure of the power supply source 1 through the thyristor reverse circuit and emergency disconnection of the coupling converter in regeneration mode ..

Claims (1)

Invention Formula T constant converter 0 voltages to three-phase AC, containing main, reverse, and distribution thyristor bridges, the AC terminals of which are connected and connected via current sensors to the output 5 pins, with the DC terminals of the main and reverse thyristors bridges connected to the power supply terminals, a single-phase diode bridge, the AC outputs of which are connected to the power network terminals, and a filter capacitor connected to the DC terminals and through mutually connected dissolving diodes - bridge of commuting thyristors, in the diagonal of alternating current of which 5 a series is connected, consisting of two successive LC chains and a separating diode connected between them, the cathode of which is connected to the anode group of the separation thyristor bridge and the first primary winding of the switching transformer, connected through the first discharge diode to the anode group of the bridge thyristor switching, and the cathode group of the distribution diode bridge is connected to the anode of the divider diode and the second primary winding of the switching transformer connected via the second a counter-on-discharge discharge diode of the cathode group of a commuting thyristor bridge, parallel to this bridge a bridge of return diodes is included, the diagonal of the alternating current of which includes the secondary winding of the commutating transformer, and two DC diodes connected to the return diodes are connected to the DC terminals the bridge with the same electrodes, with the anode of the first communication diode connected to the anode group of the main thyristor bridge connected through the first main protective thyristor to the anode group of the same The second diode is connected to the cathode group of the main thyristors, connected via the second main protective thyristor to the cathode group of the single-phase diode bridge connected through the first charging thyristor with one AC output terminal of the switching thyristors, and the second charge thyristor - with the tap-off of the throttles, the LC-chain connected to another AC output of this bridge, connected via the third charge thyristor to the anode group of the single-phase diode A bridge with a fourth LC thyristor is connected to the tap of the throttles of another LC chain, a control unit containing a frequency regulator, which forms a sequence of rectangular normalized and time shifted positive Uj pulses according to the task signal, where j is the phase index, a control pulse distributor connected by inputs to the outputs of a frequency regulator and executed by output pulses along the leading edges of the pulses UJH Uj, which are defined by the following expressions tim E: Fi UA, F2 UA, F3 UB, F4 Ub. F5 UC, F6 Uc, and on the falling edges - narrow pulses F7 UA °, F8 UB °, Fg Uc °, Fio  UA °, Fii UB °, Fi2 Uc ° and wide impulses , Fi4 UB ° 0, Fi5 Uc °°,,, as well as a logic node connected to the output of the pulse distributor of control that implements logical expressions  + UB ° Ur °, F20 -UA ° + UB ° Uc °, where are the expressions defining the control of the main thyristors, Fy-Fi2 - distribution. Fi3-Fis reversed, Fig and Fao are switching thyristors of the first order of reloading into each commutation of the mentioned LC circuit, connected by inputs to the outputs of the logical node, the first one-oscillators, which form a delay of 2/3 t, where r is the duration of the reloading of the mentioned above the switching LC circuit, the outputs connected via amplifying-decoupling nodes to the control inputs of the switching thyristors of the second LC circuit recharging, the second one-oscillators, also connected by inputs to the outputs of the logic node and output nennye forming a delay greater than d, and outputs via amplifying and decoupling nodes connected to the control inputs of the respective charge dnyh 5 thyristors, three comparators, connected by their inputs to the outputs of the current sensor and to the setter of the reference voltage signal setting the current of the setpoint; two additional single-oscillators made 0 forming on the leading edges of the incoming pulses a delay of 2 G, which by their inputs are connected to the outputs of the logical node realizing the specified logical expressions of Fig and F20, 5 two two-input logic elements 2I coinciding with their inputs connected to the outputs of comparators and additional single-shotrs, and outputs through amplifying-decoupling nodes to the corresponding control inputs of charging thyristors, characterized in that in order to expand functionality by providing switching stability overload 5 in recovery mode, it is additionally equipped with two additional communication diodes and two additional protective thyristors connected in series with a single-phase diode 0 by the bridge and connected to the same terminals of the direct current of the reverse thyristor bridge and to the same conclusions of the additional communication diodes connected by free terminals to the same names of the bridge of the returning diodes, and six logic elements 2I, four of which are connected to the control unit, four of which are connected to the control inputs of main and additional protective thyristors, and the inputs of logic elements 2I, connected by additional protective thyristors, are connected to the corresponding output the logical node and to the outputs of two other additionally introduced logic elements 2И connected through the input of auxiliary amplifying and decoupling nodes with the control inputs of the second and fourth charging thyristors. 2 9and ChF8 /////, v ill h FIG. I the inputs of these elements 2I are connected to the outputs of the comparators and additional one-shot, and the inputs of logic elements 2I connected to main protective thyristors, connected to the corresponding output of the logic node and, through the input of additional amplifying-decoupling elements, to the outputs of two-input elements of match 2I. ffr 7 . ////// Y /// I-7 UVA ( Phys 3 Fig Editor B. Fedotov Compiled by I. Zherebina Tehred M. Morgenthal ten I Proofreader M. Demchik