SU1686578A1 - Device for voltage control in multiphase circuit - Google Patents

Abstract

The invention relates to electrical engineering and is intended for use in alarm devices and the protection of electrical power systems. The purpose of the invention is to increase the reliability of protection by operating the device after a predetermined number of both short-term drops and short-term voltage rises, as well as a result of a decrease or increase in voltage over a long period of time in the phases of the monitored network. The first company relates to electrical engineering and is intended for use in alarm devices and power system protection. The aim of the invention is to increase the reliability of protection by operating the device after a predetermined number of both short-term reductions and short-term voltage rises, as well as a decrease or increase in voltage over a long period of time in the phases of the monitored network. The rator 5 changes its state when the voltage decreases in phases (the threshold is set by the second voltage divider 3), and the second comparator 6 changes its state as the voltage in the phases increases) the threshold is set by the third voltage divider 4) first 9 and second 10 elements OR. element 12 sets the mode of the one-shot 13. for short-term voltage changes, it produces a single pulse, during which counter 14 begins to count the number of these voltage changes to one side or the other for a long period of time, the one-shot 13 starts to work as a generator impulses, counting a given number of which the counter 14 gives the command to the executive body 15 to disconnect the electrical consumer from the monitored network. As a power bus 17, the devices take the output of a simple parametric stabilizer, the input terminal of which is connected to the output of the multiphase rectifier 1. 6 Il. FIG. 1-4 shows the electrical circuit of the device: FIG. 5. 6 - time diagrams of his work. A device for monitoring voltage in a multiphase network contains a multiphase half-wave rectifier 1 first 2, second 3 and third 4 voltage dividers, first 5 and second 6 comparators, first 7 and second 8 elements AND-NOT, first 9, second 10 and third 11 elements OR, element 12, one-shot 13, counter 14. executive authority 15, delay line about 4 o

Description

16, a stabilized power bus 17, the first voltage divider 2 is connected to the single-half-voltage rectifier 1 by the first end terminal and has a second terminal terminal for connecting to the zero conductor of the network 18, the middle point of the first voltage divider 2 is connected to the non-inverted input of the first comparator voltage Bis inverted input of the second voltage comparator 6, the first end terminals of the second 3 and third 4 voltage dividers are connected to the power bus

17, the second end leads are with a zero conductor network 18, the middle lead of the second voltage divider 3 is connected to the inverting input of the first voltage comparator 5, and the middle lead of the third voltage divider 4 is connected to the non-inverting input of the second voltage comparator 6, the output of which is connected with the first input of the first element AND -NE 7 and with the first input of the first element OR 9, and the output of the first comparator 5 is connected to the second input of the first element AND- NOT 7 and to the first input of the second element OR 10, with the second inputs of the first 9 and second 10 elements OR are connected to the output of the delay line 16, the input of which is connected to the output of a single vibrator 13 and to the first input of the third; Lemanga OR 11, the second input of which is connected to the output of the first element AND- NOT 7 and to the first input of the second element AND- NOT 8, the second input of the second element AND- NO 8 is connected to the input of the one-shot 13 and the output of the element AND 12, the output of the first element OR 9 is connected to the first input of the element AND 12, and the output of the second element OR 10 is connected to the second input of the element 12, the output of the third element OR 11 is connected to the input. 14, the output of the second element AND- HE 8 is connected to the input of the counter Counter 14. A delay line is made on a series-connected resistor 19 and a capacitor 20, the first lead of the capacitor 20 is connected to the neutral conductor of the network 18, the first lead of the resistor 19 is the input of the delay line 16 . and the connection point of the second terminal of the capacitor 20 and the second terminal of the resistor 19 is the output,

The executive body 15 is made on the isolation diodes 21, the switch 22, the repeater 23, the element HE 24, the executive relay 25 equipped with contacts 26. The counter 14 in addition to the actual counter 27 contains the input element HE 28 and the element AND NOT 29, one of the inputs of which connected to the output of the element 24 of the executive body 15. The one-vibrator 13 is made on the element AND-30, elements 31 and 32, the capacitor 33 and the resistor 34

(Fig. 2-4).

The device works as follows.

In the full-phase mode of the network, the output of the rectifier 1 is the pulsing positive polarity applied through the voltage divider 2 to the non-inverting input of the first voltage comparator 5 and to the inverting input of the second voltage comparator 6.

5 Ne the inverting input of the first comparator 5 is supplied with a constant voltage level from divider 3 (FIG. 5, UB), and to the non-inverting input of the second comparator 6 from divider 4 (FIG. 5, Kb). As a result, in the initial state, a signal Log is formed at the outputs of the computer recorders. 1 (high potential), which through the first 9 and second 10 elements OR and through the elements And 12 receive a signal

5 Logic 1, to the input of the one-shot 13 and to the second input of the second element IS-NOT 8, the first input of which is from the output of the first element IS-NOT 7 signal Logic 0 (at the inputs of the first element IS-NOT 7 signals Logic 1 from the outputs comparators 5 and 6). as a result, at the input of the Account of the counter 14, the level of Logic 1 is set, and at the input of Zeroing - the level of Logic 0, since this

Level 5 is formed from the output of the third element OR 11, the first and second inputs of which receive signals with a level of Logic 0, respectively, from the output of a single vibrator 13 and from the output of the first element

0 AND-NOT 7. Counter 14 is in the initial state.

When the voltage decreases, for example, in phases F2 and F4, the voltage level from the first divider 2 supplied to the non-inverting input of the first comparator 5 and the inverting input of the second comparator 6, during the time n, Г2 becomes less than the voltage level set on the inverting the input of the first comparator 5 (Fig. 2. UB), as a result, the output of the comparator 5 is a logical 0 signal in the time interval n, n. (Fig. 5), arriving at the first input of the second element OR 10, the second input of which contains the signal Logical 0 from the output

one-shot 13, as a result, at the output of the second element OR 10, and consequently, at the output of the element 12 And, a signal drop from the level of Logic 1 to

Logic level 0 (Fig. 5. d), which triggers the one-shot 13, and a Logic 1 signal appears at its output, which, arriving at the first emitter of the third element OR 11, forms the output of this element and, therefore, at the input: Resetting the counter 14, the signal Logical 1 (Fig. 5, g), allowing the counter to operate in the counting mode. At the same time, the transition of the Logical 1 level to the Logical 0 level at the output of the first comparator 5 with a decrease in voltage is transmitted to the second input of the first AND 7 NOT element, the output of which (Fig. 5, d) forms a voltage drop from Logic 0 to Logic 1, arriving at the first input of the second element IS-NE 8, at the output of the second element IS-NOT 8, and hence at the counting input of the counter 14, the signal passes from the state of Logic 1 to the state Logical 0, and since the input is Zero counter 14 is the level of Logic 1, counter 1 4 goes to the next state. If during the time when the input signal Resetting the counter 14 is Logic 1 (Fig. 5, g), the specified number of counting pulses is fed to the counting input of the counter 14, the specified combination of signals is formed at the discharge outputs of the counter 14, which leads to executive body 15 and to output a signal from the output. Operation of the executive body 15 to the input. Disable the counting of the counter 14, while the electrical consumers are disconnected from the monitored network. If during the time when the input signal Resetting the counter 14 is Logic 1, the counter input of the counter 14 is less than a predetermined number of counting pulses, then the discharge outputs of the counter 14 do not generate the specified combination of signals and the actuator 15 does not work. After working off the time setting at the output of the one-shot 13 a Logical 0 is formed (Fig. 5. g), which is fed to the first input of the third element OR 11, the first input of which also contains the signal level Logical O (Fig. 5, d), as a result on the input Resetting the counter 14, the signal Boolean 0 sets the counter to the initial state.

When the voltage rises in one or several phases, for example, FZ and F5 (Fig. 5, a), the device operates in the same way, except that when the voltage rises, the second comparator 6 is triggered, and not the first 5, since the increase in voltage marrying the first divider 2 leads

to the fact that the potential of the inverting input is greater than the potential of the non-inverting input and the second comparator 6 changes its state from the level of Logic 1 to Logic 0, which is fed to the first input of the first element OR 9.

With an increase in voltage at once in all phases to the level of UK Ue, and Ua U6, the device operates according to the algorithm described above.

FIG. 6 shows the operation of the device with a significant increase in voltage in all phases at once, when U U Ue and at a decrease in voltage in all phases, right away, when UK UB, and it is assumed that this increase or decrease in voltage lasts indefinitely (until the device disconnect the power from the monitored network). With an increase in the voltage in all phases at once (U UG), a constant level Logic O is set at the output of the second comparator, which in turn forms the level at the output of the first element AND NOT 7

5 Logic 1 (Fig. 6. g) and through the third element OR 11 level Logic 1 is fed to the input Resetting the counter 14. Allow the counter to work in the counting mode. At the same time, the signal level transition from Logic 1 to Logic 0 at the output of the second comparator b is transmitted through the first element OR 9 and through the element 12 to the input of the one-shot 13 (Fig. 6. d), as a result of which the Logical 1 (Fig. 6, L), which through time rh, resulting from passing the signal through delay line 16, arrives at the second input of the first element OR 9,

0 at the first input of which the Logic 0 is still output from the output of the second comparator 6, as a result, the output of the first element OR 9 and, consequently, the output of the AND 12 element (at the second input of the AND 12 element the Logical 1 signal is found all this time since the first comparator 5 does not change its state) the signal changes its state from Logic O to Logic 1 (Fig. 6. e) After the time setting of the one-shot 13 is completed, a Logic 0 signal is generated at its output transmitted by the first element and OR 9 and the element And 12 to the input of the one-shot torus 13 (Fig. 6, d). the one-shot 13 is cocked again, i.e. Logic 1 is formed at its output and the process is repeated again. As a result, while at the output of the second comparator (or at the output of the first comparator for the case of decreasing

in all phases) there is a constant level Logic 0, the one-shot 13 starts working as a generator of short pulses (Fig. 6). The pulses from the output AND 12 arrive at the second input of the second element IS-HE 8, the first input of which contains the signal Logic 1 (Fig. 6, d) allowing the passage of pulses to the counting input of the counter 14 (Fig. 6, e). The counter begins to count the pulses generated by the single vibrator 13 until the pin of the counter 14 forms a combination of signals set by the switch 22, as a result of which the actuator operates and disconnects the electrical consumers from the monitored network.

With a decrease in voltage in all phases at once (11 UB), the operation of the device is similar to the operation of the device with an increase in voltage in all phases at once (UK Ue). except that a constant level of Logic 0 appears at the output of the first comparator 5, and not the second 6.

Thus, the proposed device not only provides protection after a predetermined number of short-term voltage drops in the phases of the monitored network, but also in the case of short-term voltage rises, as well as a decrease or increase in voltage over a long period of time in one, several or all phases immediately monitored network. The positive effect of the invention is to increase the reliability of protecting consumers from changes. voltage in a multiphase network and increased noise immunity. The efficiency of the device is especially manifested in its use in multiphase networks that have a reactive load, for example, in motors that can fail due to an increase in voltage or from a phase imbalance. the time (e.g., with a large increase in the friction force of the mechanical parts of the drive) engine can interfere with the network, and other energy consumers, such as secondary power sources, which also need In protection against changes in supply voltage, both short-term and for a long period of time.

Claims (1)

Claims An apparatus for monitoring a voltage in a multiphase network comprising a multiphase one-half-wave rectifier with input terminals for connecting to the phases of the monitored network, a first voltage divider connected to the terminal of a half-wave one-rectifier, and a second terminal to the terminal for connection to the mains zero conductor, one-shot, counter, executive body, and the meter has an additional input; Forbidding is connected to the output. RGANI and The outputs of the bits of the counter are connected to the inputs of the executive body, characterized in that, in order to increase the reliability of protection by ensuring the operation of the device after a predetermined number of both short-term drops and short-term increases in voltage, as well as a result of decrease or increase in voltage during a long time interval in controlled phases 0 network, the second and the third voltage dividers, the first and second voltage comparators, the first and second AND-NOT elements, the three OR elements, the AND element, the delay line and stabilized 5 to the power bus, where the first terminal terminals of the second and third the voltage dividers are connected to a stabilized power bus, and the second end leads are connected to a terminal for connecting to a null conductor of the network, the middle terminal of the second voltage divider is connected to the inverting input of the first comparator, and the middle terminal of the third voltage divider eni - with non-inverting input 5 of the second comparator, where the inverting input of the second comparator and the non-inverting input of the first comparator are connected to the midpoint of the first voltage divider, the output of the second voltage comparator is connected to the first input of the first NAND element and the first input of the first element OR, the output of the first comparator is connected with the second input of the first NAND element and with the first 5 the input of the second OR element, the second input of which is connected to the second input of the first OR element and to the output of the delay line, the input of the delay line is connected to the one-shot output and to the first input 0 of the third OR element, the output of which is connected to the counter zero input, and the second input is connected to the output of the first NAND element and to the first input of the second NAND element, the outputs of the first and second elements 5 OR are connected respectively to the first and second inputs of the element AND, and the output of the element AND is connected to the input of the one-shot and the second input of the second element AND-NOT whose output is connected to the counting input of the counter. g m Fig 3 FIG. five II-PG Ultrasound P P