SU1659881A1 - Device for determining mathematical expectancy of random signal - Google Patents

Abstract

The invention relates to a measurement technique and can be used in stationary random signal analyzers. The purpose of the invention is to increase the reliability of the determination. The device contains a meter 1, keys 2. 3. block 5 summation, counters 7, 8. block 17 division, block 25 of the display. The introduction of the generator 6, the counter 9, the memory block 18, the dividers 19i, 19z, ... 19k, the trigger 16, the comparison block 20, the registers 21. 22, the coincidence block 23, the gate 24. of the key 4 and the delay elements 10-15 provide check input signal for stationarity. If the expectation is not defined for a specified number of clock cycles, the signal is considered non-stationary and the measurement is stopped. 1 IL.

Description

The invention relates to measuring technique and can be used in stationary random signal analyzers.

The purpose of the invention is to increase the reliability of the result of determining the mathematical expectation of a random signal by checking the input signal for stationarity.

The drawing shows a functional diagram of the device.

The device includes a meter 1, first, second, third keys 2-4, a summing unit 5, a clock generator 6, first, second, third counters 7-9, the first sixth delay elements 10-15, trigger 16, the first block 17 divisions, memory block 18, dividers 191.19g ... 19and according to the number of compared values, comparison unit 20, first, second registers 21.22, coincidence unit 23, valve 24, indication unit 25.

The output of the meter 1 through a series-connected key 2 and block 5 summation is connected to the first input of block 17 division. The start input of the generator 6 is connected to the start input of the device, and the output is connected to the counting input of the counter 7, the counting input of the counter 8, the inputs of the delay elements 10-13 and the control input of the key 2. The output of the counter 7 is connected to the second input of the division unit 17, the control input of which connected to the output of the delay element 11, and the output to the information input of the memory unit 18. The control input of the summing unit 5 is connected to the output of the delay element 12. The output of the delay element 10 is connected to the counting input of the counter 9, the input of the delay element 14 and the control input Record of the memory unit 18. The output of the counter 9 'is connected to the information input of the trigger 16, the output of which is connected to the control input of the key 3, the information input of which is connected to the output of the delay element 14, and the output to the control input. Reading of the memory unit 18, the first output of which is connected to the input of the delay element 15 , the second inputs of the dividers 19ι, 19g ... 19i. the first inputs of which are connected to the corresponding other outputs of the memory unit 18, and the control inputs to the output of the delay element 13. The output of the register 21 is connected to the first input of the comparison unit 20, the output of the register 22 is connected to the second input of the comparison unit 20, the remaining inputs of which are connected to the outputs of the respective dividers 19ι, 19g ... 19k. The outputs of the comparison unit 20 are connected to the corresponding inputs of the coincidence unit 23, the output of which is connected to the input of the valve 24, the control input of the key 4, the output of which is connected to the input of the display unit 25, and the input to the output of the delay element 15. The stop input of the generator 6 is connected to the output of the valve 24 and the output of the counter 8. Counters 7-9, trigger 16, memory unit 18 and registers 21, 22 have initial setup inputs.

The device operates as follows.

Preliminarily, the counter 7 is reset to zero, the value N, which determines the moment the device is stopped, is entered into the counter 8, and the value k + 1, where k is the number of compared values in the comparison unit 20, is entered into the counter 9.

The trigger 16 is set to a locked state.

3. The value 1 + Δ is entered into the register 21, the value 1-Δ is entered into the register 22, where 1 ± Δ is the set value. All keys are locked.

To start the device, a start signal is sent to the 6 clock pulse generator. In this case, the pulses from the output of the generator 6 are fed to the control input of the key 2, opening it, to the input of the delay elements 10-13, the counters 7, 8. Through the public key 2, the measured value of the signal x ^ goes to the input of the summing unit 5, which, after arriving at its control input input of the element of delay 12 of the clock N, of the second pulse generates a value of 2, ^x <1 = 1 where N is the number of the current reference. The resulting N value is 2 ^{X |} arrives at the first input i - 1 of the division unit 17, which, after the clock pulse arrives at its control input from the output of the delay element 11, forms

N the quantity “xn = -yy Y ' ^χ ί. This value ^N i = 1 is recorded in the first cell of the memory unit 18 after the arrival of a clock pulse from the output of the input delay element 10. Writing of the memory unit 18, shifting by one cell the information on the values xn-1, xn-2 obtained in the previous steps. As soon as the number of measurement steps (the number of clock pulses) becomes equal to + 1, a pulse appears at the output of counter 9, which changes the state of trigger 16 to the opposite. The signal from the trigger 16 is supplied to the control input of the key 3, opening it. From the output of the delay element 14 through the public key 3, the clock pulse is input to the Read unit 18 of the memory, providing the output of information about the values xn, xn-1, ... XN-k · From the first output of the unit 18 of the memory, the value xN goes to the input of the delay element 15 and the second inputs of the dividers 19 |, where 1 = 1, k, at the first inputs of which from the corresponding outputs of the memory unit 18 the quantities xn-1 arrive. xn-2, .... XN-k. After the arrival of a clock pulse from the output of the delay element 13, the dividers 19i generate the values Xn-i / xn, which are supplied to the corresponding inputs of the comparison unit 20, the first and second inputs of which from the registers 21.22 receive the values 1+ А1-Δ, respectively. When the condition 1- Δ <X] / hm <1 + Δ, J = Nk, N-1 is fulfilled, a signal appears at the jth output of the comparison unit 20, which is fed to the corresponding input of the coincidence unit 23. If there is a signal at all inputs of the matching unit 23, a signal appears at its output, which is fed to the control input of the key 4, opening it. Through the public key 4 from the output of the delay element 15, the value xn is input to the display unit 25 and converted into a convenient form for perception. In addition, the signal from the output of the coincidence unit 23 through the valve 24 is fed to the stop input of the generator 6, stopping it. The process of determining the mathematical expectation of the signal is completed. If during N clock cycles (N> k + 1) the mathematical expectation of a random signal is not defined, then the signal is considered unsteady and measurements are stopped. This is ensured by the fact that when the number of ticks N 'is reached, the counter 8 generates a signal that is fed to the stop input of the generator 6.

Claims (1)

Claim A device for determining the mathematical expectation of a random signal, containing a meter whose output is determined by checking the input signal for stationarity, a clock generator, a third counter, 5 counters, dividers by the number of compared values, a trigger, a valve, a third key,, a memory block are introduced into it , a comparison unit, a coincidence unit, two registers and six delay elements, the start input of a 10-pulse clock generator is connected to the Start ”input of the device, and its output is connected to the inputs of the first and second counters, per of the second, third, fourth delay elements and the control input of the first key, 15 the control input of the division unit is connected to the output of the second delay element, and the output is connected to the information input of the memory block, the output of the third delay element is connected to the control input of the summing unit, the output of the first the delay element is connected to the inputs of the third counter and the fifth delay element and the control input Record a memory block, the output of the third counter is connected to the input of trigger 25 ger, the output of which is connected to the control input the second key, the information input of which is connected to the output of the fifth delay element, and the output to the control input. Reading a memory block 30, the first output of which is connected to the input of the sixth delay element and the second inputs of the dividers according to the number of compared values, the first inputs of which are connected to the corresponding remaining the outputs of the memory block, and the control inputs with the output of the fourth delay element, the outputs of the first and second registers are connected to the first and second inputs of the comparison unit, the remaining 40 inputs of which the number of compared values are connected to the outputs of the respective division blocks, the outputs of the comparison block by the number of compared values are connected to the corresponding 45 inputs of the coincidence block, the output of which is connected through a series-connected first key and summing unit to the first input of the division block, the second input of which is connected to the output of the first counter , a second key, a second counter, an indication unit, characterized in that, c is connected to a valve input and a control input of a third key, the output of which is connected with the input of the display unit, and the input with the output of the sixth delay element, the stop input of the clock generator is connected to the output of the valve and the output for the purpose of increasing the reliability of the resulting counter.