SU1659181A1 - Data transmission system - Google Patents

Description

The invention relates to welding and can be used to supply power to the network of welding stations with remote control of the mode of their work in real time. The purpose of the invention is to increase the reliability of receiving information on the power grid and reducing the power of the transmitters. The data transmission system comprises a signal source, a transmitter, a communication line, a receiver and a display device. The power grid (~ 220 V 50 Hz) is used as a communication line. Peredat Invention is related to welding and can be used to supply power to the network of welding posts with remote control of their mode of operation in real time.

The aim of the invention is to increase the reliability of receiving information on the power supply network of 220 V 50 Hz and reducing the power of the transmitters.

2

the system is equipped with a pre-; education, a pulse modulator, a selective amplifier, a power amplifier, a 50 Hz driver, a pulse generator, and an output device. An input device, a 50 Hz driver, a control unit, an address counter, analog-to-digital and digital-to-analogue converters, two groups of I schemes, 2-2I-2IL or 2 schemes group, two operative memories, a register and a subtractor are entered into the receiver.

The data transmission system produces a digital delay of all voltage components of the power grid for the period of the first harmonic. With such a _β delay of all voltage components of the power grid, the phase relations between the first and other voltage components of the power grid do not change, since the frequencies of the higher harmonics of the power grid are multiple of the frequency of the first harmonic. Compensation of higher voltage harmonics is made.

1 hp f-ly, 8 ill.

Figure 1 shows the block diagram of the data transmission system; Fig.2 is a block diagram of a receiver of a data transmission system; FIG. 3 shows timing diagrams of operation of the control unit of the receiver of the data transmission system; 4 - a view of an alternating voltage in a power supply network of 220 V 50 Hz (b - harmonic networks making up at Ц _г = 0, 0, ψ _1π = 0; in 5 Ц „„ 1659181 А1

3

four

the same, with θ ’^" 3 θ "ψιη θ" g - harmonic compensation in (± + 1) -th period; e - the same, if there is information; e - selection of the information signal in the (ϊ-Μ) -μ period; on figa - input device and output data transmission system; on figb block diagram of a group of circuits 2-2I-2IPI; FIG. 6 is a block diagram of a device for converting a receiver of a data transmission system and timing diagrams of its operation; FIG. in fig. 7 - temporary positions of the signals necessary for the operation of the RAM; on Fig - temporary position of the signals on the subtractive device and the output of the receiver.

The data transmission system (Fig. 1) consists of a signal source 1, which includes a sensor 2 and an analog-digital converter 3, a transmitter 4, including a conversion device 5, a 50 Hz 6 driver, a pulse generator 7, a pulse modulator 8, a selective amplifier 9, and an amplifier 10 power output device 11 and a transformer. 12, the communication line 13 (power supply 220 V 50 Hz), the receiver 14 and the display device 15.

The receiver 14 (FIG. 2) consists of an input device 16, a 50 Hz driver 17, a control unit 18, an address counter 19, an analog-to-digital converter 20, a counting trigger 21, circuit groups 22, 23, memory 24, 25, a circuit group 2-2-2ILI 26, register 27, digital-to-analog converter 28, subtractive device 29 and key 30.

The output of the sensor 2 is connected to the input of the analog-digital converter 3. The output of the analog-digital converter 3 is connected to the output of the signal source 1, which is connected to the input of the transmitter 4.

The first input of the conversion device 5 is connected to the input of the transmitter 4. The second and third inputs of the conversion device 5 are respectively connected to the first and second outputs of the 50 Hz shaper 6. The output of the conversion device 5 is connected to the first input of the pulse modulator 8. The second input of the pulse modulator 8 is connected through serially the selective amplifier 9 and the power amplifier 10 are connected to the input of the output device 11. Output device 1659181

The output 11 is connected to the primary winding of the transformer 12, the secondary winding of which is connected to 5 50 Hz 6 drivers. The output of the transmitter 4 is connected to the output of the output device 11 and the phase of the power network 13 (220 V 50 Hz). The input of the receiver 14 is connected to the phase of the power network of 220 V Yu 50 Hz and the first input of the display device 15, the second input of which is connected to the output of the receiver 14.

The input of the input device 16 is connected to the input of the receiver 14. The output of the input device 16 is connected to the measuring input of the analog-digital converter 20 by the input of the 50 Hz 17 former and the first input of the subtractor 29. The former 20 and 50 Hz 18 outputs are connected respectively to the first 31 and second 32 inputs of the control unit 18. The third input 33 of the control unit 18 is connected to the single output of the counting trigger 21, the first input of the AND 23 circuit group and the first input of the 2-2I-2ILI 26 circuit group. The first output 34 of the control unit 18 is connected to the first input of the register 27. The second output 35 the control unit 18 is connected to the zero input of the address counter 19. The third output 36 of the control unit 18 is connected to the counting input of the counting trigger 21. The fourth output 37 of the control unit 18 is connected to the clock input of the analog-digital converter 20. The fifth output 38 of the control unit 18 is connected to the counting input of the counter 19 and the trigger input of the analog-digital converter 20. The sixth output 39 of the control unit 18 is connected to the second input of the AND 23 circuit group and the first input of the AND 22 group of circuits. The seventh output 40 of the control unit 18 is connected to the first input of the key 30. The eighth output 41 (parallel output) of the control unit 18 The adapter is connected to the first memory input 24. The ninth output 42 (parallel output) of the control unit 18 is connected to the first memory input 25. The output of the address counter 19 (parallel code) is connected to the second memory inputs 24, 25,

The output of analog-to-digital Converter 20 (parallel course) is connected to the second input of a group of circuits And 22

and the third input of the circuit group. And 23.

Zero output of the counting trigger 21

five

1659181

6

connected to the third input of the group of circuits And 22 and the second inputs of the group of circuits 2-2I-2ILI 26. The output of the group of circuits; And 22 (parallel code) is connected to the third input of the group of circuits 2-2I-2ILI 26 and the third input of memory 24. Output the group of circuits And 23 (parallel code) is connected to the fourth input of the group of circuits 2-2I-2ILI 26 and the third input, θ of memory 25. The output of the group of circuits 2-2I-2ILI 26 (parallel code) is connected to the input of the register 27, the output of which ( parallel code) is connected to a digital-to-analog code input, 5

Converter 28. The output of the D / A converter 28 is connected to the second input of the subtracting device 29. The output of the subtracting device 29 is connected to the second input of the 20 key 30, the output of which is connected to the output of the receiver 14.

Block 1 - signal source, is the source of information. The signal source 1 consists of sensor 2 and analog-to-digital converter 3.

Block 2 - sensor, is the primary converter.

Block 3 - analog-to-digital converter, converts the analog 30 value into a digital code. A 572PV1 analog-to-digital converter with an 574UD1 operational amplifier and a 323 SAZ comparator is used.

Block 4 - transmitter, conventional trans. Long range transmitter.

Block 5 is a conversion device. The conversion device (Fig. 6a) is intended to convert the parallel code of the analog-digital converter 3 into a serial code. Each digit of the sequential code is allocated on the positive half-wave of the mains voltage of 220 V 50 Hz, and the pulse duration does not exceed 10 ms.

Each discharge of the sequential code is separated from the adjacent discharge for two periods of the mains voltage - 220 V and 50 Hz. In the conversion device 5, the parallel code of the analog-to-digital converter 3 is mapped to the mains voltage by the signals generated by the driver 6. The conversion device 5 consists of a register 43, circuits And 44,

45, schemes OR 46, schemes AND 47,. shift register 48, the decoder 49,

divider 50, trigger 51, divider 52, and pulse generator 53.

Block 43 is a register, the usual logical element.

Block 44, 45 - And the scheme, the typical logical element.

Block 46 is an OR circuit, a typical logical element.

Block 47 is the AND circuit, typical logic element.

Block 48 is a shift register, typical logical element.

Block 49 is a decoder, a typical logical element.

Block 50 - divider, typical logical element.

Block 51 is a trigger, a typical logical element.

Block 52 - divider, typical logical element.

Block 53 is a pulse generator, a typical element of discrete technology and can be built on 155LAZ. .

Code Νί. from the signal source is fed to the input "1" and to the register 43. The signals of the generator 53 of the pulses go to divider 52. The signal of the divider 52 writes "1" to the shift register 48. Then this unit is shifted in the register by 48 clocks generated by the decoder 49 from the signals of the divider .50. The signals of the divider 50 are formed from the signals of the trigger 51 by the signals received at "Input 2" and "Input 3" (Fig. 6) at the moments of zero crossing of the positive and negative half-wave of the mains voltage of 220 V 50 Hz. the simultaneous presence of two single signals at the inputs of circuits And 44 , 45, each of these circuits generates a control signal to the OR circuit 46. Thus, the parallel conversion of the code Ν · to the serial one takes place. When the control signal is accessed to the “Input 3” circuit And 47, the serial code is output to the device output.

Block 6 is a 50 Hz shaper, a conventional device that generates the zero-crossing signals of the positive and negative half-wave of the mains voltage of 220 V 50 Hz and has two outputs from the mains voltage signals of l / 220 V 50 Hz. The device consists of two comparators, the voltage τοροЗ of 321 SAZ, determining the moments of zero crossing to 7

1659181

eight

positive and negative half-waves of the mains voltage.

Block 7 is a pulse generator, a conventional pulse generator. ,

Block 8 - pulse modulator, is a common key.

Block 9 - selective amplifier, the usual selective link.

Unit 10 - power amplifier, 1

ordinary power amplifier.

Unit 11 is an output device (Fig. 5a), which is a device that connects a power amplifier to a power grid of 220 V 50 Hz, and] consists of a transformer Tp and a capacitor C connected to the secondary winding of the transformer.

Block 12 is a transformer, a common element of electrical measuring instruments.

Block 13 - communication line, is the power supply g * 220 V 50 Hz.

Unit 14 - receiver, typical receiver. ί

Block 16 - input device (figa), the input device of the receiver 14, consists of a transformer Tr and a divider consisting of capacitors C1, C2, included in the secondary: the transformer winding Tr.

Block 17 - a 50 Hz shaper is a common threshold device that generates zero-crossing signals for the positive and negative half-wave of the mains voltage from the mains voltage of l / 220 V 50 Hz. The device consists of two voltage comparators 512SAZ, emit moments of zero crossing, respectively, but positive or negative half-waves of the mains voltage.

Unit 18 is a control unit that serves to synchronize the operation of the receiver 14 and issues command signals to the corresponding blocks of the receiver 14 at certain points in time (FIG. 3).

The control unit 18 generates control signals according to the input signals of the 50 Hz shaper 17, it determines the binding of the control signals to the moments of transition of the positive and negative half-wave of the mains voltage l / 220 V 50 Hz through zero. In addition, the control unit 18, in accordance with the signals of the counting trigger 21, generates control pulses in a certain sequence, which ensure that information is written (read) into two memories 24, 25. At the same time, one period of mains voltage at the same address in memory 24 records the coded information, and from the memory 25 is read information. In the next period of the mains voltage, information is read from memory 24 into the writing of coded information into memory 25. Block 18 provides the following control signals necessary for the operation of the receiver:.

The signal to reset the counter 19 addresses the output 35.

The control signal of the counting trigger 21 at the output 36.

The start signal analog-to-digital Converter 20 and the counting signal of the counter 19 addresses the output 38.

The signal supplied to the clock input of the analog-to-digital converter 20 at the output 37.

The enable signal to groups of circuits And 22, 23 output 39.

The recording signal arriving at register 27 at output 34.

Signal release information arriving at the CLUSCH 30, the output 40.

The write signal (read), fed to the memory 24, the output 41.

The write signal (read), fed to the memory 25, at the output 42.

Write (read) signals 41,

42 are complex signals and are formed at two outputs, since these signals are used to, in addition, select memory chips 24, 25, which are serially produced by I (537RU13, 541RU6). Figure 7 shows the temporal positions of the signals for recording (reading) information, addresses of information, information.

Block 19 - the address counter, the usual logical element. The standard binary decimal counter 155IE2 can be used. The ADC K 572PV1 with the 574UD1 operational amplifier and 52ISAZ comparator is used.

Block 21 is a countable trigger, the usual logical element.

Block 22, 23 —A group of circuits, one for each digit, 564 LA9 may be used.

Block 24, 25 - memory, operational

Memory device. It can be ¹ ·

vary 537RU13.

9

1659181

ten

Block 26 is a group of circuits 2-2I-2IPI, one for one bit. 155LR1 can be used. Figure 5 shows a diagram of a group of circuits 2-2I-2ILI 26. $

The group of circuits 26 consists of AND 5457 circuits and OR 58 and 59 circuits. Block 54 - 57 AND schema, is a typical logic element, 155 LAZ can be used. Block 27, 58, 59 - scheme OR, S is a typical element, 155LAZ can be used.

Block 27 is a register, the logical element used to store information can be used 564ТМЗ.

Block 28 is a digital-to-analog converter, a tic element, a DAC To 572PV1 can be used in conjunction with an operational amplifier 574UD1.

Block 29 is a subtractive device, a common element designed to subtract two analog signals.

Block 30 is the key, the usual logical element.

Block 15 is a display device designed to indicate received information. Received information can be displayed as synchronously with the frequency of the power network of 220 V 50 Hz, and not synchronously. In the first case, the voltage L / 220 V 50 Hz is entered into the display device.

The operation of the data transmission system is as follows.

The message generated by signal source 1, consisting of sensor 2 and analog-digital converter 3, is fed to transmitter 4 in discrete form. In the conversion device 5, the message is converted into pulses synchronous with the beginning of the power grid period ~ ^ 220 V 50 Hz, the duration of which equal to the half-period of the power network 220 V 50 Hz, i.e. their duration is 10 ms. Such a pulse duration is due to a carrier frequency of 1 kHz. In this case, 10 periods of the carrier frequency fit into the pulse. The transmitted signals are formed in two periods - every third period - of the power grid. The signal of the binding of the transmitted pulses to the frequency of the power grid is formed by the 50 Hz 6 driver from the network signal l / 220 V 50 Hz 13, which is fed to the primary winding of the transformer 12. The 6h driver outputs one by one 20

25

thirty

35

40

45

50

55

To the move, the zero crossing signal of the positive half-wave of the power voltage, and on the other, the zero-crossing signal of the negative half-wave. The converted primary signal from the converter 5 is supplied to a pulse modulator 8, the second input of which receives signals from a pulse generator 7, whose frequency is 1 kHz. At the output of the pulse modulator 8 are allocated pulses. The duration is 10 ms, i.e. in a pack there are 10 pulses. In the selective amplifier 9, the rectangular pulses (bundles) of the modulator 6 are converted into radio pulses (sinusoidal). After amplification in the amplifier 10 power (radio pulses), the signals of the selective amplifier 9 through the output device 11 are fed into the communication line (power electrophoto22O 50 Hz 13). In the receiver, after the input device 16, the analog-to-digital converter 20 is turned on. And the 50 Hz driver 17, the 50 Hz driver 17 generates from the mains voltage the timing signals necessary to separate the transmitted message from the mains voltage. One stands out at the moment of zero crossing of the positive half-wave of the mains voltage, the other at the moment of zero crossing of the negative half-wave.

The signals of the 50 Hz shaper 17 control unit generates the signals necessary to synchronize the operation of the receiver 14, i.e. to highlight the message transmitted by the power supply ~ 220 V 50 Hz. The message is highlighted in a positive half-wave of the mains voltage. The timing diagrams of the operation of the control unit 18 are shown in FIG. At the moment of crossing the zero positive half-wave of the mains voltage, the control unit 18 at the output 35 generates a signal that resets the address counter 13. In addition, according to the signal at the output 36 of the control unit 18, the calculating trigger 21 starts to change from one state, for example zero, to one, etc. When the trigger 21 is installed in the unit state, the zero output of the trigger 21 provides the permitting potential to the group of circuits I 22 and the second control input of the group of circuits 2-2I-2ILI 26.

eleven

1659181

12

The coding of the positive half-wave of the mains voltage of 220 V 50 Hz is performed by an analog-to-digital converter 20. To start up the converter 20, a signal is output from the output 38 of the control unit 18. After the conversion is completed, the converter code 20 through the group of circuits And 22 enters memory 24 and is stored in it at the address formed by the address counter 19 at the moment when the signal at the output 41 of the control unit 18 is present. At the same time, at the same address, information is read from memory 25 at the moment when a signal is present at the output 42 of control unit 18. The information '(code) from the memory 25 is fed to the second measuring input of the 2-2I-2ILI 26 circuit. The signal of the 2-2I-2ILI 26 circuit (parallel code) is fed to the register 27, where it is stored in the presence of an enable signal at the output 34 of the block 18 management. The address counter 19 counts the start signals (sampling) of the analog-to-digital converter 20.

In the subsequent period of the mains voltage ^ 220 V 50 Hz, trigger 21 changes its state. It provides the resolving potential from a single output to a group of circuits AND 23 and the first control input of a group of circuits 2-2I-2ILI 26. The prohibitive potential is fed to the second control input of a group of circuits 2-2I-2ILI 26 and a group of circuits I22.

¹ After the end of coding, the code Νΐ of the converter 20 through the group of circuits And 23 enters memory 25 and is stored in it at the address generated by the address counter 19 at the moment of the presence of the signal at the output 42 of the control unit 18. At the same time, information is read from the memory 24 at the same time at the moment when a signal is present at the output 41 of the control unit 18. Information (code) is fed to the first measuring input of a group of 2-2I-2SHII circuits 26. The signal of circuit 26 (parallel code) is fed to register 27, where it is stored in the presence of an enable signal at output 34 of control unit 18. The temporal positions of the signals required for the operation of RAM .24, 25 are shown in FIG. 7. In the ΐ-th period of the mains voltage from the output 41 to the memory 24 receives a recording signal, and from the output

42 to memory 41 is a read signal.

In (ίί-1) —the period of the mains voltage from output 41 to memory 24 receives a read signal, and from output 42, write sigils, etc. Converting the current digital code N / samples to register 27 into an analog signal is performed by a digital-to-analog converter 28. Thus, the subtracter 29 subtracts from the network voltage (ί + 1) -Γ0 a period of the network voltage of the-th period delayed by mains voltage. Timing diagrams of the subtractor and the key 30 are shown in FIG. 8. At the output of the receiver 14 in the presence of a signal transmitted by the transmitter 4, there are two pulses in a positive half-wave of the mains voltage in ί- and (ί + 1) -Μ periods. The signal from the output of the receiver 14 is supplied to the display device 15. The presence of signals in two adjacent half-waves of the mains voltage uniquely corresponds to the signal of the transmitted information.

Compared with the prototype, this system has a higher reliability of the received information, which is due to the compensation of the higher harmonic components (background) of the power network voltage ^ 220 V 50 Hz. To do this, at each moment in time, the signals of the ί- and (ί + Ό-th periods of the network containing harmonic components are in antiphase). For this purpose, a digital delay of all voltage components of the power network for the period of the first harmonic is performed. At the same time, the phase relationships between the first and the rest of the harmonic voltage components of the power network.

Improving the reliability of the transmitted information in comparison with the prototype allows you to receive signals from the recipient at a distance of 5-10 km from the radiation source.

In addition, the transmitter power has decreased significantly and is 5 W with a transmitter output of 100 mV. Experimental tests of the layout of the device manufactured in accordance with the invention have confirmed the possibility of reliable data transmission over a distance.

2.5 km of power network .Ν 220 V 50 Hz.

13 '

1659181

14

Transmitter power 5 watts. The output signal is about 100 mV. The attenuation per 100 m was 1.22. The radio pulse duration is 10 ms. Carrier frequency 1.2 kHz.

Claims (1)

Claim 1. A data transmission system containing a signal source, states from a series-connected sensor and a first analog-digital converter, a transmitter connected to a signal source, a receiver, a communication line made in the form of a power grid, connected between? do the transmitter output and the receiver input, and a display device connected to the receiver output, which is that, in order to increase the reliability of receiving information and reduce transmitter power, the transmitter includes a conversion device, the first 50 Hz generator, a pulse generator, a pulse modulator, a selective amplifier, a power amplifier, an output device and a transformer, the primary winding of which is connected to the output of the transmitter and the output of the output device, whose input is through a sequence A connected power amplifier, a selective amplifier and a pulse modulator are connected to the output of the conversion device, whose inputs are respectively connected to the first and second outputs of the first 50 Hz driver and the transmitter input, the second input of the pulse modulator is connected to the output of the pulse generator, the secondary winding of the transformer is connected to the input the first driver 50 Hz, the receiver includes input devices, the second driver 50 Hz, the control unit, the address counter, the second analog-digital conversion ovatel, counting trigger, two groups of AND circuits, two memory cell group 2-2I-2or circuit, a register, a digital to analog converter, a subtracter and a key connected between the receiver output and the output of the subtracting device ^ the first input of which is connected to the output of the digital-analog converter, the second input of the subtractive device is connected to the output of the input device, to the input of the second driver 50 Hz and to the first input of the second analog-digital converter, the output of which is connected to the first inputs of the first and second groups of circuits And, the second input of the first group of circuits And is connected to the zero output of the counting trigger and the first input of the group of circuits 15 2-2И-2ИЛИ, the second input of which is connected to the single output of the counting trigger and the second input of the second group of circuits And, the output of the first group of circuits And connected to the first input of the first 2d memory cells and the third input of the 2-2I-2ILI group of circuits, the fourth input of which is connected to the output of the second group of circuits I and to the first input of the second memory cell, the output of the group of circuits 25 2-2И-2ИЛИ are connected through .registr to the digital-to-analogue converter, the inputs of the control unit are respectively connected to the first output of the second driver 50 Hz, 30 with the second output of the second shaper 50 Hz, with a single output account. first trigger, the outputs of the control unit from the first to the ninth, respectively, are connected to the third inputs _ first and second groups of circuits AND, with zero input of the address counter, counting input of the address counter and triggering input of the second analog-digital converter, clock input of the second analog-digital converter, second register input, second key input, counting input of the counting trigger, second input the first memory cell, with the second input of the second memory cell, where the output of the address counter is connected to the third inputs of the first and second memory cells, and the input of the input device is connected to the output of the receiver. 2. The system according to claim. ^ Characterized by the fact that the second input of the display device is connected to the power mains. 1659181 1 1659181 1.1 .. W_N111 I I! I I Ы _Ш.1 I_1_1_Ш_I I I I I_ here _{x x} —— 1-1 = 1 - [= □ -Г = 1 __-. 32. .. .. - 1 --—: - 1. ____________ □ _ y # ppplp ΊΠΠΠΠΓ pppt ΊΠΠΠΠΓ ___ 42 rLPPPE_PPPP_ΊΠΠΠΠΓ ................ pppp _ PYOD & —ALLALL-νΐΜΛΛΛΛ -........ 'ULLLLL, -CHAAL / b Fi.Z FIG. four 1659181 ~ 1 but about · - 731ΓΉ ~ ^ ШВ50Г ^ ~ ' one .one ι *: B_: Ί with, Ν. ϊ '4 R five υΰ 7 ⁱⁱ from (rit. Input ί 2 °° tsme, rit. go { Fi'§ Gd-1 input ------------------- 1— .G 0 — A__. --1 ---- .YH05G III 1 1 1111 I III 1 II 1111 .Input 0-1.1-.1 ..... 1 ... Ι 1 ..... 1 ...... IL-1 ... ..1.-1-.1.,. 1 .1 ..- 11 .1 I .. 3 ’0 ПП ПППП ПП П ПП-.П.П.П.П.П.П.П-П..П 'Ha η Π Π Π P_ □ _ □ _ M'o-P - w— □ _— □ -: - □ _ FIG B 1659181 nineteen 22.23 ——- у - у ~ --- \ · / 7 Output o— / ALAL-CHP -chMFg-MLG -Mmg Fig.8