SU1596461A1 - Angle digitizer - Google Patents

Abstract

The invention relates to automation and computer technology and can be used in automatic motor control systems for inputting angular values into a digital computer. In order to improve the accuracy of the angle-code converter, which contains a pulse generator, the first counter, ROM, two DACs, a phase shifter, a filter, a pulse shaper, the element I, a low-order trigger, a sample matching unit, a phase discriminator, a trigger trigger, a control unit , third and fourth counters, register. In the converter, a combined conversion method is implemented: the high and low bits are determined by the method of reading the traveling mark, and the low - by the method of accumulation, which allows to increase the frequency of the pulse generator. 2 hp f-ly, 3 ill.

Description

The invention relates to automation and computer technology and can be used in systems for automatic control of a DJI motor to input angular values into a digital computer.

The aim of the invention is to improve the accuracy of the converter.

FIG. 1 shows a flowchart of a converter; FIGS. 2 and 3 are timing diagrams of the converter operation for the rotation angle of the rotor of the phase shifter 2 and 2.5, respectively.

Angle converter - code contains phase shifter 1, counter 2, read-only memory 3 (ROM), digital-to-analog converters 4.5 (DAC), 6 pulse generator, filter 7, shaper 8 pulse, trigger 9 low-order, block 10 sample matching , phase disk riminator 11 (for example, trigger), trigger 12, synchronization, element I 13, counter. 14, counter 15, register 16, control block 17.

The matching unit 10 comprises a D-flip-flop 18, two I-19, 20 elements, an inverter 21, and an IPI-HE element 22.

The control unit 71 contains a D-flip-flop 23 and a decoder 24. Angle converter - the code works as follows. The higher bits (n + m) of the first first counter 2 form the highest kbdovy scale of the converter. To the m bits of the second counter 14, the sample of the lower time scale of the converter and finally the youngest bit of the converter code is formed at the output of the trigger 9. The pulses from the output of the generator 6 (Fig. 2a) are fed to the input (n + m) of the first discharge counter 2, at the outputs of which pulses appear divided by the frequency of the bits (Fig. 2b, c, d) and p 2 (Fig. 2 d, e). Counter 2 generates the address codes of the persistent storage device 3, in which the sine and cosine functions are recorded. Function codes appear at the inputs of the first 4 and second 5 digital-to-analog converters, the outputs of which form analog voltages, respectively, sinusoidal (Fig. 2g) and cosine (Fig.2z form. These voltages are fed to the inputs of the phase shifter 1 as reference signals. At the output of the phase shifter 1, a signal appears (Fig. 2i), shifted in phase relative to the reference signals by an angle proportional to the mechanical control of the rotation of the rotor of the phase shifter. This voltage is fed to the input of the filter 7, which suppresses high the frequency components of the input voltage of the phase shifter 1, obtained from the outputs of the digital-to-analog converters 4, 5. as well as interferences, induced in the lines to the phase rotator 1 and from it. The voltage from the output of the filter 7 is fed to the input of the first pulse shaper, on the output of which (rectangular 1-1 pulses are formed (Fig. 2k), the front fro that coincides with the moment when the output voltage of the phase shifter passes through zero passing through the filter 7. The pulse from the output of the first driver 8 pulses is fed to the synchronization input the trigger 9, to the input D of which pulses from the generator 6 arrive, fixing on its leading front a half-cycle of the frequency of the pulses of the generator 6 at the instant the output signal of the first is formed and forms 8 (FIG. 2l) Thus, the lowest bit of the output code of the converter is realized. From the output of trigger 9, the low-order code goes to the output of the converter. In addition, the pulse from the output of the first generator of 8 pulses is fed to the first input of phase discriminator 11. The output of phase discriminator 11 is a signal of level 1, the leading edge of which coincides with going through zero of the output signal of phase shifter 1. To the second input of phase discriminator 11 the signal of the oldest of the m least significant bits of the first counter 2 (fig. 2d) is received, passing through the matching unit 10 (fig. 2m). On the leading edge of this signal, the phase discriminator will go to the zero state. Thus, the output of the phase discriminator 11 is a turn of the signal corresponding to the time interval from the moment of passing through the zero output signal of the phase shifter to the leading edge of the output signal of the oldest of the m bits of the first counter 2 (Fig. 2n). Since the state of the first trigger 9 in this measurement cycle (Fig. 2L) is zero, the output signal of the oldest of the m bits of counter 2 goes to the second input of the phase discriminator from the output of the most significant of m bits of counter 2 without delay. Since the trigger 9 is in the zero state, the output of the inverter 21 has a level log. 1, neither the second input of the second element AND 20 comes in, while the log level O. from the output of the trigger 9 enters I 3 the first input of the first element AND 19. Therefore, the element 19 also is closed and AND 20 is open and the signal from the senior output of m bits of the counter 2 through the element AND 20, the element OR NOT 22 passes to the second input of the discriminator 11 without delay (Fig. 2m). The pulse from the output of the phase discriminator 11 (Fig. 2n) arrives at the input of the synchronization trigger 12, at the output of which a pulse appears containing an integer number of periods of the frequency of the clock pulses of the generator 6 (Fig. 2 o). This impulse arrives at the first input of the element I 13, at the second input of which the pulse of the clock generator 6 is received (Fig 2a). At the output of the element And 13 appear them pulses corresponding to the number of clock periods, laying down gxc in the time interval from the moment of transition of the signal of phase shifter 1 through zero to the moment of transition of the signal of the highest m bits of counter 2 (Fig. 2n), which arrive at the subtracting input of counter 14. Counter 14 initially and at the end of each measurement period is set to zero. Thus, the counter 14 measures the time interval from the moment of transition through the zero output signal of the float spreader 1 to the moment of transition of the highest part of the bits of counter 2, corresponding to the moment of switching the high code scale n bits, but in the reverse code that corresponds to measuring the time interval from the moment of switching the highest code scale n bits to the moment of going through the zero of the output signal of the phase shifter. On the falling edge of the signal of the phase discriminator 11, the control block 17 is activated. When this is established, the unit 23 of block 17 (Fig. 2p) is installed in unit t, and an enabling signal appears at the enable input P of the de encoder 24. In this case, a series of control pulses appears at the outputs of the decoder 24, corresponding to the states of the lower bits of counter 2. The first of these pulses (Fig. 2c) records the high n bits of counter 2 into counter 15, the second pulse (Fig. 2t) subtraction from the contents of the counter 15 units takes place. Consequently, in counter 15, the state of counter 2 at the time of passing through the zero of the phase shifter signal will be restored. On the third pulse (Fig. 2y), the contents of counter 14 and counter 15 are set to the output register 16. To the value of the n-digit code of counter 15 The value of the K-bit code of the counter 14 is compacted (docked), the low-order value of the angle code corresponding to the half-period of the clock pulses of the generator 6 is already at the output of the trigger 9. Thus, the full output code of the converter is formed - the code. On the fourth pulse (Fig. 2f), the counter 14 is reset to prepare it for the next measurement. Finally, the fifth pulse, which appears at the corresponding output 15 of the decoder 24, sets the trigger 23 to the zero state (Fig. 2p) i, stopping the operation of the control unit 17. FIG. Figure 2 shows the timing diagrams of the converter operation for the cases when the angle is equal to two samples, while the trigger 9 indicates the zero state of the half cycle of the clock pulses of the generator 6. The counter 14 counts from O to K 2. In the counter 15, the code is n 8 (taking into account the state of m bits of the counter 2, 2 2 8), with the subsequent subtraction of its single state changes to n 0. This state of n O, K 2 is entered in register 16. Thus, the output code n + K + +, 5 O + 2 + O 2-discrete. FIG. Figure 3 shows the timing diagrams for the operation of the converter for the case when the angle is equal to 2.5 samples. In this case, the trigger 9 us-. is forced into the unit state, and the reset signal of the phase discriminator 11 passes through the D-flip-flop 18 with a delay of one clock relative to the initial one, element 19, the element OR-NOT 22 (Fig. 2m), however, after synchronization on trigger 12, the duration of the time interval (compared to the case in FIG. 2), the counter 14 counts the same number of pulses. Further operation of the converter occurs in the same way. The output code in this case is n + K + Op-0.5 O + 2 + 1-0.5 2.5 discretes. Thus, in the angle-code converter, a combined method of transformation is realized: the highest and the lowest bits are determined by the method of matching the running mark, the low bits by the accumulating method. This makes it possible to lower the switching frequency of the bits of counter 2, from which the high-order bits are read. Counter 15 is needed to recover the code counted from counter 2 at the time of the trigger of the older of the m low-order bits, to the value that counter 2 has at the moment of going through the zero output signal of the phase shifter. If counter 15 is not used, the output code of the angle transducer - the code will have a constant offset equal to the capacity of the second counter 14. If the offset

the zero of the phase shifter is not essential for the operation of the converter; the input of register 16 is connected with the output of counter 2 without counter 15.

In the proposed device, the code is written from counter 2 to 15 only for the higher bits and, therefore, at a lower frequency than the generator,

eliminates read error since at the moment of recording the state of the counter does not change. Separating and measuring (at the maximum frequency) the time interval due to crossing the zero voltage across the phase shifter to the leading edge of the output signal of the oldest of the least significant bits allows increasing the dynamic accuracy of the angle-code converter.

In addition, the introduction of a low-level trigger, primarily intended for controlling the sample matching unit 10, further doubles the accuracy by determining which of the half-periods of the pulse generator transits through zero voltage from the output of

All this refers to fixed. the frequency of powering the phase shifter, i.e. to the frequency of information from the converter at its fast response. Since the position sensor itself — the phase shifter in its physical principle of operation — is an inductive transducer and uses frequency methods of signal conversion to remove information, the speed and accuracy are interrelated. With

Equal circuit solutions the higher the accuracy of the converter, the lower the speed and vice versa. However, many phase shifters, such as the PV-67, have a fixed value for the frequency of the supply voltage — 2000 ± 100 Hz. Certain speed requirements put forward and installations that use angle-code converters, such as AC electric drives. In terms of accuracy, the requirements are usually not as stringent: they should be no worse than a given value. Therefore, the positive effect is evaluated at a fixed speed.

Claims (3)

1. Angle converter - a code containing series-connected pulse generator and the first (p + ha) bit counter, the output of which is connected to the input of a permanent storage device, the outputs of which through the first and second digital analogue converters are respectively connected to the corresponding inputs of the phase shifter, the output of which through the filter is connected to the input of the pulse shaper, element I , characterized in that, in order to improve the accuracy of the converter, a low-order trigger has been introduced into it; a sample matching unit, a phase discriminator, a trigger trigger, a control unit the second and third counters and the register, the output of the pulse driver is connected to one input of the phase discriminator, the C-input of the low-level trigger, the output of the pulse generator is connected to the D-input of the third-party sampler, the C-input synchronization trigger (Zacia and one input of the AND element, the output of the low-order trigger is connected to the second input of the sample matching unit, the output of which is connected to another input of the phase discriminator, one output of which is connected to the D input of the trigger synchronization, the output of which is connected by another input of the element I, the output of which is connected to the counting input of the second counter, the outputs of which are connected to the first group of inputs of the register, another output of the phase discriminator is connected to the first input of the control unit, the second input of which is connected to the output of the th-th bit the first counter, the outputs m of the lower-order bits of which are connected to the group of inputs of the control unit, and the outputs n, the older bits of the first counter are connected to the corresponding inputs of the third counter, the outputs of the control unit and the first to the fourth are connected respectively to the input of the installation of the third counter, its subtracting input, the register entry input, the second counter zeroing input, output # 1 of the third counter connected to the second register input group, the output of the 10th digit of the first counter connected to the third input the matching unit, the samples, the register and the low-order trigger are the outputs of the converter. 15 2. Converter according to claim 1, characterized in that the sample matching unit contains a trigger, an inverter, two AND elements, whose outputs are connected to the inputs of the OR-NOT element, whose output is the output of the block, the C input of the trigger is the first input block, and the D input is the third input of the block, the inverter input is the second input of the block and is connected to one input of the first element AND, the other input of which is connected to the output of the trigger, whose D input is connected to one input of the second element AND, the other input connected to the output of the inverter. W 15 P 3. The converter according to claim 1, characterized in that the control unit contains a trigger and a decoder, the information inputs of which are a group of block inputs, the synchronization input is the second input of the block, and the enable input is connected to the trigger output, the D input is connected to the logical unit bus, the C input is the first input of the block, the outputs of the first to fourth decoder are outputs of the first to fourth block, and the fifth output of the decoder is connected to the R input of the trigger.