SU1569954A1 - Digital frequency discriminator - Google Patents

Abstract

The invention relates to a pulse technique. The purpose of the invention is to improve the accuracy of frequency discrimination. The digital frequency discriminator contains an amplifier-limiter 1, waiting for Mr. r. 2 clock pulses, inverter 3, counter 4, frequency selectors 5, driver 6 pulses, triggers 7, AND-NOT 8 el-devices and delay el-9. Input sinusoidal the signal is converted to meander. It enters simultaneously at the IS-NE 8 via inverter 3, on triggers 7, on r-2 and on shaper 6 and on-delay 9 on counter 4, which counts the number of pulses from r-2 proportional to the input signal. This code is sent to the selectors 5, and then to the trigger 7. The unit state of the trigger 7, corresponding to the required code of the input signal period, controls the operation of the corresponding el-AND-HE 8, allowing the input meander signal, corresponding to the selected period, to pass to the output devices. Thus, at each output of the device, a meander input signal of only one selected frequency appears. 2 Il.

Description

1

The invention relates to a pulse technique and can be used for filtering, distinguishing frequency-modulated signals in the construction of digital systems for the transmission and processing of discrete information.

The purpose of the invention is to improve the accuracy of frequency discrimination.

Figure 1 shows the electrical block diagram of a digital frequency discriminator; Fig. 2 shows timing diagrams for details of the work of the discriminator.

The digital frequency equalizer contains a limiting amplifier 1, a waiting generator of 2 clock pulses, an inverter 3, a counter 4, N frequency selectors 5, a driver of 6 pulses, N triggers 7, N elements AND –NE 8, delay element 9, input 10 and exits 11.1-11.N.

Digital frequency discriminator works as follows.

The sinusoidal frequency signal arriving at input 10 (Fig. 2a) is converted by amplifier-limiter 1 into a square wave signal / i (Fig. 26), which in one of the half-periods allows the waiting generator 2 to generate pulses with a strictly defined phase relative to the input signal (Fig.26). At the output of the waiting generator 2, a pulse sequence is formed with the number of pulses proportional to the period of the input signal (Fig. 2c). As a result of counting the number of these pulses by the counter 4, at its output a code is formed that is proportional to the period of the input signal. This code arrives at the inputs of the selectors 5. A pulse (fig. 2d) is applied to the gate inputs of the selectors 5 and to the delay element 9 at the falling edge of the output signal of the amplifier-limiter 1 (fig.2b). At the output of one of the selectors 5 tuned to the required code, an impulse arises (FIG. 2e, e, g), setting the COOT- corresponding trigger 7 to one state (FIG. 2Z and, k), allowing the input of the meander signal ( Fig, 26) on the corresponding to this frequency output 11.1-11.N (Fig.2l, m, n). After a certain time interval required for the operation of the selector 5 and the trigger 7, the pulses of the input delay element 9 reset the counter 4 to its initial state (Fig. 2c). The triggers 7 are reset to the initial state by the leading edge of the square wave signal (Fig. 2 and k). A single trigger state 7, corresponding to the desired input signal period code, controls the operation of the corresponding AND-HE element 8, allowing the input meander signal, corresponding to the selected period, to pass to the device output. Thus, at each of the outputs of the digital frequency distributor, a meander input signal of only one selected frequency appears (Fig.2l, m, n).

Claims (1)

Invention Formula A digital frequency discriminator, containing N NAND elements, whose outputs are digital frequency discriminator outputs, serially connected limiter and inverter, the output of which is connected to the first inputs of all AND-N elements of the N trigger, the reset outputs of which are connected to the output of the amplifier - the limiter and the output of the i-ro trigger, where i «1, N, is connected to the second input of the 1st NAND element, N frequency selectors, the output of the 1st one of which is connected to the installation input of the 1st trigger, and series-connected generator clock pulses The meter and counter, the output of which is connected to the first inputs of all frequency selectors, the input of the amplifier-limiter is the input of a digital frequency discriminator, characterized in that, in order to improve the accuracy of frequency discrimination, sequentially connected pulse generator and a delay element, the output of which is connected with the reset input of the counter, and the clock pulse generator is made waiting and its input is connected to the output of the amplifier limiter and the input of the pulse generator, the output of which is connected to the second m inputs of all frequency selectors. se e cvs pe e e. 5 - Ј- s; five; "NJ ЈV