SU1437974A1 - Generator of pseudorandom sequences - Google Patents

Abstract

The invention relates to a pulse technique and can be used in test and information technology. The purpose of the invention is to expand the functionality of the generator and its scope. The pseudo-random signal generator contains a pulse counter 2, a multiplexer 3, a random access memory 4, a register 5, elements AND 6.1 ... 6.P, an adder 7 modulo two, a persistent memory 8, an element And 9, a bus 1 clock pulses and two groups of 10 and 11 tires. The use of the device ensures the separate control of the parameters of pseudo-random numbers in the clock cycles of the generator with preservation of the preceding states - 1 SHY. 1 il. &

Description

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The invention relates to a pulse technique and can be used in test and information technology.

The purpose of the invention is to expand the functionality of the pseudo-random signal generator due to the separate control of parameters

pseudo-random signals.

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The drawing shows a structural diagram of a pseudo-random signal generator.,

The pseudorandom signal generator contains a bus 1 clock pulses connected to the counting input of the counter 2 pulses, a multiplexer 3, the outputs of which are connected to the corresponding information inputs 4 of the random access memory (RAM) 4, the outputs of which are connected to the corresponding information inputs of the register 5, the outputs of which are connected with the first inputs of the corresponding elements And 6.1-bp of the group 6 elements I, the outputs of the elements 6,1-6 .p of which are connected to the inputs of the adder 7 modulo two, permanently remembering e device (ROM) 8, element 9, the first group 10 of buses, the second group 11 of buses, the corresponding buses of which are connected to the corresponding inputs of the first group of information inputs of multiplexer 3 and with the control input of multiplexer 3, (1 + 1) - The second input of the second group of information inputs of which is connected to the iM output (, 2... п-1; n-bit of register 5) of register 5. First, the input of the second group of information inputs 1 1 1 1 1 3 is connected to the output of the adder 7 modulo two. The corresponding terminals of the first busbar group 10 are connected to the first input of the element I 9, to the installation input, to the control input and to the corresponding information inputs of the counter 2 pulses, the outputs of which are connected to the corresponding address inputs of the ROM 8, the outputs of which are connected to the second inputs of the corresponding elements And 6.1-bp group 6 elements I. A bus 1 clock pulses is connected to the control input of RAM 4 and to the register synchronization input 5. The overflow output of the counter 2 pulses is connected to the second input / element And 9, the output to expensively connected to the synchronization input of the counter 2 pulses.

The device works as follows.

Let a logical zero signal be sent to the input of the counter 2 pulses, a binary combination is sent to its information inputs, which is rewritten into the counter of 2 pulses by a signal from the first input of element 9. At the control input (input A) of the multiplexer 3, the signal high logical level Consider the operation mode of the generator, provided that the operation of the pulse counter 2 is prohibited by a logical zero signal at its input (counting lock). Under the influence of the positive potential of the clock pulse entering the input of RAM 4, the latter operates in the information reading mode, and the n-bit binary word located at the address M is rewritten into a (parallel) register 5. The bits of the register 5 are masked with a binary code combination with the outputs of the ROM 8, determined the coefficients of the characteristic polynomial. The result of modulo-summing two signals of the selected bits of register 5 is formed at the output of adder 7 modulo-two, from where it arrives at the first input of the second group of information inputs of the multiplexer 3, and from its output - at the first information input of RAM 4. At the end of the positive potential of the clock pulse, a low logic level signal appears at the clock pulse 1, which transfers the RAM 4 to the recording mode of the signals from its information inputs to the same cell from which information was previously read. Thus, the signals from the first, second, etc. ... (n-1) of the outputs of register bits 5 are recorded in the second, third ..., n-th bits of the memory cell of RAM 4 with the address M, and the first digit of this cell records the result of the modulo summation two signals of register 5, masked in accordance with the coefficients of the polynomial, recorded in the bits of the memory cell (with address M) of the ROM 8. In the next cycle of the clock signal when blocking the counter 2 pulse operation, the RAM cell 4 with the address is interrogated

with the polynomial coefficients located at the ROM 8 address of the same name. Since the access to other cells of RAM 4 (except for the selected Cell) is not performed, the remaining cells retain their state, which serves as initial conditions for accessing them during device operation.

The initial setting of the initial conditions on the addresses of the RAM 4 is provided by feeding a logical zero signal to the control input of the multiplexer 3, as a result of which the generator feedback is disconnected and the signal is switched to the RAM 4 inputs; from the inputs of the first group of information 1P inputs of multiplexer 3 connected to the second group 11 buses of the device. Consequently, at zero potential on the bus 1 of clock pulses, data is recorded from the first group of information inputs of multiplexer 3 to the selected cell of RAM 4. Changing the address of the polled cells provides for recording the beginnings of numbers in the corresponding RAM cell 4.

Thus, blocking the operation of the counter 2 pulses ensures the functioning of the device in the mode similar to the mode of operation of the device prototype. The difference is that pseudo-random numbers form

M, recording its contents in register 5, followed by recording of the shifted signal into its higher (2-n) -th bits, and the result of modulo-two summation - for the first digit of the polled cell, etc. Consequently, when the device operates with a fixed content of the counter 2 pulses and with a non-zero content of the memory cell of RAM 4 with the address M, a pseudo-random signal is generated at the output of the device, the characteristics of which are determined by the contents of ROM 8 at the same address. To change the characteristics of the generated signal in accordance with a given program, it is sufficient to set the new value of the address of the polled RAM 4 cells and ROM 8, by writing 2 counts of the new number to the counter of the selected address. In this case, pseudo-random numbers arriving at the output of the device are formed in the RAM cell 4, for example, with the address K and have characteristics in accordance with

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separately in the cells by the addresses of RAM 4, which preserves the previous state when moving to new addresses and allows the generation of sequences whose initial conditions may be previously interrupted signals. In this mode, the binary code combination on the information inputs of the pulse counter 2 determines the address of the initial cell of RAM 4 and the selection of the characteristic of the generated signal.

If there are 2 pulses of a logical unit signal at the control input of the counter, under the influence of clock pulses, the counter of 2 pulses successively passes states, the number of which (before overflow) is determined by the value of the binary code combination at its information inputs. Consequently, in each clock cycle of the device, pseudo-random signals are generated at its outputs, the characteristics of which are determined by the current value of the contents of the counter 2 pulses, affecting the address inputs of RAM 4 and ROM 8, accessing the i-th memory cell of which is performed through M clock cycles than multidimensional pseudo-random sequences are generated, the numbers of which are determined by the current value of the contents of the counter 2 and 5 pulses. In this mode, the binary code combination M on the setup inputs of the pulse counter 2 determines the number of separately controlled signals.

Thus, in the device, the pseudo-random signal parameters are separately controlled in its working cycles with preservation of the previous states, which allows.

5 when passing to the generation of signals with new parameters, remember the final state of the interrupted sequence and, upon return, use it as the initial one, thereby preserving the structure of the generated signal. With a cyclical change of the pulse count counter 2, multidimensional pseudo-random signals are formed, the characteristics of which

5 is different in each cycle of the cycle, determined by the conversion factor of the counter 2 pulses. This mode of operation is effective in organizing a parallel anaggis of a large number

honest digital blocks, each of which is investigated under the influence of signals with given characteristics. For example, when addressing the receivers connected to the device outputs by the contents of the counter 2 pulses, signals are formed at the inputs of each of them, the structure of which is determined by the coefficients of the corresponding characteristic polynomial located at the selected address of the ROM 8.

Claims (1)

Invention Formula A pseudo-random signal generator containing a% pulse bus, connected to a sync-register input, whose outputs are connected to the first inputs of the corresponding elements AND of a group of elements AND, the outputs of elements AND of which are connected to the inputs of a modulo adder, characterized in that, in order to expand the functionality due to the separate control of the parameters of pseudo-random signals, the second group of buses is entered in the first, the corresponding tires of which are connected to the first group of info control inputs and control input of a multiplexer, the outputs of which are connected to the corresponding information inputs 5 0 0 five 746 memory device, the corresponding tires of the first group of buses are connected to the first input of the element I, to the installation input, to the control input and to the corresponding information inputs of the pulse counter, the outputs of the bits of which are connected to the corresponding address inputs of the permanent storage device, the corresponding outputs of which are connected to the second inputs of the corresponding elements AND of the group of elements AND, the clock pulse bus is connected to the control input of the random access memory a, with a counting input of a pulse counter, the overflow output of which is connected to the second input of the element I, whose output is connected to the synchronization input of the pulse counter whose discharge outputs are connected to the corresponding address inputs of the random access memory, the outputs of which are connected to the corresponding information inputs of the register, the i-th output of which is connected to (i +) - M input ... n-1; n is the size of the register) of the second group. formation inputs of the multiplexer, (the first input of the second group of information inputs of which is connected to the output of the modulo two.