SU1429129A1 - Device for analysis of electrocardiograms - Google Patents

Abstract

The invention relates to computing and can be used to study the functions of the cardiovascular system. The aim of the invention is to increase interference, stability due to the suppression of network interference at. change the frequency of the mains. The device contains an amplifier 1, a multichannel analog-to-digital converter 2, a computing unit 3, a recorder 4, a switch 5, a generator 6 pulses of the reference frequency, a divider 7 frequency, a phase detector 8, a driver 9 W of reference signals. 3 or „

Description

The invention relates to computing and can be used | To investigate the functions of the cardiovascular system, the purpose of the invention is to increase noise immunity by suppressing the power supply network when changing the frequency of the supply network,

, FIG. 1 is a block diagram of the device; in fig. 2 is a block diagram of the operation algorithm of the device j in FIG. 3 is a block diagram of the operation of a digital filter ,, I The device contains an amplifier 1, | a multichannel analog-to-digital converter (ADC) 2, a computation unit 3h recorder 4, a switch 5, a generator 6 pulses of the reference frequency, a frequency divider 7, phase the detector 8, the driver 9 of the reference signals, the input 10 of the device steps 11-42 algorithm.

For example, the Irisha computer can be used as a computing unit. The code of the A / D converter 2 enters, operative. Memory through the first port of the parallel interface. The second port is used to switch the groups of leads of amplifier 1, switch channels of AID 2, control switchboard 5, and amplify pulses of program start of AID 2. The output of the processed ECG curves from the memory memory is output through the third port of the parallel interface. tee on the register.

The device operates in accordance with the algorithm (FIG. 2), the steps of which are indicated as follows: 11 - Start 5 12 - Interface initialization; 13 - Turn on the ADC on the first channel; 14 - Switching the switch to run the ADC; 15 - Olsidani state of pre-conversion; 16 - Matching conversion results; 17 - Record counting in delay 38; 18 - Rounding up to 8 bits; 19 - Record counting in delay. 35; 20 - The delay is delayed by a delay of 35 samples from the input rounded value; 21 - Summation with the content of the delay 38;

22- Record result in delay 38

23- Round to 8 bits; 24 - Record B delay 40; 25 - Subtraction of a delayed 40 countdown

from the rounded result of the calculations on the first link; 26 - Summation with delay content 42; 27 - Record in delay 42; 28 - Rounding up to 10 bits; 29 - Subtraction from the input sample, delayed 41; 30 - Bsod result; 31 - Check: whether the third channel was tested; 32 - Switching A1.Sh to the next channel; 33 - Switching the switch to software start; 34 - Program launch Aim.

In addition, a delay of 35 for 512 counts, a delay of 36 for 504 counts are indicated. A, adder-subtractor 37, a delay of 38 for 8 counts, a subtractor 39, a delay of 40 for 512 counts, an adder-subtractor 41, a delay of 42 for 8 counts (Fig 3).

The device works as follows.

After switching on the device, block 3- programming the parallel interface to implement communications, switches the A / D converter 2 to the first channel, switches the switch to start the conversion, and goes into the waiting state.

The generator 6 produces pulses with a frequency 8 times the network frequency, which, after dividing by eight, is fed to the input of the phase detector 8c. The other input of the latter receives the reference signal of the frequency frequency from the imager 9. Phase detector 8 produces an error signal proportional to the phase difference of the pulse sequence and reference signal. This error signal adjusts the oscillator frequency 6 so that the phase difference of the signals at both inputs of the phase / s detector 8 is zero. This ensures the stability of the position of the pulses that trigger the ADC within the period of the network frequency.

A start pulse through switch 5 is fed to AC 11 2, including an analog-digital conversion. Upon its completion, a chipping request signal is generated, under the influence of which the computing unit starts processing the current sample. The processing of the countdown consists in performing the operations of the algorithm (Fig. 3).

Block 3 reads the ECG count. The read count is written to delay buffer 36 by 504 counts. After that, calculations are made for

the first link of the filter, the count is rounded up to 8 bits and written to the delay buffer 35 by 512 samples. After that, the count delayed by 35 by 512 samples is subtracted from the input count, added to the delay buffer 38 by 8 samples, and the result no rounding is again recorded into the delay buffer 38. The routed up to 8 bits result of the calculations in the first stage is used as an input reference for the calculations when implementing the second filter layer.

The calculations performed in the second stage are similar with the only difference that the actions are performed on the contents of the delay 40 by 512 samples and the delay 42 by 8 samples. The result of the calculations in the second stage is rounded up to 10 bits and subtracted from the sample, delayed by 504 for the sampling period by delay 36, and the result is transmitted to the recorder.

After that, unit 3 turns on the ADC 2 to the next channel, switch to the position that ensures the program launch of the ADC and its actual launch. When processing data on the second channel, the same actions are performed.

After processing the count on the third channel, all actions are repeated, starting with square 13 of the algorithm. Delays 35, 36, 38, 40 and 42 are implemented in the random access memory of block 3 by shifting the count addresses each time the buffer is accessed.

Claims (1)

Invention Formula I 0 five An electrocardiogram analysis device containing a multichannel analog-to-digital converter, the input resolution of which is connected and the output of which is connected to the read output and information input of the computing unit, respectively, the data output of the computing unit is the output of the device whose information inputs are connected to the information inputs of the multichannel analog-digital converter , characterized in that, in order to improve noise immunity due to the suppression of network interference during the change frequency mains, a reference driver, a phase detector, a reference frequency generator, a frequency divider and a switch, the output of which is connected to the control input of a multichannel analog-to-digital converter, which stubs and information and control inputs of the switch connected to the output of the reference frequency pulse generator and 0 by the command outputs of the computing unit, respectively, the output of the pulse generator of the reference frequency is connected to the input of a frequency divider, the output of which is connected to the first input of the phase detector, the second input of which is connected to the output of the reference signal former, and the output of the phase detector of the pulse eto0 freon frequency. Piiz.3