SU1409288A1 - Cardiostimulator - Google Patents

Abstract

This invention relates to medical technology and can be used as a cardiac pacemaker. The purpose of the invention is to increase the safety of stimulation with a change in frequency. The device contains a frequency adjuster 1, a clock frequency generator 2, a frequency divider 3, an agreement block 4, a comparator 5, a decoder 6, an arithmetic unit 7, a register 8, a frequency increment adjuster 9. The design of the pacemaker allows a gradual change in the frequency of the stimulating pulses of the programmable pacemaker, regardless of the frequency setting rate. 1 il.

Description

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This invention relates to medicine, in particular to cardiac pacemakers.

The purpose of the invention is to increase the safety of stimulation with a change in frequency.

The drawing shows a structural diagram of the cardiac stimulator.

The pacemaker contains 1 frequency setters, 2 clock frequency generator, 3 frequency divider, matching unit 4, comparator 5, decoder 6, arithmetic unit 7, register 8 and frequency incrementing unit 9.

The pacemaker works as follows.

The frequency divider 3 produces a division of the pulses of the clock frequency generator 2 by the required value in accordance with the code set at its second input and output of the register 8 and the specified frequency adjuster 1 irritation (stimulation).

When measuring the frequency of the output pulses, the comparator 5 compares the code previously recorded in the register 8 and the code newly set by the frequency adjuster 1. The signal from the output of the comparator 5 is fed to the input of the decoder 6, which converts it into tuning variables that arrive at the first input of the arithmetic unit 7 and determine the functions it performs. So, if the frequency value newly set by frequency adjuster 1 is greater than the frequency value previously recorded in register 8, arithmetic unit 7 performs arithmetic addition of register 8 contents with a code defining the value of y frequency ra specified by frequency increment setting 9. From the cutoff of the signal from the output of the splitter 3 of the pulse frequency, the result of the arithmetic addition is recorded in the register 8 and then again fed to the first input of the comparator 5 and the second input of the splitter 3 frequency.

The described process continues until the equality of the frequency set by the unit 1 and recorded in the register of 8 codes is achieved. In case of equality of codes, the decoder 6 generates signals of tuning variables at which the arithmetic

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Block 7 does not take any action with the contents of register 8, arriving at its third entrance. In order to obtain the stabilization of the 1st value of the frequency of the stimulating pulses, the frequency increment value, set by the frequency increment generator 9, must be a multiple of the step (value) of the frequency change, which is set by the frequency adjuster 1.

A similar process occurs when the frequency value set by the frequency adjuster 1 is less than the frequency value that was recorded in register 8. In this case, the arithmetic unit 7 performs an arithmetic reading of the contents of the register 8 and the increment value specified by the frequency increment adjuster 9 until equality is reached setting codes 1 frequency and register 8.

Thus, the introduction of a comparator, a decoder, an arithmetic logic unit, a register, and an increment block into the cardiac stimulator allows smoothly changing the frequencies of the stimulating pulses of the programmable pacemaker regardless of the speed of the frequency setting unit 1 frequency, which increases the safety of stimulation when the frequency of the output pulses cardiac pacemaker.

In addition, a gradual change in the frequency of stimulating pulses is more easily tolerated by the patient during electrophysiological i-rays. contrast studies of the heart, when the doctor can accidentally change the frequency of stimulation.

Claims (1)

Invention Formula A pacemaker comprising a serially connected clock generator, a frequency divider and a matching unit, serially connected frequency adjuster, comparator, and decoder, characterized in that, in order to increase the safety of stimulation when the frequency changes, it contains a series connected frequency increment generator, an arithmetic unit and the register, the output of which is connected to the second inputs of the arithmetic unit, the frequency divider and comparator, the second input - to the output of the frequency divider, and the output is decrypted ra is connected to the third input of the arithmetic unit.