SU1456928A1 - Device for threshold control of time period - Google Patents

Abstract

The invention relates to measurement techniques and automation and can be used for threshold control of a mixture of deterministic and random values, presented as time-varying period or duration of the input periodic signal, as well as in automatic control systems, in the knees as variable time period or the duration of the signal. The device for the threshold period control includes a pulse former 1, a reference generator 2, a pulse counter 3, decoders 4 and 5, switches 6 and 7, triggers 8.9, 12.13, And 10 and II elements, delay element 14, control unit 15 , block 16 analysis. The description of the invention also provides structural electrical diagrams of the control unit 15 and the analysis unit G6. Elimination of false alarms of the device in the presence of fluctuations in the duration (period) of the input monitored signal and during short-term changes of this duration (period) by an amount greater than the difference between the upper and lower values of the threshold levels, improves the noise immunity of the device. 2 hp f-ly, 2 § (L

Description

The invention relates to measurement technology and automation and can be used for threshold control of a mixture of deterministic and random values, presented as a time-varying period or duration of an input periodic signal, as well as in automatic control systems, in which the adjustable parameter is represented as variable in time period or signal duration.

The purpose of the invention is to increase the noise immunity of the device by eliminating the possibility of tripping when interference pulses arrive on the input bus.

FIG. Figure 1 shows the electrical structure of the device; 2 shows timing diagrams for his work.

The device (figure 1) contains the driver 1 pulses, the input of which is connected to the input bus. The output of the reference generator 2 is connected with the counting input of the counter 3 pulses, the outputs of which are bitwise connected to the inputs of the first and second decoder 4 and 5. From the first to the k-th outputs of the decoder 4 are connected respectively to the first through the k-th closing contacts of the first switch 6. From the first to the M-th outputs of the decoder 5 are connected respectively to the first to the M-th closing contacts of the switch 7. The switching contacts of the switches 6 and 7 are connected to the S-inputs of the first and second triggers 8 and 9 respectively. Outputs of the first and volts And 10 and 11 are connected to the R-inputs of the third and fourth triggers 12 and 13j, respectively, and the output of the trigger 12 is connected to the information input of the delay element 14, the clock input of which is connected to the first output of the control unit I5 and the R-inputs of the trigger 8 and 9 The output of the trigger 13 is connected to the first input of the analysis unit 16, the output of which is connected to the output bus, and the second input is connected to the output of the delay element 14. The code of the driver 1 is connected to the installation input of the counter 3 and the input of the unit 15, the second you-:. the course of which is connected to the first inputs of the elements And 10 and 11, the second inputs of which are connected to the inverse outputs respectively of the flip-flops 8

and 9, the direct outputs of which are connected to the S-inputs of the flip-flops 12 and 13, respectively.

Block 16 analysis contains the first to third elements And 17-19, the outputs of which are connected respectively from the first to third inputs of the element OR 20, the output of which is connected to

the output of block 16. The first inputs of the elements And 17 and I9 are connected to the first input of the block 16, the first input of the element And 1 8 and the second input of the element And 19 to the second input of the block. 16, and the second

the inputs of the elements And 17 and 18 - S. the output of the element OR 20.

The delay element 14 is made in the form of a shift register, the information and clock inputs of which are connected

respectively with information and

the clock inputs of the element 14, and the output of the N-ro bit of the shift register - with the output of the delay element.

Depending on the nature of the signal supplied to the device's input (continuous harmonic oscillation, the period of which is to be monitored, or, for example, a periodic pulse sequence for which the duration of the pulses is controlled), as a driver 1, a limiter amplifier can be used respectively (to obtain

rectangular pulses, the duration of which is proportional to the monitored period), or an ordinary transistor switch (to form clear edges at the input signal and match, if necessary, its parameters with the element base used when implementing the device).

As a reference generator 2

a square pulse generator can be used, the frequency of which is stabilized by a quartz resonator.

The counter 3 pulses can be performed on chips, for example, K 155IE2.

Decoders 5 and 4 can be implemented on the matching elements, by which the required

threshold levels. At the same time, the inputs of the coincidence elements are connected to the corresponding outputs of the counter of 3 pulses, and the outputs corresponding to the specified threshold levels are connected via

31

Switches 6 and 7 are assigned to the S-input according to triggers 8 and 9.

Triggers B and 9 are designed to generate signals of instantaneous upper (trigger 8) and lower (trigger 9) threshold levels and element control AND 10 and 11, through which, in the case of failure of triggers 8 and 9 after the measurement of the duration of the next input signal , issue setup commands to the initial state of the triggers 12 and 13.

Triggers 12 and 13 form signals that exceed the upper (trigger 12) and lower (trigger 13) values of the threshold levels (Fig. 2n, m).

The delay element 14 is designed to delay the time of the output signal of the trigger 12 of the upper threshold level value and can be implemented as a shift register with N outputs on the chips, for example, K155TM2 or K155IR.

The control unit 15 consists of two single vibrators, the inputs of which are combined and connected to the output of the former 1. The output of the first single vibrator

0

T (t), reflecting the law by which the duration (period) varies; input monitored signals. The dashed straight lines in this diagram show the upper (Tthp. &Amp;) and lower (Trp.) Values of a given threshold level.

In Fig. 2a, a pulse sequence is supplied to the input bus of the device for a threshold sequence. control of the period, the pulse duration of which changes relatively slowly and at the same time fluctuates according to a random law T (t). In this case, under the influence of single short-term impulse noise, for example, single abnormal changes in the duration of the input signals (outliers or dips) can occur.

FIG. 26 shows the same sequence after the formation of the fronts by shaper 1.

FIG. 2c conventionally depicts high-frequency pulses of the reference oscillator 2, counted by the counter 3 in those time intervals for which it is opened under the influence of

five

the torus is the first output, and the output of the AOR is the signal of the driver 1.

the second one-shot - the second output of the control unit 15. In this case, the first one-shot starts on the leading edge (in our example, a negative differential from 1 to O), and the second - on the falling edge (in our example, a positive difference from O to G) of the pulse signal received at the output of the imaging device 1.

The analysis block 16 is organized in such a way that, if there is a Log.o level at both inputs of the block or the Log level. 1 only at one of the inputs at its output there is a level of Log.O. Level Log.G appears at the output of block 16 analysis only when the levels Log. arrive simultaneously at both of its inputs. After the occurrence of the level Log.1 at the output of the analysis unit 16, the level

The log.O on its output is restored while the log level is received. On both of its inputs.

35

Until those. then, for a long time, the input signals supplied by the control to the input of the device exceed the lower (T „op c) and ver (Tf, op g) threshold values

the excess signal at the output of the I analysis, simultaneously being

bus output of the device, is not covered (fig.2g).

40 The input signals may exceed one time (Emission of the lower and upper values of the specified threshold, wh and leads to the appearance of

45 encoders 4 and 5 of the signals with the maximum overshoot of the lower (Fig. 2d) thresholds (Fig. 2d), subsequently affecting the triggers (Fig. 2d), 13 (Fig. 2m) and the trigger

50 (Fig. 2i), 12 (Fig. 2n), as is not sewn by the analyzing unit 16, since in this case, Uro Log.1 (Fig. 2m, o) due to a set of two measures with element 14 output

50 (Fig. 2i), 12 (Fig. 2n), as exceeded by the analysis block 16 is not perceived, since in this case the level Log.1 (Fig. 2m, o) due to a two-cycle delay by element 14 of the output

The device for the threshold control 55 of the trigger signal 12 simultaneously on

l period works in the following way.

The upper diagram of figure 2 is conditionally depicted curve

both of his inputs do not arrive.

The triggers 9 and 8 are then returned to the initial state by a pulse (Fig. 2e) generated at the first output.

Until those. then, while the duration of the input signals supplied to monitor the input of the device does not exceed the lower (T ор or ц) and upper (Tf, op g) values of the threshold level.

the excess signal at the output of the analysis block I6 I, which is simultaneously

bus output of the device does not appear (Figure 2d). - At the same time,

The input signal can sometimes exceed one time (Outlier) immediately the lower and upper values of the predetermined threshold, which. Although it results in the output of the decoders 4 and 5 of the signals of instantaneous excess of the lower (Fig. 2d) and upper (Fig. 2d) thresholds that sequentially act on the flip-flops 9 (Fig. 2d), 13 (Fig. 2m) and triggers B

(Fig. 2i), 12 (Fig. 2n), as exceeded by the analysis block 16 is not perceived, since in this case the level Log.1 (Fig. 2m, o) due to the delay of two cycles by the output element 14

trigger signal 12 simultaneously on

both of his inputs do not arrive.

The triggers 9 and 8 are then returned to the initial state by a pulse (Fig. 2e) generated at the first output.

de control unit 15 before the beginning of each new measurement of the duration of the input monitored signal, and triggers 13, 12 - at commands that start from the second output of control unit 15 at the end of each measurement (fig.2g) through open elements 11 (fig.2k) and 10 (FIG. 2L), and in that case, during the whole measurement, the trigger 9 and 8, respectively, did not operate.

In that case, when the duration of the input signals is gradually increased so that, once exceeding the value of T o. it no longer becomes less than the value, there comes a point in time when the level of Log.1 from the output of the trigger 13 excesses (Fig. 2m) and the output of the 14-delay element (Fig. 2c) begins to flow to both inputs of the block. 16 analysis at the same time / At the output of the analysis block 16 also appears the level of Log.1 (fig.2t), corresponding to the appearance of information on the output of the device at the output of the device.

In the future, under the influence of single impulse noise, the same decrease in the duration of the input periodic signal to a value smaller than 1po.n can occur. However, the Log level. G at the output of block 16 of analysis, .a means information about the excess on the output bus of the device, does not disappear, since the Log level is still present at one of its outputs. (Fig.2m, o).

Further, when the duration of the input signals begins to decrease gradually and becomes shorter, first, the values of T. ,,, and then the values. , there comes a time when two inputs of the analysis unit are simultaneously: - two are simultaneously consumed. Level Log. G (Fig.2m5d). At its output, Log.O (Fig. 2t) immediately appears, informing of the end of the elevation.

If each short-term outlier, or failure of a controllable value, represented as a time-varying period or duration of input signals, contains not one but another two (or more) signals that are abnormal in duration, for a full selection of the same &; single impulse noise is sufficient569286

but the delayed signal from the output of the element 4 delays should not be removed after two, but after three (and more) t-shots.

For normal operation of the device, in addition, it is necessary that the time interval between outliers and dips governs the JTj value of delay element 14, proportional to the number of cycles through which the delayed signal is taken.

Thus, the advantage of the proposed device for threshold

The 15 control of the period in comparison with the known one consists in its higher noise immunity, which is achieved by introducing into the device the fourth trigger, the second element I, the delay element and the analysis unit. At the same time, false alarms of the device are excluded not only in the presence of fluctuations of the duration (period) of the input controlled

25 signals, but also for short-term changes (outliers or dips) of this duration (period) by an amount exceeding the difference between the upper and lower threshold values

30 levels.

The use of the proposed device in information-measuring systems for threshold and tolerance. Monitoring of a periodic signal

25 and in automatic control systems, will increase the reliability of control and noise immunity.

systems. I

Claims (3)

40 claims 1. A device for threshold period monitoring, containing a pulse shaper, the input of which is connected to the input bus, and the output is connected to the input of the control unit and the installation input of the pulse counter, the counting input of which is connected to the output of the reference generator, and the output is equal to the bottom with the inputs of the first and second decoders, and the first to the k-th outputs of the first decoder are connected respectively from the first to the k-th closing contacts of the first cross-section of the H5, the switching contact of which is connected to the S-input of the first trigger, and from the first to the M-th output of the second desh1-1fratora are connected respectively from the first to the M-th closing contacts of the second switch of the second element I, the first input of which, the switching contact of which is connected to the second output of the unit is connected to the S-input of the second trigger, and the second inputs of the first and pa, and the direct output of the first flip-second element I is connected to the sdner connected to the S input of the third trigger, the R input to the R input of the second elevation trigger and to the first output of the control unit, the second output of which is connected to the first input g of the first element And, the output of which is connected to the R-input of the third trigger outputs, respectively, of the first and second triggers, 2. The device according to claim 1, that is, that the analysis unit 10 contains the first to third elements AND, the outputs of which are connected from the first to the third by the inputs of the element OR, pa, as well as the output bus, of which the output and output are connected to the output more or less by the fact that, for the purpose of the analysis unit, the first input of improving the noise immunity of the device And 15 is connected to the first by eliminating the possibility of the input of the third element Both with the first actuation when the analysis unit arrives at the input, the second input is connected to the second input because it is connected to the second input. r introduced the second element And, the fourth and third element And with the first input trigger, the delay element and the block of the second element And, the second input of which, the output of which is connected to the output-horn-o is connected to the second input by the first bus, and The first and second inputs of which, respectively, with the output of the fourth trigger of the transform and with the output of the delay element, the clock support 25 are made in the form of a shift register, whose input is connected to the first output, the information and clock inputs of the control unit, and connected accordingly with tween ny input - with the output of the third-trig information and clock inputs ger element. Moreover, the S-input of the fourth delay trigger, and the output of the N-ro bit, gera is connected to the direct output of the second shift register and connected to the output of the trigger, and the R input is from the delay delay slot. element And the output element OR, 3. The device according to claim, 1, characterized in that the element of the VYUros Versions of the first and second triggers, respectively 2. The device according to claim 1, that is, so that the analysis block contains the first to the third elements AND, the outputs of which are connected from the first to the third by the inputs of the element OR, the output of which is connected to the output of the analysis unit, the first input of the element I is connected to the first input of the third element I and to the first input of the analysis unit, the second input of which is connected to the second input. g of the third element And with the first input of the second element And, the second input of which is connected to the second input of the primary holder is made in the form of a shift register, the information and clock inputs of which are connected respectively to the information and clock inputs of the delay element and the output of the N-ro bit of the shift register is connected to the output of the delay element. AND element and the output of the element OR, 3. The device according to claim 1, characterized in that the element is