SU1444959A1 - Position code to large-base code converter - Google Patents

Abstract

The invention relates to the field of computer technology and automation and is intended to translate number codes from a number system with any base into number codes with any major basis in digital control systems and information processing devices. The aim of the invention is to increase the conversion rate. The goal is achieved by introducing a group of triangular matrices, a group of multiplication blocks and a multi-input adder into the position code converter containing a triangular matrix, each element of the triangular matrices containing a multiplier and adder. 2 Il.

Description

4 4 4 CO JV CO

The invention relates to computer engineering and automation and can be used in information processing devices that operate S different number systems to translate the positional code from a number system with any base into number codes with any large base. The purpose of the invention is to increase the conversion rate.

Figure 1 shows the block diagram of the code converter; Fig. 2 is a schematic of a transformation cell.

The code converter (Fig. 1) consists of cells of the same type 1, contains (p-1) multiplication unit 2, a multiple-input adder 3. The cells of the same type 1 together form n triangular matrices 4, with outputs of the highest bits -i Dov 5 and VECODs low-order bits 6. Information inputs 7 of the transducer arrive at the inputs of the last columns of the triangular matrices 4. The outputs of the triangular matrices 8 arrive at the inputs of multiplication units 2 and the inputs of the multi-input adder 3, whose outputs are output 9 of the converter.

The input 10 of the base of the input code of the converter and the input 11 of the selection of the base of the output code arrive on all the cells of the triangular matrices. The weight inputs 12 of the converter are fed to the inputs of multiplication units 2.

Each cell 1 contains (Fig. 2) a multiplier 13 and an adder 14. Multiply enters input 15, and a term at input 16, a multiplier (input code base) enters input 17. Input 18 receives an output code base, which ensures the choice of the system reckoning, blocks 13 and 14.

The basis of the operation of the code converter, when transferring the number A from a number system with a smaller base P to a numbering with a larger base q, is the algorithm for parallelizing the initial number A (p) on n parallel branches. In this case, each of the branches is processed independently of each other by the algorithm of sequential multiplication of the highest digit of the part of the number A (p) on the basis of the original number system p, followed by adding to the resulting product the next order of the digit of the part of the number A (p). Production operations

g 0

five

0 5 0

with

0

d "

five

in the q-ary number system and the process of multiplication and addition is repeated until the lower digit of the part of the number A (p) is added.

Converter codes works as follows.

The information inputs 7 of the converter are fed into the number A being converted in the number system with the base P, the initial number being divided into n parts, each of which contains (l (, - 1) -ls-bits (S O, 1, 2, ... (p-1); Ig ls (m + 1) / n, the sign DhC - the nearest lower integer m - the maximum width of the input code n - an integer,. The highest bit of the code is -1, each group arrives at triangular matrices through the inputs 15 of the converter cell 1 of the first row to the inputs 1 of the multiplier 13, at the output of which a number multiplied by the constant P of the original appears numbering system. On adder 14 of cell 1 of the first row, the result of multiplication and the digit of the previous bit, -2 of the transformed part of the number arriving at the inputs 16 of the transformation cell 1, are minimized. 15 of the first cell of the second row and the most significant bit of this result, obtained at the outputs of the 5 cell, is fed to the inputs 15 of the second cell of the second row, and so on. as a result of a parallel translation of each of the n parts at the outputs of 8 of each matrix, we obtain n parts of the original number A in the numeration q. The translation results obtained at the outputs 8 of each matrix, except for the first one, go in parallel to the inputs 15 of the corresponding multiplication blocks 2, the second inputs of which are supplied respectively to the constants P S in the numeration q. The result from the outputs B of the first matrix and the products obtained at the outputs of each of the blocks of multiplication 2, go respectively to the n group of inputs of the multi-input adder 3. As a result of the summation at the outputs 9, the code of the transformed number A in the numeral system with base q is obtained. The multiplication operations on multiplication units 2 and summing over multiple inputs.

adder 3 is produced in a q-ary number system.

Thus, in one cycle of operation on, the outputs 9 of the code converter appear the code of the converted number in the number system with base q.

On this basis, the maximum delay of the translation process is

A (P)

(one

- 2)

 Max

H +

ty is the delay of the signal by a block that is not sufficient {t is the delay of the signal by a multi-input adder,

and the time for converting the number A from the number p to the number q in the known code converter is equal to

T (pj (m - O t.

ten

Example. Translate number A (120011202112) from ternary to decimal. With

A (1200 l l 202112) 5 (298715)

Claims (1)

The invention formula holds a multiplier and an adder, and 55 output of the highest bit of the first cell The position code converter i-ro of the matrix column (i 1 .... m-2i 9 is a code with a large base, performed - the input code width), the unit in the form of a triangular matrix is identical to the input of the multiplicand first - typical cells, each of the so-called (i + 1) -ro columns, the output of the highest 81 about 6561.0. X 6561 295245 X 81 - 3402 - 298715 ten 51444959 bit j-th cell (j 2 .., m-1) j-ro column of the matrix is connected to the input of the term (j-1) -th cell (i + 1) -th column of the matrix, the output of the lower bit j cells of the i-ro column are connected to the input of the multiplicative (3 + 1) -th cell of the i-ro column of the matrix, the input of the multiplicand of the first cell of the first column of the matrix and the inputs of the term of all the cells of the first column of the matrix are connected to the corresponding information inputs of the converter which is connected to the inputs of the selection of the base of the output code of all the cells of the matrix, the inputs of which are connected enes input code to an input of a base, yield significant bit of the first cell of the last row of the matrix and outputs low bits of all the cells of the last row of the matrix are output matrix otlichayuschiy15 from ds + i Ig of the same type of cells, where Ig 8 (m + 1) / p, 8 0, g. - (n-1), n is the number of triangular matrices, (p-1) multiplication blocks and a multi-input adder, whose information outputs are information outputs of the converter, the input selection of which output code base is connected to the input selectors of the output code of all multiplication blocks all cells of all entered triangular matrices and a multi-input adder, the first group of inputs of which is connected respectively to the outputs of the first triangular matrix, the rest (n-1) - a group of inputs of a multi-input adder respectively connected with The outputs of the multiplication units 20, whose multiplicative inputs are connected respectively to the outputs of the corresponding triangular matrices, the multiplicator inputs of the multiplication units of all multiplication units are connected with the fact that, in order to increase the conversion rate, additional 25 -1) - triangular form. each matrix consists of FI I fiffiA QsQlSi Ol Phie. i 0 4959 15 from ds + i Ig of the same type of cells, where Ig 8 (m + 1) / p, 8 0, g. - (n-1), n is the number of triangular matrices, (p-1) multiplication blocks and a multi-input adder, whose information outputs are information outputs of the converter, the input selection of which output code base is connected to the input selectors of the output code of all multiplication blocks all cells of all entered triangular matrices and a multi-input adder, the first group of inputs of which is connected respectively to the outputs of the first triangular matrix, the rest (n-1) - a group of inputs of a multi-input adder respectively connected with Rupp multiplying outputs of the units 20, multiplicand inputs of which are connected respectively to the outputs of the respective triangular matrices, blocks multipliers multiplying the inputs of all the blocks are connected to the multiplying so25 responsible Vedova vhbdami pre-forming. 9 g-1 t 5, /five. 1 GZ  f L / one , g5 2