SU1329369A1 - Multichannel digital device for acoustic-emission check - Google Patents

Abstract

The invention relates to the non-destructive testing of acoustic emission methods and can be used to control developing defects and determine their coordinates in the material of construction. The aim of the invention is to increase the reliability of monitoring by expanding the dynamic range of recording acoustic transmission (AE) in amplitude and activity, as well as more accurately determining the location of the source of AE. The device allows for write-independent reading of data from storage unit 10; to realize the principle of registering the time of samples that save the memory volume of the storage unit 10, which makes it possible to register AE signals with greater activity and in a larger dynamic range; improve the registration of the front of an AE pulse, which makes it possible to more accurately determine the location of AE sources. 3 il. S (l

Description

The invention relates to non-destructive acoustic emission monitoring method and can be used to control developing defects and determine their coordinates in the material of construction.

The aim of the invention is to increase the reliability of monitoring by expanding the dynamic range of acoustic emission (AE) detection in amplitude and activity, as well as by more accurately determining the location of the AE source.

Figure 1 shows the structural scheme of a multichannel digital device for acoustic-emission control; figure 2 is a fragment of the signal AE; figure 3 - timing charts of the first decoder.

A multichannel digital device contains an electronic computer (computer) 1, a counter 2 times, a generator of 3 pulses and at least two channels 4 receptions, each of which contains a converter 5 connected in series, an amplifier 6 and an analog-to-digital converter (ADC) 7, register 8 delay, the first comparison circuit 9, the first memory block (ST) 10, information input 11 of which is connected to the output of the ADC 7, to the input of the delay register 8 and to the input Y of the comparison circuit 9, the maximum value register 12, circuit 13 comparison. In One of the register 2 maximum values, the input Y of the second comparison circuit 13 and the input X of the first comparison circuit 9 are connected to the output of the delay register 8 and the input X of the second comparison circuit 13 is connected to the output of the maximum value register 12. The device also holds a block 14 of code modification, the output of which is connected to the input 15 of the register of the maximum register 12 maximum values, the register 16 for storing the address, the first counter 17 of the address, the information input of which is connected to the output of the register 16 for storing the address, the output of the first counter

The 17 addresses are connected to the input of the address storage register 16, the output of the first ST 10 is connected to the information input

18 COMPUTER I. In addition, the device contains a distributor of 19 pulses, the input of which is connected to the output of the generator of 3 pulses, and the output 20 distributes n 19 pulses connected to

the counter input of time counter 2, the first multiplexer 21, the second and third counters 22, 23 of the address, the third comparison circuit 24, the first OR circuit 25, the second ST 26, the first synchronization circuit 27, the output of the second address counter 22 connected to the input 28 of the first multiplexer 21 and the input X of the third comparison circuit 24, the output of the third address counter 23 is connected to the input 29 of the first multiplexer 21 and the input Y of the third comparison circuit 24, the output of the first OR circuit 25 is connected to the recording input of the BZ 26 and the counting input of the second counter 22 of the address the output of the first multiplex Ekora 21 is connected to the address input of the second ST 26, the output of which is connected to the information input 30 of the computer I, the output 31 of the read request of the computer 1 is connected to the input 32 of the first timing circuit 27, the outputs 33, 34 of the distributor 19 pulses are connected respectively to the inputs 35, 36 the first synchronization circuit 27, the output 37 of the first synchronization circuit 27 is connected to the read enable input of the second ST 26, the output 38 of the synchronization circuit 27 is connected to the control input of the first multiplexer 21 and the counting input of the third counter 23 of the address, the output of the comparison circuit 24 en with the entrance to the request for servicing the computer 1. In each channel 4 of the reception, counters 39 of extreme values are entered, the first and second decoders 40, 41, the address counter 42, the second multiplexer 43, the second synchronization circuit 44, the register 45 of time stamps. The outputs of the first and second circuits 9, 13 of the comparison are connected respectively to the inputs 46, 47 of the decoder 40, the output 48 of the first decoder 40 is connected to the information input of the second ST 26, to the input of the circuit OR 25 and to the control input of the register 45 time stamps, output 49 of the first decoder 40 is connected to the input of the record of the first counter 17 of the address, the output 50 of the first decoder 40 is connected to the counting input of the counter 39 of extreme values, the output 51 of the first decoder 40 is connected to the input 52 of the synchronization and the maximum value register 12, to the input of the block 14 modifiers and codes and with the installation input of the extreme values counter 39, the output of which is connected to the input of the second decoder 41, the output 53 of the second decoder 41 is connected to the synchronization input of the address storage register 16 and the information input of the first BZ 10, the output 54 of the second decoder 41 is connected to input 55 the first decoder 40, the output 56 of the request to read the computer 1 is connected to the input 57 of the second synchronization circuit 44, the output 20 of the distributor 19 pulses are connected to the recording resolution input of the first BZ 10 and the counting input of the first counter 17, the output 3 3 of the distributor 19 pulses are connected to the input 58 of the second synchronization circuit 44 and with the synchronization input of the delay register 8, the output 34 of the distributor 19 pulses are connected to the input 59 of the second synchronization circuit 44 and to the second input 60 of the A / D converter 6, the output 61 A1Sh 7 is connected to the input synchronization of the time stamp register 45, the output of which is connected to the information input of the second ST 26, the control input of the first ST 10 is connected to the output 62 of the second synchronization circuit 44, the output 63 of the second synchronization circuit 44 is connected to the control input of the second multiplexer 43 and c Evenly the input of the address counter 42, the output of which is connected to the input 64 of the second multiplexer 43, the output 65 of the address counter 17 is connected to the input 65 of the second multiplexer 43, the output of the second multiplexer 43 is connected to the address of the register 45 time is connected to the output of the counter 2 time.

The first decoder 40 contains the first, second and third schemes And 66, 67,

68, the second circuit OR 69 and the first inverter 70. The first input 46 of the second circuit AND 67 is connected to the first input of the second circuit LLI 69, as well as to the input of the first inverter 70 and to the output of the first circuit 9 comparison. Second entrance

47 of the second circuit AND 67 is connected to the output of the second circuit 13 of the comparison. The first input of the first circuit AND 66 is connected to the first input of the third circuit AND 68 and the first input 55 of the second circuit OR

69, also with an output 54 of the second decoder 41. The output 48 of the first circuit AND 66 is connected to the control input of the register 45 of time stamps. The output of the first inverter 70 is connected to the second

the input of the third Lg I 68 circuit. The output 51 of the second And 67 circuit is connected to the second input of the first And 66 circuit and to the synchronization input 55 of the register 12 of maximum values. The output 50 of the second circuit {ШИ 69 is connected to the counting input of the counter 39 extreme values.

The first synchronization circuit 27 comprises the first, second and third triggers 71,72,73, the fourth And 74 circuit and the second inverter 75, the input 36 of which is connected to the first input of the fourth And 74 circuit and to the second input 60 of the A / D converter 7, the output of the fourth And 74 circuit connected to the input R of the third flip-flop 73. The input 32 of the first flip-flop 71 m input P of the third flip-flop 73 is connected to the output 31 of the read request of the computer 1 and to the second input of the fourth circuit And 74. The input S of the first flip-flop 71 is connected to the first exit; the second trigger 72 and the input C of the third flip-flop 73. The output of the first flip-flop 71 is connected to the input D of the second flip-flop 72, the output of the inverter 74 is connected to the input R of the third flip-flop 73. The input 35C of the second flip-flop 72 is connected to B1: 1 input 33 of the distributor 19 pulse - Sol Second exit 38 second trigger

79

combination with counting input

m; a counter of 23 address. The output 37 of the third trigger 73 is connected to the input 1 of the read solution of the second ST. The second synchronization circuit 44 is identical to the first synchronization circuit 27. The outputs 62.63 of the second synchronization circuit 44 correspond to the outputs 37, 38 of the first synchronization circuit 27, and the inputs 57, 58, 59 to the inputs 32, 35, 36.

A multichannel digital device for acoustic emission monitoring works as follows.

To organize the simultaneous recording and reading of information about the AE signal, the operation of the blocks is synchronized by gates from the outputs 20, 33, 34 of the distributor 19 pulses.

The acoustic emission signals in each of the reception channels 4 are received by the acoustic transducer 5, amplified by the amplifier 6 in a given frequency band and fed to the input of the ADC 7. During the strobe at the output 34 of the distributor 19 pulses of the ADC 7, a sample code is generated.

corresponding to the amplitude of the AE signal, the sampling code on the leading edge of the strobe in code 20 of the pulse distributor 19 is recorded in the first ST 10 at the address determined by the code at the output of the counter 7 of the address. On the falling edge of the same pulse, the code value at the output of the counter 17 of the address will increase by one and will correspond to the address for recording the next sample of the AE signal. According to the gate, arriving at the synchronization input of the delay register 8 from the output 33 of the pulse distributor 19, the sampling value of the AE signal is written in register 8 delay. The output of the first comparison circuit 9 takes the value of logical 1 if the sampling value of the AE signal is less than the previous one. Such a logic of operation allows the dropout part of each half-wave to be distinguished during the registration of the AE signal.

In some parts of the front of the AE signal, there can be a decrease in the amplitudes of the half-waves of the AE signal, due to the interference of reflected waves, waves of various modes and t, n ,, the device registers completely the front of a complex AE signal,

This makes it possible to improve the temporal reference to the fronts of the signals when determining the difference in the time of arrival of the AE signal through different reception channels. Thus, in particular, an error is excluded when linking to the front of the AE signal by the maximum amplitude. This is achieved by introducing the first and second decoder 40, 41 and the extreme values counter 39. The value of the sample code recorded in register 12 of maximum values is a threshold, above which an absolute value of the code of the current sample begins to register act A3,

With this second comparison circuit 13, a command is generated for the first decoder 40, according to which the strobe on the code 51 of the first decoder 40 sets the output of the extremum counter 39 O for the arrival of a pulse from the comparison output 9 of the first decoder 40, writes the maximum half-wave value of the AE signal to the maximum value register 12 . The second decoder 4 produces a logical O by you0

five

0

five

0

five

0

five

0

five

54, which serves as a command to enable the start of counting the extreme half-wave values of the AE signal. When registering the extremum of the Nth half-wave (in this case), the decoder 41 generates a signal at the output 53, through which the address corresponding to this extremum is written to the address storage register 16, and on the low-order bit of the information word of the first STZ 10, a unit is written indicating the end of the recording of the AE act data. When registering the N + 1 half-wave, the second decoder 41 on the output 54 produces a command for the first decoder 40 on the windows Maintenance bills of extreme values of half-sii- Nala AE. This principle allows avoiding errors when registering the front and pulse of an AE having an uneven increase in the extremes of the half-waves of the AE signal. When registering the following extremes of the half-waves, the first decoder 40 generates pulses at output 49, where the address of the Nth extremum amplitude from the output of the address storage register 16 is rewritten the output of the counter 17 addresses. Thus, in the first STZ 10, only the informative part of each AE pulse is stored. Over time, the code stored in the maximum value register 12, under the control of the code modification unit 14, decreases according to a law close to the attenuation of acoustic waves.

When the amplitude of the signal of the AE ADC 7 changes at the output 61, a pulse is generated that is used to record the current time in the timestamp register 45 (a chip with three input states is used as the timestamp register), the first decoder 40 produces 48 pulses at the output 48 at which the output of the timestamp register 45 enters the active state, and the time corresponding to the start of registration of the next pulse, the AE is recorded in the second ST 26 at the address determined by the address counter 22. The information word ST 26 also contains data about the channel number. On the falling edge of the pulse at the output of the first circuit OR 25, the value of the output code of the address counter 22 is increased by one. Thus the proposed device

captures only the moment of the start of registration of the AE pulse, which leads to a significant econfirmation of the volume of the ST memory.

The first synchronization circuit 27 and the pulse distributor 19 synchronize the operation of the computer 1 and the read and write operations. The third comparison circuit 24 generates a request signal for the servicing of the computer 1 if the value of the output code of the second counter 22 of the address is greater than the value of the output code of the third counter 23 of the address. If there is a request for service, the computer 1 generates at the output 31 a data entry command of the second ST 26, in the presence of which the first synchronization circuit 27 generates control signals for the first multiplexer 21 to connect the address input of the second ST 26 with the output of the third counter 23 of the address to record information on this the address to the buffer registers of the second ST. 26. On the falling edge of the pulse at the output 38 of the synchronization circuit 27, the value of the output code of the third counter 23 of the address increases by one. The computer 1 reads the data about the time of the start of registration of the pulse AE and the number of the corresponding channel 4 of the reception. According to this number, the computer 1 sends a command to the second circuit 44 CHI; - the synchronization of the specified channel and starts & t the data of the amplitude of the AE signal from the first STB 10 of the channel 4 reception. If the pulse period of the generator of 3 pulses is known, the computer 1 can match the sample number of the amplitude of the AE signal with the real time. On the basis of the end of the data on the pulse AE encrypted in the lower section of the information word of the first ST-10, the computer 1 generates a data entry command at the output 31 of the second ST-26. The data is entered into the computer 1 before the end of the service request signal.

Thus, this device allows you to increase the reliability of monitoring by introducing blocks and links that allow you to implement a write-independent reading of data from the ST, while eliminating the dead time required to read information from the ST; implement the principle of recording the time of samples saving the memory size of the ST, which makes it possible to register AE signals

with greater activity and in a larger dynamic range; to improve the registration of the pulse front AE, which allows you to more accurately determine the location of the AE sources.

ten

15

20

25

35

40

45

50

55

Claims (1)

Invention Formula A multichannel digital device for acoustic emission control containing an electronic computer, a time counter, a pulse generator and at least two reception channels, each of which contains a transducer connected in series, an amplifier and an analogue 1 and {fryovaya transducer, electric register, circuit Comparison, first, 1st storage unit, information input of which is connected to the first output of the analog-digital converter, to the input of the delay register and to the input Y of the first comparison circuit, register maxi values, the comparison circuit, the input of the register of the maxImal values, the input Y of the second comparison circuit and the input X of the first. comparison chips are connected to the output of the delay delay circuit, input X of the second circuit; Spamming is connected to the output of reg. 11. Ilia maxc ajn of values, the code modification block, the output of the modifying block of n codes is connected to the first synchronization input of the maximum register register, the address storage register, the first address counter, whose information input is connected to the output of the storage register of the address, the output of the first counter of the address is connected to the input of the register of the storage of the address, the output of the first storage unit is connected to the first information input of the electronic computer, characterized in that controls, a pulse distributor is inputted to it, the input of which is connected to the output of the pulse generator, and the first output is connected to the counting input of a time counter, the first multiplexer, the second and third address counters, the third comparison circuit, the first OR circuit, the second storage unit, the first circuit synchronization, the output of the second address counter is connected to the first input of the first multiplexer and to the input X of the third comparison circuit, the output of the third address counter is connected to the second input of the first multiplexer and to the input Y of the third comparison circuit, the output of the first OR circuit is connected to the recording input of the second storage unit and with the counting input of the second address counter, the output of the first multiplexer is connected to the address input of the second storage unit, the output of the second storage unit is connected to the second information input of the electronic computer, the first the output of the read request of the electronic computer is connected to the first input of the first synchronization circuit, the second and third outputs of the pulse distributor are connected to the second and third the inputs of the first synchronization circuit, the first output of the first synchronization circuit is connected to the read enable input of the second storage unit, and the second output is connected to the control input of the first multiplexer and the counting input of the third address counter, the output of the third comparison circuit is connected to the input of the electronic computing service request machines, an extremal counter, the first and second decoders, the fourth address counter, the second multiplexer, the second synchronization circuit, reg time stamps, where the outputs of the first and second comparison circuits are connected respectively to the first and second inputs of the first decoder, the first output of the first decoder is connected to the information input of the second storage unit, the first input of the first OR circuit and the control input of the time stamp register, the second output of the first the decoder is connected to the input of the record of the first address counter, the third output of the first decoder is connected to the counting input of the extreme values counter, and the fourth output is connected to the second synchronization input of the maximum value register, with the input of the code modification unit and with the installation of the extreme value counter installation, the output of which is connected to the input of the second decoder, the first move of the second decoder is connected to the synchronization input of the address storage register and the information input of the first storage unit, the second output of the second the decoder is connected to the third input of the first decoder, the second output of the read request of the electronic computing machine is connected to the first input of the second sync circuit tions, the first output pulse distributor coupled to the write enable input of the first memory block and with the counting input of the first the address counter, the second output of the pulse distributor is connected to the second input of the second synchronization circuit and to the synchronization input of the delay register, the third output of the pulse distributor is connected to the third input of the second synchronization circuit and to the second input of the analog-digital converter, the second output of the analog-digital converter is connected to the input synchronization register time stamps, the output of which is connected to the information input of the second storage unit, the control input of the first storage unit is connected to output of the second synchronization circuit, the second output of the second synchronization circuit is connected to the control input of the second multiplexer and the counting input of the fourth address counter, the output of which is connected to the first input of the second multiplexer, to the second input of which the output of the first address counter is connected, the output of the second multiplexer is connected to the address input of the first storage unit, the input of the register of time stamps is connected to the output of the time counter. 90 fO j tea CVJ : i SG) tvj mr lO Ш1 } - CJ U -3 Sh -r v; prz ™ rrr: r  -r: rm ----- ™ -14 - | 44 kc iCi C4J SGE Co tr L I  t  J Sh SLij L-JT FIG. 2 ppppppppppppppppppppppp d / gz