SU1325461A1 - Device for sorting numbers - Google Patents

Abstract

The invention relates to automation and computing and can be used in discrete automation devices for solving problems of quasi-optimal control, in particular, in systems for processing test results of technical objects. The purpose of the invention is to increase speed. The device contains registers 1, elements AND 2 polling bits, elements AND 3 analysis bits, elements AND-NOT 4, elements OR 5 bits, multi-input elements OR NOT 6, output elements AND 7, elements AND 8 zeroing, result register 11. The device determines the minimum non-zero number from the numbers recorded in the registers and outputs it to the result register, excludes it from the analysis by zeroing the register in which it is written, then determines the next, its value number, etc. . At the output of the device, a sequence of numbers is sorted in increasing order. 1 il. W (L co w ate 05 & 7aivr i

Description

The invention relates to automation and computing and can be used in discrete automation devices for solving problems of quasi-optimal control, in particular, in systems for processing results of testing technical objects.

The purpose of the invention is to increase the speed of the device by eliminating zero numbers from the sorting process.

The drawing shows a diagram of the device.

The device contains n registers 1, elements AND 2 polling bits, elements AND 3 analysis bits, elements AND-NOT 4, elements OR 5 bits, multi-input elements OR H E 6, output elements And 7, elements AND 8 zero, delay element 9, multi-input element OR 10, result register 11.

The device works as follows.

In the initial state, the zeroing registers (circuits of the initial installation of the device in the initial state are not shown), since this operation can be carried out through the starting input, while at the zero outputs m bits of all the registers high, single potentials are established, and at the outputs of all m bits of register 11 are low. Parameter values in binary code are written by bit through single inputs into registers. If there is no entry in the register on the inverse outputs of its bits ij (where i, ..., ", jl, ..., m) are high potentials, and at the output of the AND-NOT 4 element there is a low potential, then at the outputs of the elements And 2, - /, elements OR Y; - also low potentials, and at the outputs of the elements OR NOT HE 6j - high. And although at the second inputs of the elements AND of the memory are high potentials, but since their first inputs are low potentials, the outputs of the elements And 3, / are low potentials. Low potentials are also maintained at the outputs of the AND 8, - elements, at the output of the OR 10 element, at the output of the delay element 9 and at the outputs of the elements 7 /.

If there is an entry in the register at least in one bit, at the output of the element AND-NO 4, a high potential is established, so that the elements And 2, all the gp bits at the third inputs are under high potentials, since with the contents of the registers 1, and ;, s, 1, a; s, 2, ..., a;, s, w at the output of the element AND-HE 4, a potential is established a;, 4 a;, s, 1 L a, s, 2L - --La ,, Oh, and if at least one value | a.z / | | a, s / j, then ai ,, ai, i, i L ... A ai; D ... 1. Therefore, at the output of the element And 2,;, "| there will be a potential equal to a ,, 5, t a ,, „0 at a ,, t O and / or a; 4 o and a, l., rf ,,, p L a ,, 4 1 with a ;, 1, „, 1 and a, yt 1.

Then the potentials at the output of the elements are determined from the following relations

Element

AND-NOT 4, and, 4 a | Lag1,2L ---- La ,, |,; L --- L

L a ,, | ,, „

And 2ts., 2, / a ,, a /,. (| -1) L at4

And 3, - / a /, f, u, a, 5, (/ -. |) L a ,, 2, / La, -, 4

OR 5, -, - a, -5, a ,, 2,, L and ,, h, /

And 8; a /, 8 a /, 5 l ats

OR-HE6 /

a6 ,, ai, 2, / Va /, 2,, V -.- V Va ,, 2,, V-.Van, 2, / OR 10

, 8Va2,8V --- Va ,, 8V -.- Aan, 8Var. where a „is the potential at the starting input of the device.

Delays (9) Time Delay

on Tzad

on

and 7;

; a, j - aj, j

 a-.i l a

0

five

0

five

0

From the analysis of the above ratios and the device circuit, it can be seen that a high potential is present at any time at the output of the element OR 5 of the first register register 1, which contains the minimum value of the parameter, but different from zero, and, moreover, at the outputs of the elements OR NOT 6 at any moment of time, the code of the minimum, from among those recorded in registers 1, of the parameter value is recorded.

Pulse from the start-up input of the device through the element OR 10 registers II, with a delay in the output of the delay element 9, the contents of the outputs of the elements OR-NOT 6 through the elements 7 and recorded in register 11, through the element 8 the register 1 containing the minimum, but different from zero, the value of the parameter is zeroed, after which the process through the element OR 10 and the other elements is repeated. Moreover, each time in register 1, the next is recorded, in order of increasing absolute values, the value of the parameter.

The process is terminated after all values are sorted, and since the registers are zeroed out at each stage, the device is ready for operation again.

Claims (1)

Invention Formula 45 A device for sorting numbers, containing n registers, where n is the number of sorted numbers, n groups of (ha-1) elements AND interrogation of bits, where m is the size of numbers, n - groups of (m-1) elements And ana. the number of bits, n groups of tons of elements OR bits. m of multi-input elements OR-NOT, m of output elements AND, n elements And zeroing, result register, delay element, moreover, the output of element OR i-th bit of the j-th group, where i 1,2 ..., p. j / l, 2, ..., (m-1), is connected to the first inputs of the elements And polling and analysis (g -) - 1) -th bit of the / -I group, the outputs of which are connected to the inputs of the element OR (/ +1) -th bit of the / -K group, the second inputs of the elements of the AND polling and analysis of the bits of the y-th group are combined, the output of the element OR of the t-th bit of the / -I group is connected to the first input of the / -th element and zeroing, the output of which is connected to the installation inputs in the “About j-th group registers”, the first inputs of the elements OR of the first bits of all groups are connected to the inputs of the first element OR — NOT, the output of which is connected to the second inputs and elements And the first bits, the outputs of the elements AND the demand of all () bits are connected to the inputs (i-fl) -ro of the element OR-NOT, the output of which is connected to the third inputs of the elements AND of the analysis () -th bit of all groups , the outputs of the output elements And are connected by the corresponding information inputs of the result register, the second inputs of all elements And zeroing and the first inputs of the output elements And are connected to the output of the delay element, characterized in that, with a goal of increasing speed. 0 it contains n elements AND polling of the first bits, n elements AND-NOT and a multi-input element OR, and the inverse output of the first bit of the / -th register is connected to the first input of the / -H element AND of the first bit whose output is connected to / the m input of the first element OR NOT, the inverse output of the (r + 1) -th bit of the / -th register is connected to the third input of the AND polling element of the (/ + 1) -th bit of the / -th register, the inverse outputs of all bits The / -th register is connected to the inputs of the / -th element of the NAND, the output of which is connected to the second inputs of all the elements of AND interrogation and analysis The jth group's arrays, the outputs of the zeroing elements are connected to the n inputs of the OR multi-input element, (n + 1) whose input is connected to the device start input, and the output is connected to the input of the delay element and the setting input in “About the result register, the outputs of the elements OR are NOT connected to the second inputs of the corresponding output elements I.