SU1396250A1 - Pulse shaper - Google Patents

Abstract

The invention can be used in automation and computing devices, as well as in control devices for digital systems. The invention allows to expand the range of variation of delays and durations of the generated pulses, which is achieved by introducing into the device a second counter 4 pulses and an element OR 9. In addition, the device contains a master oscillator 1, element II 2, counter 3 pulses, block 5 of memory , registers 6 and 7, output unit 8, input gaine 10 and output buses 11. The output unit can be made in the form of a storage register. The operation of the device is explained in the table provided in the description of the invention. 2 ill., I table. about S9 (L 7J S u i

Description

The invention relates to a pulse technique and can be used in automation and computing devices, as well as in control devices for digital systems.

The purpose of the invention is to expand the range of variation of the delays and durations of the generated pulses. .

Fig. 1 shows an electrical block diagram of a pulser; 2 shows timing diagrams for his work.

The device for forming the pulses contains the master oscillator 1, the element AND 2, the first 3 and the second 4 pulse counters, memory block 5,. the first 6 and second 7 registers, output block 8, element OR 9, input bus 10 and output lines 11, connected to the corresponding outputs of the output block I, I. The first input element. That I. 2 is connected to the output of memory block 3, the output is to the installation input of the first counter of 3 pulses and to the first input of the first register 6, whose informational inputs are connected; through the second register 7 with the input bus I I. 10. The output of the master oscillator 1 is connected to the second input of the first register 6, with the counting inputs of the first 3 and second 4 counters; owls and with the first input of the output block; 8, the second input of which is connected: to the output of the second counter 4 impulses; and to the control input of the first I counter 3 impulses. The first and second groups of outputs of the memory block 5 are connected to the information inputs of the output block 8 and the second counter of 4 pulses, respectively. The second input element AND 2 is connected to the installation input of the second counter 4 pulses and to the output of the element OR 9, the inputs of which are connected to the outputs of the corresponding bits of the second counter 4 pulses. The lower and higher address bits of the memory block 5 are connected to the corresponding outputs, respectively, of the first counter of 3 pulses and the first register 6. The output block I can be executed in the form of a storage register.

The device works as follows.

Let it be necessary to form pulses in three channels - (on three of the tires 11) devices with a period of trace

Q

H 0 5 Q .Q 5 Q

five

vani T UTr with the following values of delays t and durations: in the first channel t О, ty in the second channel Ь ЗТ, t in the third channel t вТ, ty Тd,

As can be seen from FIG. 2, in the time diagram, there are five sections (time intervals) in which no change of information occurs. The time diagram of the device can be described as logical states O and I, with the establishment of a level at the output of the device corresponding to the formation of the leading edge of the pulse, the steady-state value of the pulse duration, and the establishment of the level O of the falling edge of the pulse (decay).

The logical states of the allocated plots in the time diagram of the device are presented in the form of a table.

Before starting work, block 5 is loaded with information about the time parameter X of the generated pulses on the corresponding buses 11 in accordance with the time diagram of the device (in the case of using a permanent storage device, information is recorded before it is installed in the device). Each of the allocated plots corresponds to a certain cell of memory of block 5. In the first three bits of the cell of memory (the first group of outputs of block 5), information about the state of the channels at the output of the device is set in the divided time interval, the fourth bit of the memory cell (output block 5) determines the pulse-following period T, and in subsequent bits of the memory cell (the second group of outputs of block 5) the information on the multiplicity K of the formed time interval is set to the period T of the repetition of clock pulses minus one period ", i.e. K-1; Then, the counters 3 and 4 and the block 8 are set to the zero state (the installation means are not shown), and in the register 6 from the register 7 it records the information about the selected number of the pulse sequence. Before the start of operation, the information outputs of counter 4 are in the zero state, then the output of element 9 is also set to level O, which allows information to be recorded into counter 4 from block 5. At the output of the counter, a signal is generated that delays the operation of counter 3 in counting mode and recording information from block 5 to block 8

Thus, in the initial state, the first group of outputs of block 5 is set to levels 100, according to the third pulse counter 4 does not change its state, because the information at its inputs is zero, and the contents of counter 3 are incremented by one, which corresponds to the choice of the third time interval . The further process of forming the time diagram occurs as described.

change to the first time allotted IQ zom with the change of information until the appearance

ABOUT,

the interval (see table), the output of block 5 is set to 1, and on the second group of outputs - the multiplicity of repetitions (K-1), represented in binary code (in the case of Naga). Then, the start of the master oscillator 1 / trigger circuit (not shown) is performed. The pulses from the generator 1 output go to the counting inputs of counters 3 and 4, into register 6 and into block I. The leading edge of the first pulse is copied from block S to block 8, as a result of which the leading edge of the pulse is formed in the first canape of the device. At the same time, the number 1 is transferred to the counter 4 from the block 5., and the counter 3 increases its contents by one, which corresponds to the choice of the second time interval. At the output of element 9, a level 1 is set, which permits the operation of counter 4 in the subtraction mode, and at the output of counter 4, a signal is generated that prohibits the operation of counter 3 in counting mode and the recording of information into block 8. By the time the second pulse arrives at the outputs, block 5 - the information corresponding to the states of the second selected time interval is set (see, table).

With the arrival of the second pulse from the output of the generator 1, the counter 4 decreases its content by one, i.e. is set to zero, at the output of element 9, a level O appears, allowing the recording of information, into the counter 4, the output of which sets the level O, allowing the operation of the counter 3 in the counting mode and writing the information into block 8.

With the arrival of the leading edge of the third pulse, the O level is formed at the output of the first channel, which corresponds to the trailing edge of the pulse being formed.

Thus, at the output of the first channel of the device, a pulse of duration t 2To is formed. With coming

at the output of the U level block 5, as a result of which the output of the element 2 generates the enable signal of setting the counter 3 to zero and more

15 recording information from register 7 to register 6. With the arrival of the tenth pulse, the device returns to its initial state. With the arrival of the eleventh pulse, the process of forming the 2Q time diagrams with the specified time pulse widths in the channels repeats.

Claims (1)

Invention Formula thirty 35 40 25 A device for generating pulses containing a master j eHepator, the output of which is connected to the counting input of the first pulse counter and the first input of the output block, whose outputs are connected to the corresponding output buses, the information inputs to the first group of outputs of the memory block, lower address bits The ports of which are connected to the corresponding outputs of the first pulse counter, the upper address bits to the corresponding outputs of the first register, whose information inputs are connected through the second register to bus, the first input - with the installation input of the first pulse counter and with the output of the element I, the first input of which is connected to the output of the memory unit, the one that is connected with the purpose of expanding the range of variation of the delays and the durations of the generated pulses, the second pulse counter and the OR element are entered into it, the output of which is connected to the second input of the AND element and with the installation input of the second pulse counter, the inputs with the outputs of the corresponding bits of the second pulse counter, whose information inputs are connected to the second group of outputs of the memory unit, the counting input with the second input of the first register, and the first input of the single output 50 55 Zom with the change of information before the appearance ABOUT, at the output of the U level block 5, as a result of which the output of the element 2 generates a signal for setting the counter 3 to zero and more recording information from register 7 to register 6. With the arrival of the tenth pulse, the device returns to its original state. With the arrival of the eleventh pulse, the process of forming a time diagram I with the specified time para-pulses in the channels repeats. Invention Formula 0 five 0 five A device for generating pulses containing a master j eHepator, the output of which is connected to the counting input of the first pulse counter and the first input of the output block, whose outputs are connected to the corresponding output buses, the information inputs to the first group of outputs of the memory block, lower address bits The ports of which are connected to the corresponding outputs of the first pulse counter, the upper address bits to the corresponding outputs of the first register, whose information inputs are connected through the second register to bus, the first input - with the installation input of the first pulse counter and with the output of the element I, the first input of which is connected to the output of the memory unit, that is, with the purpose of expanding the range of variation of the delays and the durations of the generated pulses, the second pulse counter and the OR element are entered into it, the output of which is connected to the second input of the AND element and with the installation input of the second pulse counter, the inputs with the outputs of the corresponding bits of the second pulse counter, whose information inputs are connected to the second group of outputs of the memory unit, the counting input with the second input of the first register, and the first input of the single output 0 five 51396250 iro unit, the second input of which is the pulse connector and with the output of the second one with the control input of the first pulse counter.