SU1372330A1 - Device for connecting microprocessor with external devices - Google Patents

Abstract

The invention relates to computing and can be used in microprocessor-based data processing systems for communicating a microprocessor with external devices connected to an interface trunk. The purpose of the invention is to expand the field of application of the device by providing connectivity to the interface trunk

Description

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external devices of different speeds. The goal is achieved by the fact that in a device connected to the interface highway 1 of external devices and containing groups of bus drivers for address 2 and data 6, a generator of 3 clock signals, element I, state register 5, decoders of address 7 and control signals 8, node 9 the formation of the ready signal, including the first trigger 13, is introduced into the node 9 of the formation of the ready signal, the second trigger 14 and the three elements OR 11.12 and 15. 3 Il.

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The invention relates to computing, in particular to means of microprocessor control, and can be used in data processing and control systems.

The purpose of the invention is to expand the field of application of the device by allowing the use of external devices of different speeds in the system.

Figure 1 presents the block diagram of the device; Fig. 2 is a functional diagram of a readiness formation node; FIG. 3 is a time diagram of the operation of the device.

The device is connected to the interface line I of external devices and contains (FIRE group of bus drivers 2 addresses, generator of 3 clock signals, element 4, state register 5, group of bus drivers of data 6, address decoder 7, control decoder 8 and node 9 forming a ready signal o The external interface 10 is connected to the interface line 1, which are either memory devices or input devices, including slow action, requiring standby operation.

For example, a persistent storage device with multiple reprogramming with electrical recording and erasing information such as KI60IPP1 can be used as a slow-acting storage device; an electric typewriter of the Consul type can be used as a slow-acting input / output device.

The node 9 of the formation of the ready signal (figure 2) contains the elements OR

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11 and 12, triggers 13 and 14, and the element OR 15.

For communication with external input / output devices and memory devices, the following signals from the interface bus 1 are used: ADRs are address signals indicating the address of the memory cell or input-output devices; INF - information, serving to transfer data, commands, states, etc .; CTE - reads the memory, indicates that information is being read (commands, data, etc.) from the memory device; RUPD — write to memory indicates that information is being recorded to the memory device; FTVT — reads an input / output device, indicates that information is being read from external input / output devices; RELT — write to I / O devices, indicating that recording is being made to external I / O devices; OTV is a response indicating that the specified operation is complete; ESR - interrupt request; SPR - interrupt confirmation.

The device uses the following microprocessor signals (580ВМ80): AO-A15 - address, indicating the address of the memory cell or the address of an external input / output device; DO-D7 - data intended for the transmission of command data, states; SYNCHR - synchronizing, indicating the beginning of each machine cycle of the microprocessor; RECEPTION - indicates that data bus DO-Д7 is in the mode of entering information into the microprocessor; OUT - indicates that the data buses are in the mode of outputting information from the microprocessor; The GT is a ready signal indicating that there is information on the data buses;, F1, F2 - clocking and pulses.

A device for communicating and exchanging information over i) 1 interface bus 1 provides a program mode under the influence of a microprocessor and a mode of organizing communication and exchanging information on an interrupt.

At the beginning of each machine cycle in cycle T1, the microprocessor generates a synchronous sync signal. In the same cycle, the microprocessor sets the address of the memory cell or input-output device on address buses AO-A15. The address remains constant until the occurrence of the F2 pulse in a clock cycle that follows the clock cycle of the current cycle. An 8-bit control word is output on the data bus cycle T1.

In the T2 cycle, by the F2 pulse, the SYNCHR signal is picked up and the Acceptance signal is set, the microprocessor switches to the information receiving mode. In the T2 cycle, on the trailing edge of the F2 pulse, the GT signal is also analyzed.

Depending on the value of this sig

The transfer is made either to the TK cycle of the machine cycle or to the TOL state, the output of which is available only if there is a signal at the GT input of the microprocessor that corresponds to the readiness of the memory or external input-output device.

In the TK cycle, data from the storage device or an external I / O device is received on the data bus, the signal at the output F is received at the output RX,

In beats T4 and T5, if they are needed, actions are performed on the operands. By the pulse F2 of cycle T4, the value of the address on the address bus changes with, and its value is undefined until the occurrence of the pulse F2 of the cycle T1 of the next cycle.

The microprocessor operation diagram during information output differs from the one considered only in that the EXTRA signal appears on pulse F2, in a tick following T2 cycle, and is picked up on a pulse F1 of T4 clock.

In the last cycle of the last command cycle, the signal level at the microprocessor DSS input is checked. With a high level of this signal and the previously established internal trigger

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PERMISSION. INTERRUPTION microprocessor on the clock pulse F2 of this cycle sets the internal trip-er interruption. The next skinny cycle will be the INTERRUPT cycle. In this loop, the word Confirmation of the interrupt request is set in the control word. After the control word is decrypted, this code will correspond to the SPR signal (interrupt confirmation). The device that issued the interruption request receives it and sends the interrupt vector code to the information fields INF.

Thus, from the description of the time diagram of the microprocessor, we can conclude: there are periods when the bits of the address bus are in the B unspecified state; the readiness signal must be determined before the appearance of the command signals on the control bus; between the analysis of the signal ZS and the issuance of the control signal of the SPR, the microprocessor checks the signal GT.

The device works as follows.

The signal SYNC and pulse F2 through the element 4 and 4 in register 5 enter the control word code, which determines the operation mode of the microprocessor in this cycle. The control word bits are fed to the input of the decoder 8, where the decoding and generation of one of the control signals of the RUPD, CHTZU, PZVV, PTVU, PPR interface is performed using the signals from the microprocessor microprocessor.

When the microprocessor accesses a slow device (external storage device or I / O device), the output of the decoder 7 generates request signals for waiting for the ZAPR1 or ZAPR2, which correspond to either the reference to the slow memory (ZAPR1) or the appeal to the slow explosive (ZAPR2) o Signals ZPR1 and ZALR2 arrive respectively at the inputs of the flip-flops 13 and 14.

The operation of the circuit in the case of a slow memory is as follows. The signal SYNC and pulse F1 at the output of the trigger 13 will set the signal corresponding to the unavailability of the memory. Through the element OR 15, it enters the input of the microprocessor and translates it into the state of TOX. The OTV1 signal from the slow memory passes through the OR 1I element and resets the trigger 13. In the case of a part of the address bits used for addressing the memory cells and I / O devices on the decoder code 7, the ZAPR1 signal also appears, although the address at this moment occurs fast I / O device. The trigger 13 will also be set to the state corresponding to the unavailability of the memory, but already in T2 pulse F2 when reading the slave. In the next clock pulse F1, when writing to the I / O device, the HTVV signals, or the SCRV, respectively, which, having passed through the OR 11 element, reset the trigger 13 and the GT signal again, are set to devices and the microprocessor will continue to perform the work

Similarly, it works with a slow I / O device. To reset trigger 14, in the event of an unforeseen occurrence of an unavailable signal, use

signals OTV2, RUPD, ZPVV.

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If a request for an interruption of the HRPT appears during a call to a slow-acting charger, then the trigger 13 will also be set to a state of inconvenience, since the address of the ADR buses in T1 and T2 will be given the address of this charger. But already in the T2 cycle, the F2 signal instead of the commands to access the memory (RUPD or CHTZU) from the output of the decoder 8 will produce a PRD signal that, having passed through the OR element 1, will reset the trigger 13 and the microprocessor will continue the work on interrupt processing.

As a result, when using external devices with different speeds in the system when using the full address space, the time of unforeseen waiting is only one machine cycle in the case of writing to external devices (RUPD or RPC), or there will be no such intervals at all in the case of commands to read external devices ( CTZU, CTTV) or the occurrence of the signal R1P, therefore, the system hangs situations are excluded.

Claims (1)

The device for communication of a microprocessor with external devices, containing a group of address bus drivers, the inputs and outputs of which form a group of inputs and outputs of the device, respectively, for connecting to the address bus of the microprocessor and the address bus of the external devices address decoder, status register, control decoder signals, the group of outputs of which forms a group of outputs of the device for connecting external devices to the bus control bus, and information inputs are connected to the output of the state register, controlled by the input of the connected to the output element I, the group of bus data drivers, the first information inputs / outputs of which are connected to the information input of the status register and are a group of inputs and outputs of the device for connecting to the microprocessor data bus The outputs of the bus group data drivers form the input-output device for connecting the external devices to the data bus, and the clock generator, the first and second outputs of which are The corresponding outputs of the device for connecting to the microprocessor clock inputs, the first input of the element I are connected to the output of the clock signal generator, and the second input is the input of the device for connecting to the microprocessor clock output, the control inputs of the control decoder and the bus data drivers form the input of the device for connecting to the output of the microprocessor exchange mode setting, and the readiness signal forming unit, including the first trigger, with the information input united with the first output of the address decoder, characterized in that, in order to expand the field of application of the device, the second trigger and three OR elements are entered into the readiness signal generation node, the address decoder input connected to the outputs of the group address bus generators, and the second output connected to the information the input of the second trigger, the synchronization of the first and second triggers are connected to the output of the element I, the inputs resetting the first and second flip-flops are connected respectively to the outputs of the first and second OR elements, the input groups of which are connected to the control decoder signal output group, the inputs of the first and second OR elements are the corresponding device inputs for connecting the PLS .1 ZLVZ ijTee calving / 7 FOR PR. 2 PAGE Smug In the first and second external device synchronization buses, the outputs nepBoi o and the second flip-flops are connected respectively to the first and second inputs of the third OR element, the output of which is the output of the device for connecting to the microprocessor ready input. / J 75 GT / FIG. 2 DO-If7 CuHxp Fig.Z