SU1234963A1 - Automatic tracking divider of periods of pulsed signals - Google Patents

Abstract

The invention can be used in automatic devices for dividing the time-varying period of tracking of large-scale pulses, angle marks, etc., for example, in diagnostic equipment for carburetor engines, diesel engines, turbines, pumps, etc. for determining uneven rotation of the shafts. The purpose of the invention is povapenie accuracy. (Lgo 00 4 CO a 00

Description

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dividing in a dynamic mode, is achieved by taking into account not only the first, but also the second and subsequent losses over time. The device contains a reference generator 1, trigger 2 strobe, delay line 3, adder 4, two identical channels I and II. Each channel contains a controlled divider 5 by a given division factor n, counters 6-11 pulses, triggers 12-16, registers 17-19, the next divider .0, delay element 21 null-organ

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The invention relates to a pulse technique and can be used in automatic devices for dividing the time-varying period of the following scale impulses, angle marks, etc., in particular in the equipment for diagnosing the mechanisms of cyclic action - carburetor engines, diesel engines, turbines, pumps and etc. - to determine irregular rotation of the shafts.

The aim of the invention is to increase the accuracy of dividing dynamically the time-varying periods of the pulse signals by taking into account not only the first, but the second and subsequent time derivatives of the changing periods.

The drawing shows a structural diagram of an automatic follow-up period divider of impulse si-channels.

The divider contains the reference generator 1, the trigger 2 of the gate, the line 3 of the delay for 1/2 period of the pulse of the reference generator 1, the adder 4, two identical channels, each of which includes a controlled divider 5 by a predetermined dividing factor n, the first counter is 6 pulses (the K numbers of the scale units of the reference generator 1), the second counter is 7 pulses (remainder counter) ,, the third counter is 8 pulses (accumulative), quarter-HF 9, fifth 5 and sixth 1G pulse counters, the first

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22, elements AND (ZI-NK) 23 and 29, gold And (2I-NOT) 24, 25, 26, 27 and 28, elements 2I-2Sh1I-NOT 31 and 32, NSKLKY SOTSEE OR 33, inverter FOR, elements AND 35 and 36, elements OR 37 and 38. The introduction of new elements and new functional relationships provides for the formation of an additional amendment introduced to the controlled divider. This makes it possible to take into account the presence of second and higher derivatives in the law of variation of the dividend period. 1 silt

12, the second 13, the third 14, the fourth 15 and the fifth 16 flip-flops, the first register 17 (the memory of the K number), the second register 18 (the memory of the remainder 1), the third register 19, the next divider 20 with the automatically settable by ficent dividing, delay element 2, null-organ 22, first element AND 23- (ZI-NOT), second element AND 24 (2I-NOT), third element AND 25 (2I-NOT), fourth element And 26 (2I- NOT), p - element And 27, the sixth element And 28 (2I-NOT), the seventh element And 29 (ZI-NOT), the eighth element And 30 (2I-NOT), the first element 31 and the second 32 elements 5ent 2I- OR OR NOT.

The divider of the pulse following periods also contains the element IC- KEY OR 33, the inverter 34, the fifth 35 and the tenth 36 And elements, the first 37 and the second 38 KPI elements.

The output of the reference generator 1 is connected to the input of the line 3 of the delay for 1/2 the period of the following pulses of the reference generator. Each of the channels includes serially connected first pulse counter 6, first register 17 and next divider 20, serially connected controlled divider 5, second register 18 and second counter 7 pulses, the rising speed of the controlled divider 5 is connected to the input of the first counter 6 pulses, the third counter of 8 pulses, the information inputs of which are connected to information 1

The first inputs of AND 23, the output of which is connected to the subtractive Bxonv of the supervised divider 5, the second 24 and the third 25 And elements, the first inputs of which are connected to the output of the reference generator 1, the outputs to the subtracting inputs of the second 7 and third 8 pulse counters, respectively, and the second inputs - to the output of the first trigger 12, the first input of which is connected to the output of the second counter 7 pulses, and the second. - to the output of the following divider 20 and to the input of the adder 4, the fourth element I 26, the first input of which is connected to the output of the reference generator, the second to the output of the third counter 8 pulses, and the output to the subtractive input of the following divider 20, the fifth 27, the sixth 28 and seventh 29 elements And, the second 13, the third 14 and the fourth 15 tripers, the first 31 and the second 32 elements 2I-2OR-NOT, the fourth counter of 9 pulses connected in series, the third register 19 and the fifth counter of 10 pulses, the outputs of the fourth the counter 9 is connected to the inputs of the zero-body 22, the output of the fifth counter 10 pulses are connected to the R-input of the second trigger 13, the S-input of which is connected to the input of the device, and the direct output to the first input of the fifth element I 27, the second input of which is connected to the output of the delay line 3 by 1/2 following period pulses of the reference generator 1, and the input to the subtracting input of the fifth counter 10 pulses and the first input of the first element 2I-2ILI-NO 31, whose input is connected to the first input of the first element I 23, and the second input to the forward output of the third trigger, 14, the inverse output of which is connected to the first input of the six-pole AND gate 28. the second; the course of which is co-linear with the first input of the fifth element I 27, and the output with the third input of the first element I 23, the delay element 21, the input of which is connected to the control inputs of the first 17 and second

18 registers of its channel, and input to the third register 1U of another channel, to the R-input of the fourth trigger 15 of another channel, as well as to the control input of the first counter 6 pulses of its channel, to S-BXO- third 14 and fourth 15 flip-flops, control input four

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counter 9 pulses of its channel, the subtracting input of which is connected to the output of the seventh element I 29, and the summed input to the output of the second 5 element 2I-2NLI-NOT 32; In addition, in each channel, the R input of the third trigger 14 is connected to the output of the null organ 22 and to the counting input of the fourth Tpiirrepa 13, the direct output of which

0 is connected to the first input of the seventh element I 29 and the inverse output to the first input of the second element 2И 2ШШ-НЕ 32, the second and third outputs of which are connected to the second input of the seventh element I 29 and the output of the reference generator, the first output of the trigger 2 strobe connected to the input of the delay element 21 and the third input of the seventh element And 29 of the first channel, as well as the fourth input of the second element 2I-2ILI-NOT 32 and the second input of the first element And 23 of the second channel, and the second output - to the input of the delay element 21. and the third is the input of the seventh element And 29 watts the first channel, and also with a quarter input of the second element 2I-2ILI-HE 32 and the second input of the first element I 23 of the first channel, the R-input of the second trigger 13 each, the second channel connected to one of the inputs of the first element of the GSHI 37, R-input n That trigger of each channel is connected to the output of a gaest counter of 11 pulses, S-input to the output of the first element OR 37, direct output to the second input of the eighth

0

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element I 30, the first input of which is connected to the output of the line 3 of the delay or 1/2 of the pulse-following period of the linear generator 1 and to the first

the entrance of the ninth em.I 35; the starting input of the sixth counter T1 of pulses of each channel is connected to the device input, the subtracting input to the output of the eighth element I 30, the information inputs to the information outputs of the third register 19, the first input of the element EXCLUSIVE OR connected to the inverse output of the fifth trigger 16 of the first channel, the second input - to the inverse output of the fifth trigger 16 of the second channel and to the first input of the tenth element I 36, and the output to the input of the inverter 34, the output of which is connected to the second inputs of the ninth 35 and tenth 36 elements And, the output of the nine that of the AND gate 35 is connected to the first input of the second OR gate 38, the second input of which

It is connected to the output of the reference generator, the third INPUT of the first element 2I-2SH1I-NO 31 of each channel is connected to the output of the second element OR 38, the fourth - to the output of the tenth element And 36.

The automatic following divider of the Leriods of pulsed signals operates as follows.

A pulse sequence with a time-varying following period is fed to the input of trigger 2 of the gate and simultaneously to the recording input of the sixth counter 11 pulses of each channel. The signal from the output of the trigger 2 strobe alternately opens the first elements AND 23 of both channels.

. With the arrival of the first pulse, the first element AND 23 of the first channel opens at the second input and the second element 2I – 2ILIL 32 of the second channel opens at the first input. The pulses of the reference oscillator with the following frequency fg from the output of the first element 2I - 2, OR - NO 31 through the first element I 23 arrive at the subtractive input of the controlled divider 5. From the output of the controlled divider 5, the pulses with the following frequency f ,, / п fill the first counter 6 pulses of the number K of the scale units of the reference generator t. At the same time, the pulses of the reference generator 1 with the frequency of the trace-f from the output of the second element 2I-. 32 is filled at the summing input of the fourth pulse counter 9. The filling of the first 6 and fourth 9 pulse counters continues until the next input pulse arrives. The time between the first and second input pulses, equal to Tn, the divisible period, is the measurement time. At the same time, the first counter 6 pulses of the number K of the Scale units of the reference generator 1 is counted; K Tg / p is the t pulses (t is the period of the reference generator), and in the controlled divider 5 the remainder C remains in the Divided coefficient, where “Td), M ,; M is the number of impulses. Owl reference generator 1 in the dividend. period, which is counted by four-meter counter 9 pulses.

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With the arrival of the second input pulse, trigger 2 of the gate transitions to the second steady state, the first element 23 of the first channel closes, the pulse from the second output of trigger 2 of the gate enters the control inputs of the first register 17 (memory of the K number) and the second register 18 (memory The numbers f) to the first input of the second element 2I-2IL-NOT 32 and through the element 27 of the delay 21 to control the “1st input of the first counter of 6 pulses. The code combinations corresponding to the numbers K and are fixed in the first 17 and second 18 registers, respectively. The first pulse counter 6, with a certain delay determined by delay element 21, is reset to zero.

With the arrival of the second input pulse, the measurement time ends and the testing starts, i.e. division of the measured period. At the same time, the second element 2I-2ILI-HE 32 is closed at the first input, the seventh element I 29 opens and starts filling the subtracting input of the fourth counter 9 pulses with pulses of the reference generator 1. During the second quarter period, the counter of pulses 9 counts M - the number of pulses of the reference generator 1 in the second period. The difference in the numbers M, - M, indicating the change in the period of the input sequence, is recorded in the third register 1.9 at the end of the second period with the arrival of the third input pulse and on the Information Inputs of the fifth pulse counter 10 and determines the correction that is made to the controlled divisor. 5 in the next third period - the next measurement period in the 1st ka-. Nalb.

 The third input pulse at the S-input of the second trigger 13 sets it to the state of a logical unit at the forward output, the fifth. And 27 opens, the pulses of the reference generator 1, delayed by line 3 delays by 1/2 of the period t, are received by subtracting 1- The first input of the first counter is 10 pulses and the third input of the first element 2И-2ШШ-НЕ 31.

Consider three possible options: Mj M,, M, - M,, M, M ,.

The 1/2 pulses of the reference generator 1 from the output of the lnn 3 delay are sent to the subtracting input of the fifth counter 10 pulses and the third and fourth inputs of the first element 2I-2ILI-HE 31, the output of the last one and the pulses of the reference generator I delayed by 1/2 of period t. (pulses from the third and fourth inputs) are fed through the first element I 23 to the input of the controlled divider 5. As soon as the fifth counter of 10 pulses counts ftM delayed by 1/2 period t, pulses, the second trigger 13 is faulty, the fifth element AND 27 is closed, the passage of delayed by ½ period t - the pulses of the reference generator 1 to the subtracting input of the fifth counter 10 pulses and the third and fourth inputs of the first element 2I-2IL-HE 31 stops . The code on the fifth counter 10 pulses is updated by a census from the third register 19, but the count is not renewed 5 because the pulse is at the S input of the second trigger (W is not.

Thus, for the third period, the input of the controlled divider 5 receives M pulses from the reference generator 1 and dM delayed by 1/2 period t pulses, as a result of which the sequence M enriches by LM pulses, M M + JM. The value of T + lT, measured in three. period is equal to T, | - the period of testing.

If M, M, M O, the Sequence M at the input of the controlled divider 5 is not enriched and is not depleted j the correction is not made. The fourth counter 9 pulses as a result of measurement (at the end of the processing period) comes to zero and through the null body 22 keeps the third trigger 14 at the R input in the state of a logical unit at the inverse output. A fifth pulse counter 10, the information inputs of which are recorded. zero, keeps the second trigger 13 in the state of logical zero at the direct output, which closes the fifth element And 27, prohibiting the passage shifted by 1/2 of period t. pulses from the output line 3 delay input

counter 10 pulses and k.a third input of the first element 2I-2ILI-NOT 31.

At the output of the sixth element And 28, a logical unit is established, no intervention in the operation of the first element, And 23 occurs.

Thus, a comparison is made of the two post periods of the input pulse sequence (Tpj and 1). The code combination of the difference Tr - TD & T at the end of the second period (period of testing) by the third input pulse is recorded in the third register 19 and on the information inputs of the fifth counter of 10 pulses, it is determined by the correction, the divisor 5 3 next 1, the leaner period - the next measurement period,

The signal from the output of the sixth element And 28 closes the first element And 23 by T, if the period of the input pulse sequence decreases by l T. M detainees by 1/2, the period tp -1 pulses of the reference generator 1 from the output of the first element: that 2И-21 CHI-HE 31, adding gots to the M pulse sequence of the reference generator 1 at the input of the controlled divider 55 if the period of the input pulse sequence is increased by A. So if the period of the input pulse sequence does not change, then no correction is made.

The distribution of the remainder recorded at the end of the measurement period in the second register 18 is the same as the 3 lime devices,

With the arrival of the second input pulse, the measurement time ends and the testing period begins, i.e. de j. life measured period. At the same time, the code combinations of the number K (equal to the number of pulses of the reference generator t, falling on the n-th part of the divisible period) from the first counter. 6 pulses are recorded in the first register 17 and on the information inputs of the next divider 20. The code combination of the remainder f is written in the second register 18 and on the information inputs of the second counter 7 pulses. The code combination of the number n is written on the information inputs of the third counter of 8 pulses.

The pulses from the output of the reference generator 1 through the open fourth element And 26 continue to flow to the subtractive input of the following divider.

Let M M, i.e. the entry-to-sequence period is reduced. The pulses from the reference generator 1 through the first and second inputs of the second element 2I-2ILI-NOT 32 again arrive at the summing input of the fourth counter 9 pulses, the latter counts M - the number of pulses of the reference generator 1. in the third divisible period. From the output of the line 3 delays. The impulses of the reference generator, delayed by 1/2 the period t, are fed to the subtracting input of the fifth counter of 10 pulses.

The third trigger 14, on the inverse output of which a logical unit is set, together with the logical unit on the direct output of the second trigger 13 closes the sixth element 28, which closes the first element 23 on the third input, the pulses of the reference generator 1 on the input of the controlled divider 5 do not come. As soon as the five counter of 1 pulses counts down the IMMM pulses, at its output a zero appears, the second trigger 13 reverses, the sixth element And 28 opens, and removes the prohibition from the third input of the first element II. , the latter opens, the pulses of the reference generator 1 from the output of the first element 2I-2, OR-NOT 31 begin to flow to the input of the controlled divider 5,

: Thus, the controlled divider 5 starts in the third, period, an account with a delay of T time - 1 g (T, is the duration of the first input period; T, is the length of the second input period) and counts P - Mj - l M pulses (dM M, - M) As a result, the pulse train is depleted by dM pulses.

If each subsequent period of the input sequence is less than the previous T., - T by the value of LT - const, then the value of T - dT, measured in the third period, is equal to Tc - the period of testing.

In the fourth pulse counter 9, which is filled in the third period by the summing input, the number Mj is recorded at the end of the third period,

In the fourth period (the period of testing), the fourth leg of the counter of 9 pulses goes through the live input. The difference M ,, - Mj at the end of the fourth period is fixed at one third

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The register 19 and the information inputs of the fifth counter of 10 pulses determine the correction applied to the controlled divider 5 in the fifth period - the next measurement period in the 1st channel, h, etc.

Let M M, i.e. the period of the input pulse sequence is increased,

M is the number. Recorded at the summing input of the fourth counter 9 pulses in the first period, less than M is the number of pulses of the reference generator 1, coming} on the subtracting input of the fourth counter 9 pulses in the second period,

As soon as the number of pulses is 5 when-. followed by a subtracting input to the fourth counter 9 pulses, becomes equal to M, (zero state of the fourth counter 9), it goes to the All 1 state and starts counting in reverse order, which does not make sense. In order to avoid this, a null organ 22 is inserted into the divider. The zero outputs of the fourth counter 9 pulses are connected to the input of the well organ 22, which, when the fourth counter of 9 pulses passes through zero, produces a pulse to the R input of the third trigger 14 and on the counting input of the fourth trigger 15. The third 14 and fourth 15 triggers and the switch-. are in love. The fourth trigger 15 closes the seventh element I 29 (the pulses of the reference generator 1 to the subtractive input of the fourth counter 9 pulses are stopped) and opens the fourth input of the second element 2I-2ILI-HE 32, and the pulses of the reference generator 1 arrive at the sum of the fourth input. go counter 9 pulses. The counting starts from No.ul to IM (dM M, - M,).

Thus, at the end of E; the second period (processing period), the third combination of the M number is recorded on the third register 19 and on the information inputs of the fifth counter 10 pulses, the third trigger 14 sets the state of the logical unit on its forward code .i thus opens the fourth input of the first element 2I-2ILI-NOT 31. The second trigger; 13 is set to the state of the logical unit at the direct output. P -. The second element And 27 is cut off, Zad20. As soon as the next divider 2i with the automatically set division factor counts in the countdown mode K of the pulses of the reference generator 1, it is completely cleared and an impulse appears at its output. This pulse rewrites the code combination of the number K from the first register 1 7 to the informational input divider 20 and triggers the first trigger 12, which opens the second 24 and third 25 And elements, which transmit pulses of the reference generator 1 to the input of the second counter 7 pulses (the counter the remainder) and at the input of the third counter 8 pulses (storage).

As soon as the second counter 7 pulses in the countdown mode counts the number of pulses of the reference generator 1 equal to the remainder, it is completely cleared and a pulse appears at its output, which again rewrites the code combination of the remainder C from the second register 18 and transfers the first trigger 12 to another A steady state is 1 {s. The signal from the output of the first trigger 12 closes the second 24 and third 25 elements AND, and in the third counter of 8 pulses the first portion of the remainder is recorded.

The next pulse at the output of the following splitter 20 reopens the first trigger 12. The process repeats, and the next portion of the remainder t is recorded in the third pulse counter 8. This is repeated until the product m-1 becomes equal to n m - the number of cycles. At tp, at the output of the third counter 8 of the impulses, a pulse appears that closes the fourth element I 26 as it passes, and one pulse of the reference generator t is equal to i / f,. This is equivalent to the fact that the pulse at the output of the follower divider 20 appears with a delay of 1 / f, equal to the passage time of one pulse, provided that the follower divider 20 always counts the same number of pulses of the reference generator Herbal K.

If the product is mt n, then at the moment when the third counter of 8 pulses counts the number of pulses equal to n, at its output. There is a pulse closing the fourth elec 23496312

Ment 26 is at the time equal to 1 / f, and the remainder of this cycle in this cycle, TG - - n, is recorded in the third counter of 8 pulses and is taken into account in the future. In the next accumulation cycle in the third counter, 8 pulses start with this new residue. By the end of the test period (equal to Tg), the third counter of 8 pulses is freeO

given completely.

At the output of the follower divider 20, output pulses are formed that are located distantly non-equidistantly. The distance between pulses in the output pulse sequence is n / fg and n + 1/4.

The next, third input impulse changes the state of the trigger 2 of the gate, the first element AND 23 opens and the measurement period starts again.

At the same time, the first AND element 23 of another channel is closed and the other channel performs the refinement (division) of the period of the input signal. The process is repeated. The correction found in the automatic divider as a result of comparing the durations of the two periods of the input pulse sequence is made at the beginning of the third period (measurement period) into the controlled divider 5 through the first And 23 element. In addition to this amendment, which belongs to the prototype,

controlled divider 5 introduces an additional amendment, taking into account the nonlinear law of variation of the divisible period in time and forming as the difference of indications at the outputs

the third register 19 of the first channel and the third register 19 of the second channel.

The indications of the third register 19 of each channel arrive at the information inputs of the sixth counter 11. pulses and are recorded into it with the aid of pulses from the input pulse sequence.

At the end of the work of the fifth counter 10 pulses of each channel, the inputs from the first element OR 37 receive signals from the output of the fifth counter 10 pulses of each channel. The signal from the output of the first element

OR 37 simultaneously triggers n - trigger 16 of each channel. When the fifth trigger 16 is triggered, a logical 13 appears at its direct output.

ka unit, which leads to the opening of the second input of the eighth element And 30 of each channel. Through the open eighth element I 30 in each channel, a delay of 1/2 of the period tj is delayed, the sequence of pulses of the reference generator 1 from the output of the line 3 delay post :, 11 pulses of each channel simultaneously drop to the sixth counter.

If the sixth counter of 11 pulses of the first and second channels (measured period grows) is unequal, the sixth counter of 11 pulses of the first channel with a lower recorded number reaches its zero value earlier. When the sixth counter reaches zero, 11 pulses of one of the channels triggers the fifth flip-flop 16 of this channel and closes the eighth element I 30 of the same channel with a pulse of zero logic from the direct output on the second input.

At the same time, the pulse of the logical unit from the inverting output of n - (of that trigger 16 of the same channel goes to the first input of the EXCLUSIVE OR element 33,

The sixth counter 11 pulses of another channel with a large recorded number continues to count and after some time t reaches its zero value. In this case, the fifth trigger 16 of this channel is triggered and closes with a pulse of logical zero from the direct output at the second input the eighth element AND 30 of the same channel. Simultaneously, the pulse of the logical unit from the inverting output of the fifth trigger 16 of the same channel goes to the second input of the element EXCLUSIVE OR 33 The impulses coming to the first and second inputs of the EXCLUSIVE OR 33 form at its output a stroke and a pulse of duration t, which through the inverter 34 opens the ninth element 35 at the second input the pulse sequence of the reference of the generator 1 from the output of the delay line 3, arriving at the first input of the ninth element I 35, from its output is fed to the first input of the second element SH.38. The number of these pulses is equal to t f. The second input of the second element OR 38 receives a pulse sequence from the output

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25 35 40, -5 () 55 9fi314

yes support gay-eratora 1. At the output of the second element OR 38, a pulse sequence is formed, enriched with a burst of pulses that have passed during time t, which simultaneously arrives at the first inputs of the first element 2I-2OR-NO 31 of each channel. The output of the first element 2I-2ILI- NOT 31 of each channel is connected to the first input of the first element AND 23, respectively, therefore the enriched pulse sequence. From the output of the first element 23 is recalculated by the controlled divider 5 taking into account the number of pulses in the formed burst over time t.

In the case of a smaller measured period, the sixth counter of the 11 pulses of the second channel with the lower recorded number reaches its zero value earlier. At the output of the EXCLUSIVE OR 33 element, a pulse of duration t is also formed, which goes to the second input of the tenth element AND 36. Together with the potential at the first input of the ninth element 36 AND and at its output, a mercury pulse of duration t with a potential of zero. This potential of logic zero is fed to the second input of the first element 2Н-2ИЛИ-НЕ 31 of each channel. Pa. In this case, a controlled sequence of pulses is fed to the controlled divider 5 from the reference generator 1, depleted in time t,

The proposed automatic follow divider allows to take into account the nonlinear law of change in time. The divisible period of the input sequence and form an additional correction introduced into the controlled divider and increasing the accuracy of the division. The additional amendment is formed from the difference between the indications at the outputs of the third registers, which is the difference between the differences of the previous and subsequent changing periods measured on the 1st and 11th channels. Formed. The addition of the additional amendment takes into account the presence of the second and higher derivatives in the law of variation of the dividend period. The division accuracy of the proposed automatic divider is 1.5–2 times higher than the division accuracy of the prototype device.

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Claims (1)

Invention Formula The automatic tracking period divider of the pulse signals containing a reference oscillator, the output of which is connected to the input of the delay line, a strobe trigger, an adder and two channels, each of which includes serially connected first pulse counter, first register and next divider, serially connected controlled divider, second register and second pulse counter, the output of the controlled divider is connected to the input of the first pulse counter, the third pulse counter, whose information inputs are soy dinenees with information inputs of a controlled divider, the first element I, the output of which is under the subtracting input of the controlled divider, the second and third elements AND, the first inputs of which are connected to the output of the reference generator, the outputs to the subtracting inputs of the second and third pulse counters, respectively, and the second inputs - to the output of the first trigger, the first input of which is connected to the output of the first trigger, the first input of which subcategories to the output of the second pulse counter, the second to the output of the next divider and to the input of the accumulator, h The fourth element is And, the first input of which is connected to the output of the reference generator, the second to the output of the third pulse counter, and the output to the subtractive input of the following divider, the fifth, sixth and seventh elements And, the second, third and fourth triggers the first and second element 2I-2ILI-KE, serially connected, the fourth pulse counter, the third register and the fifth pulse counter, the group of outputs of the fourth pulse counter is connected to the inputs of the q-organ, the output of the fifth pulse counter is connected to the R-input of the second trigger, S -input to second, connected to the input bus of the device, and direct output to the first input of the fifth element I, the second input of which is connected to the output of the delay line and the code to the subtractive input of the fifth pulse counter and the first input of the first element 2И-2ИЛИ-НЕ, output which is connected to the first input of the first element H, and the second input you j 0 5 ,, 0 five 0 five . 496316. to the direct output of the third trigger, the inverse output of which is connected to the first input of the sixth element And, the second input of which is connected to the first input of the fifth element And, and you -. move - with the third input of the first element And, the delay element, the input of which is connected to the control inputs of the first and second registers of this channel, and the output to the input of the third register of another channel, to the R-address of the fourth trigger of another channel, as well as the first input, the pulse counter of its channel, to the S inputs of the third and fourth flip-flops, the control input of the fourth pulse counter of its channel, the subtracting input of which is connected to the output of the seventh element I, and the summing input to the output of the second element 2I-2 SCH1I-NOT, in each channel the R-input of the third trigger is connected to the output of the zero-organ and to the counting input of the fourth trigger, the direct output of which is connected to the first input of the seventh element I, and the inverse output to the first input of the second element 2I -2OR-NOT, the second and third inputs of which are connected to the second input of the seventh I element and to the output of the reference generator, the first gate trigger output is connected to the input of the delay element and the third input of the seventh I element of the first channel, as well as the fourth input of the second element 2I -2 OR NOT and the second input of the first element And the second channel, and the second output - with the input of the delay element and the third input of the seventh element And the second channel, as well as the fourth input of the second element; that 2I-2OR-NOT and the second input of the first element And the first channel, differing in that, in order to increase the accuracy of division in a dynamic mode, in each. the fifth channel is entered by the fifth trigger, the sixth pulse counter, the eighth element I. the element EXCLUSIVE or the inverter, the ninth and tenth element AND, the first and second elements OR, and the R-input of the second trigger of each channel is connected to one of the inputs of the first element OR , R-input of the fifth trigger of each channel is connected to the output of the sixth pulse counter of its channel, S-BSHO to the output of the first element 1-ish, direct 7 1234963I a output - to the first input of the eighth trigger of the second channel and to the switch And, the second input of the tenth element And, a. connected to the output of the delay output line -.to the inverter input, the output koi to the first input of the ninth elementary is connected to the second inputs of deI, which triggers the input of the sixth counter in the same and tenth elements And, the output the pulses of each channel of the plug of that element AND are connected to the device input bus, the subtractive input of the second element OR, main input - to the output of the eighth element; the second input of which is connected to the output; information inputs - to the input of the reference generator, the third fbrmag ionic outputs of the third registrated entry of the first element 2H-2ILI-NOT pa, the first input element EXCLUSIVE each channel is connected to the output OR is connected to the inverse output of the second element OR the fourth trigger of the first channel, the second - to the output of the tenth element input - to the inverse output of n toto I.