SU1285460A1 - Information output device - Google Patents

Abstract

The invention relates to the field of devices capable of displaying various information, and can be used, in particular, for information about library applications executed. The purpose of the invention is to simplify the device. The information device contains the first and second display units, an encoder, a keyboard, a register, OR elements, a single pulse generator, AND elements, counters, decoders, a trigger, NOT elements, a clock generator, a pulse distributor, a ZI element, a random-access memory unit multiplexer. The first keyboard outputs through an encoder are connected to the inputs of the first OR element and the register, the outputs of which are connected to the inputs of the first display unit and the random access memory (RAM). When pressing the keys of the keyboard, the signal from the output of the first element OR starts the generator of a single pulse and the corresponding code is entered into a register. The register is controlled by a single pulse generator, the first counter, and decoders. In the write mode, the codes from the register are copied to the RAM cells. The operation of the device is synchronized from the pulse distributor, to which a signal is output from the clock generator. Outlets of RAM are connected to the inputs of the second display unit. Indication of numbers is carried out by sequential reading from RAM. The device provides for locking the display from RAM cells, in which there is zero information. For this, the output of the second element OR is connected to the outputs of the RAM, and in the case of zero information, the multiplexer connects the RAM counter to the signal of a higher frequency. 9 il. i (L Yu ac sd O5

Description

The invention relates to devices for displaying various information, and can be used for information about completed library orders.

The purpose of the invention is to simplify the device.

FIG. 1 shows a block diagram of an information device; in fig. 2 shows an example of the execution of the block diagram of the first display unit; in fig. 3 shows an example of a block diagram of a second display unit; in fig. 4 is a block diagram of an electronic key for controlling the display elements of the second display unit; in fig. 5 - diagram of the element ZI-OR; in fig. 6 - time diagram of the mode “Data entry; in fig. 7 is a temporary chart of the “Painting” mode; in fig. 8 - time diagram of the “Record; in fig. 9 - time diagram of the “Forced Recording.

The device (Fig. 1) contains a keyboard 1, an encoder 2, elements OR 3-5, element 6, generator 6 of a single pulse, elements 8 and 9, counter 10, decipher 11 and 12, register 13, display unit 14 , trigger 15, clock generator 16, pulse distributor 17, counter 18, element ZI-OR 19, counter 20, random-access memory unit 21 (RAM), display unit 22, elements OR 23 and 24, element NOT 25, elements AND 26 and 27, element OR 28, multiplexer 29, element OR 30.

FIG. 2 shows the inputs 31 and 32 of the first and second groups of the display unit 14, the binary code decoders 33 in the seven-segment, the resistor blocks 34, the seven-segment indicators 35, positive voltage 36.

The emitter followers 37, the electronic key block 38, the display element block 39 (FIG. 3) are also included in the circuit of the second display unit.

The structural circuit of the electronic key includes an input 40, resistors 41-43, a transistor 44, indication elements 45, a positive voltage bus 46 (Fig. 4).

FIG. 5 shows the first 47, the second 48, the third 49, the fourth 50, the fifth 51 and the sixth 52 inputs, the element ZI-OR 53, exit 54.

FIG. 6 shows time diagrams at the outputs: keyboard groups 1 - position 55, generator 16 - position 56, distributor 17 pulses - positions 57 and 58, element 9 - position 59, counter 10 - position 60 in the mode “Data entry; in fig. 7 - time diagrams at the outputs: the third keyboard 1 - position 61, element ZI-OR 19 - position 62, multiplexer 29 - position 63, counter 20 - position 64 in the mode “Painting; in fig. 8 - time diagrams at the outputs: first keyboard 1 - position 65, element 8;

position 66, trigger 15 - position 67, element AND 26 - position 68, counter 20 - position 69, element NE 25 - position 70, multiplexer 29 - position 71 in mode

“Record; in fig. 9 - time diagrams at the outputs: second keyboard 1 - position 72, element OR 28 - position 73, multiplexer 29 - position 74, trigger 15 - position 75 in the Forced Recording.

Let us consider the use of an information device to notify library readers about the fulfillment of their orders for books delivered from a book depository.

The device works as follows.

The following main modes of operation of the information device are possible: “Data entry,“ Painting, “Recording,“ Indication and “Forced recording.

Mode “Data entry. The number of the completed order is dialed on the keyboard 1 using the keys O-9. When you press any of the keys O-9 at the outputs of the keyboard group 1, the logical "1 appears, the encoder 2 generates the corresponding binary code. At the same time, a logical ' 1 signal appears at the output of the element OR 3, which through the element OR 4 is fed to the start input of the generator 7 of a single pulse. Since the first and second keyboard outputs are logical “Oh, then this

the same level at the output of the element OR 5, and at the output of the element NOT 6 - the logical "1. The generator 16 clock pulses produces pulses 56, in which the distributor 17 pulses produces pulses 57 and 58, shifted in time. A single pulse generator 7 generates a single pulse 57 according to a clock signal, and since the output of the element is NOT 6 logical "1, then the signal 59 appears at the output of AND 9. This signal goes to the counting input of counter 10 and the gate input of the decoder 11. By the falling edge of the signal 59 is adding -fl to counter 10 (position 60). The outputs of the counter 10 control the inputs of the decoders 11 and 12, i.e., which of the outputs of the decoder is determined by the logical ' 1 signal. From the first output of the decoder L, the signal arrives at the first control input of the register 13 and the code indicated by the display unit 14 is entered from the encoder 2 into it. Register 13 consists of four-bit sections. Therefore, each time the O-9 keys of the keyboard 1 are pressed, the corresponding codes in the register section 13 will be entered alternately. Thus, the order code is entered. The outputs of the decoder 12 are connected to the second

the inputs of the display unit 14 and control the display of the comma on the seven-segment indicators. This allows individing a section of register 13 into which when pressed

O-9 keys enter the corresponding code.

In more detail, the display unit 14 is shown in FIG. 2. The code from register 13 is fed to the first inputs of the 31 block and then to the decoders 33 of the binary code to the seven-segment one. The resistors of the blocks 34 set the current through the segments of seven-segment indicators 35, the outputs of which are connected to the positive voltage bus. The second inputs of the 32 blocks are connected via resistors of the block 34 to the comma of seven-segment indicators 35. In the keyboard 1 it is necessary to use the keys with chatter suppression.

Mode “Painting. When you press a key of this mode, the logical key 1 appears at the third keyboard 1 exit, and the entire array of the RAM block 21 is painted with the code dialed on register 13. This happens as follows. A logical signal "1 (position 61) is fed to the sixth input 52 of the ZI-OR element 19, the first input 47 of which receives pulses 57 from the distributor 17 pulses, therefore, at the output of the ZI-OR element, there appear pulses 62, on which counter mode 20 (position 64). At the same time, the signal 61 is fed to the input of the AND 26 element and through the OR 30 element to the control input of the multiplexer 29. The pulses 58 arrive at the input of the AND 26 element and then through the OR 28 element to the second input of the multiplexer 29. Since its control output is logical "1, then pulses 63 appear at the output of the multiplexer 29, which are used to write to the cells of the RAM 21. The key of this mode is kept pressed until the code is written to all the cells of block 21. This is determined by the frequency of the generator 16. When typing a zero code on register 13, the block 21 is reset.

Record mode. The code typed in register 13 is written into block 21 as follows. Let the array of block 21 itself be painted with a non-zero code, with the exception of a few cells. Pressing the Record key produces a logical "1 (position 65)" signal at the second output of the keyboard 1. This signal through the elements OR 5 and 4 starts the generator 7 of a single pulse. In this case, the output of the element NOT 6 is a logical "O, so the signal at the output of the element And 9 is not generated. At the inputs of the element And 8, a coincidence occurs and a signal 66 is generated at the pro output, which sets the trigger 15 (position 67) to b. The output of the trigger 15 is connected to the input of the OR element 24, the logic "1 from which is fed to the fifth input 51 of the ZI-OR element 19, and the second input 48 of this element is pulsed 58, therefore, its output produces pulses 68 and the counter 20 starts

work in counting mode (item 69). When the RAM 21 counts the zero information, the logical element b appears at the output of the NOT 25 element (position 70), 5 coincidence occurs at the outputs of the And 27 element, and the signal 71 from the output of the multiplexer 29 records into the RAM cell 21 and on the falling edge resetting the trigger 15. In this way, in the “Record” mode, an automatic search for a cell with zero information and the recording of a code from register 13 to this cell is performed.

Mode "Indication. This mode is the main operating mode. Pulses from the output of counter 18, which works in

- the frequency divider mode goes to the third input 49 of the ZI-OR element 19, the fourth input 50 of which receives the signal from the output of the element OR 23. In the case of non-zero information from the output of the RAM 21, the addition of "+ 1 to the counter 20 occurs via a signal from the counter 18, i.e., relatively slowly. In all modes, the logical unit level is fed to the input of the RAM 21 sample, i.e. the RAM 21 operates as a code converter. The duration of the signal at the outputs of RAM 21 is equal to the duration of the younger

bit counter 20. This makes it possible to perceive information from the RAM 21 visually in the display unit 22, and in the case of zero information - logical “1 at the output of the element NOT 25 - through the element

0 OR 23 the signal arrives at the fifth input 51 of the ZI-OR element 19 and the counter 20 starts to operate in an accelerated mode. This makes it possible not to obstruct the display unit 22 with zero information, i.e., bypassing the "empty zones." It should be noted that in the mode

"The search for a cell with zero information is also recorded at an accelerated rate.

During operation of the display unit 22, information from the outputs of the RAM 21 is fed to the inputs of the decoders 33, the outputs of which through the resistors 34 control seven-segment

indicators 35. The outputs of the decoders 33 through the emitter followers 37 are controlled by means of an electronic key block 38 by a block 39 of display elements. Structurally, the electronic key block 38 and the display element block 39 are made in the form of a separate remote display, which can be located at a considerable distance from the information device. The low impedance output of the emitter followers 37 allows the board to be removed from blocks 38 and 39 on

0 significant distance from information device.

FIG. 4 shows a block diagram of the electronic key of the block 38 for controlling the display elements of the block 39. From the output of the emitter follower 37, the signal is fed to input 40 and through resistor 41 to the base of transistor 44. In the initial state, transistor 44 is locked and the voltage on the collector is set by divider resistors 42 and 43. Display elements 45 (neon lamps) are hot while. Resistors connected in series with elements 45 set the current through display elements 45.

From several of these elements 45, one segment is formed. When a logical "1" signal arrives at the base of transistor 44, the transistor opens and the voltage across its collector decreases sharply, the display elements 45 go out. T. o. for the correct operation of the display elements, the decoders 33 must provide information in the reverse code, and the seven-segment indicators 35 must be with one anode. Building a block of 39 display elements on neon lamps ensures good brightness and low consumption of mosh.

Forced Recording mode. It is used to record information from register 13 into a cell of RAM 21 with non-zero information. When you press the corresponding key on keyboard 1, a logical signal "1 (position 72)" appears at its third output. A coincidence occurs at the inputs of the AND 8 element and the signal from the output of the OR 28 element (position 73) is fed to the second input of the multiplexer 29. Since its control input is logical "1, then the signal 74 is output at the output of the multiplexer 29. the cell of RAM 21 and resetting the trigger 15. This mode is used when the order for the book is completed, the reader of the book is taken and it is necessary to change the information in the corresponding cell of RAM 21.

The device is simple in its design, has a wide functionality. The developed design uses 42 K 155 series microcircuits and six K 514 ID2 microcircuits. The RAM size is 12, the capacity is 16. It is possible to display 16 three-digit numbers. Frequency generator 16 clock pulses 256 Hz. The counter's size is 18–8, i.e., in the display mode, the information device displays each number for 2 s, since from the distributor 17 pulses the pulses 58 to the counter 18 arrive already with a frequency of 128 Hz. The display panel is located about 30 m from the information device. The capacity of RAM 21 can be increased, which is not necessary, since practice shows that in the middle libraries never more than 16 order numbers are processed.

Claims (1)

Invention Formula A device for outputting information comprising a first display unit, an encoder and a keyboard, the outputs of the group of which are connected to the outputs of the encoder, characterized in that, in order to simplify the set It contains a register, first, second, third, fourth, fifth, sixth and seventh elements OR, generator of a single pulse, first, second, third and fourth elements AND, first, second and third counters, first and second decoders, trigger , first and second elements NOT, clock generator, pulse distributor, ZI-OR element, random-access memory unit, second display unit, 0 multiplexer, the keyboard group outputs are connected to the inputs of the first OR element, the output of which is connected to the first input of the second OR element, the second input of which is connected to the output of the third OR element, the first input of the first AND element and the input of the first element NOT, the output of which is connected to the first input The second element And, the second input of which is connected to the second input of the first element And and the output of the generator of a single pulse, the input 0 start which is connected to the output of the second element OR, the synchronization input of the generator of a single pulse is connected to the first input of the element ZI-OR and the first output of the pulse distributor, whose input is connected to the output of the clock generator, the second output is connected to the first inputs of the third and fourth elements And, the second input of the ZI-OR element and the counting input of the first counter, the output of which is connected to the third input of the ZI-OR element, the output of which is connected to the counting input of the second counter, the outputs of which with the address inputs of the RAM, the outputs of which are connected to the inputs of the second display unit and the inputs of the fourth element OR, the output of which is connected to the input of the second element NOT and the fourth input of the element ZI-OR, the output of the fifth element OR is connected to the fifth input of the element ZI-OR, the first input of the fifth element OR is connected to the second input of the fourth element AND and 0 trigger output whose installation input is connected to the output of the first element AND and the first input of the sixth element OR, the second input of which is connected to the output of the third element AND, the output is connected to the second input of the multiplexer, the first input of which is connected to the output of the fourth element And, the output of the multiplexer is connected with the input of the trigger entry and the input of the recording of the RAM block, the information inputs of which are connected to the inputs of the first group of the second display unit and the outputs of the register, the information inputs of which are connected with the outputs of the encoder, and the control inputs of the register with the outputs of the first decoder, the control inputs of which are connected to the control inputs of the second 5 of the decoder and the outputs of the third counter, the counting input of which is connected to the strobe input of the decoder and the output of the second element And, the outputs of the second decoder 0 five 0 the torch is connected to the inputs of the second group of the first display unit, the first keyboard output is connected to the first input of the third OR element, the second keyboard output is connected to the second input of the third OR element and the first input of the seventh OR element, the third keyboard output is connected with the sixth input of the ZI-OR element, the second inputs of the third element AND and the seventh element OR, the output of which is connected to the control input of the multiplexer, the output of the second element is NOT connected to the third input of the fourth element AND and the second input of the fifth OR element. Fial 33 3t 35 31 33 3f 35 33 3tt 35 32 X 0 FIG. 2 Fig.Z g 7 hell w 5