SU1277379A1 - Polyfunctional logic element - Google Patents

Abstract

This invention relates to the field of computing. It can be used when building combinatorial logic nodes of digital equipment. The purpose of the invention is to expand the functionality by forming in parallel two types of logical functions of two variables. In order to achieve this goal, inverters 8, 9, 11 are introduced into the device. In addition, the device contains transistors 3, 10 and inverters 2, 5, 12. 1 Il.

Description

P1

with

H

CO 1. The invention relates to a pulse technique and can be used in the construction of combinational logical nodes of digital equipment. The purpose of the invention is to expand the functional possibilities by forming in parallel five logic functions of two variables. In the drawing, an electrical schematic diagram of the multifunctional logic element is shown. The device comprises a first input bus 1 connected to the input of the first inverter 2 and a gate of the transistor 3, a second input bus 4 connected to the input of the second inverter 5, the source of the p-transistor of which is connected to the common bus 6 , the power supply bus 7, the second input bus 4 is connected to the input of the third and fourth inverters 8 and 9, the first input bus 1 is connected to the gate of the p-transistor 10, the source of which is connected to the power bus 7, and the drain to the output m of the third inverter 8, the input of the fifth inverter 11 and the source of the resistor of the sixth inverter 12, the output of which is connected to the source of the p-transistor of the fourth resistor of the fourth inverter 9, the output of the fifth inverter 11 is connected to the source of the first transistor of the fourth inverter 9, the output of which connected to the output of the first inverter 2 and the sources of the p-transistor and p-transistor, respectively, of the third and second inverters 8 and 5, the output of the second inverter 5 is connected to the input of the sixth inverter 12, the drain of the p-transistor 3 and the source of the p-transistor of the fifth inverter 11, source n-transistor and 3 and the source of the p-transistor of the sixth inverter 12 are connected to the common bus 6, the sources of the p-transistors of the third and fifth inverters 8 and 11 are connected to the power bus 7, the outputs of the sixth inverter 12, the fifth inverter 11, the third inverter 8, the second inverter 5 and the first inverter 2 are respectively outputs 13 through 17, respectively. The table shows the state of all internal and external circuit nodes on all possible sets of input variables, as well as the state of transistors 3 and 10 (H - open, - closed).

From the table it follows that the scheme works in accordance with the equations:

Y1 X1-X2 h-XI X2 Y2 XI © X2;

Y2 XI X2 + XI-X2 Y1 XI-X2;

Y3 XIX2 XI + X2 E X1 / X2,

Y4 XI + X2 X1 X2 XP X2;

Y5 xi.

Thus, on an arbitrary input data set, the circuit simultaneously calculates five logical functions.

Claims (1)

Invention Formula Multifunctional logic element containing the first input the bus connected to the input of the first inverter and the gate of the p-transistor, the second input bus connected to the input of the second inverter, the source of which transistor is connected to the common bus, power supply, characterized in that, in order to extend the functionality, the second input bus is connected to the input of the third and fourth inverters, the first input bus is connected to the gate of the p-transistor, and the drain to the output of the third inverter, the input of the fifth inverter and the source of the p-transistor of the sixth inverter, whose output is connected to the source of pn anzistora fourth inverter, the output of the fifth inverter coupled to the source of the p-transistor of the fourth inverter, the output of which is connected to the output of the first inverter and the sources of the p-transistor and p-transistor, respectively, of the third and second inverters, the output of the second inverter is connected to the input of the sixth inverter, the drain of the p-transistor and the source of the transistor of the fifth inverter, source The p-transistor of the sixth inverter is connected to a common bus, the sources of the p-transistor of the third and fifth inverter are connected to the power bus, the sources of the p-transistor and the p-transistor are connected respectively to the power bus and the common bus or connected together and with the output of the first inverter.