SU1275521A1 - Device for displaying information on screen of cathode-ray tube - Google Patents

Abstract

The invention relates to computing technology, namely, information and training devices based on microprocessors and microcomputers, and can be used to display static and dynamic information, including alphanumeric, graphic, and arbitrary characters. The purpose of the invention is to simplify the device by reducing the volume of the memory block — by introducing a third, fourth, and fifth resistors, switches, an adder, a second interface block, a decoder, and a third counter. 4 il. s

Description

You vj

ate

The invention relates to computing technology, namely, information-training devices based on microprocessors and microcomputers, and can be used to display static and dynamic information, including alphanumeric, graphic and arbitrary character. Devices are known for displaying information on the screen of a cathode ray tube lj. However, these devices are intended only for displaying static information and when using them to display arbitrary dynamic objects, the amount of memory equipment and control circuits increases significantly. I The closest to the invention to the technical essence is a device that contains arrays of RAM storing information about the desired position of objects by coordinates X and Y, RAM, which contains the addresses of objects in the ROM, the scale and color of objects, the ROM, which stores information about the contents of objects o, the first and second counters fixing the position of the beam on the screen, respectively, on the Y and X coordinates, the first and second registers of the required location of objects on the Y and X coordinates, respectively, the first and second patterns of comparing the position of the electron beam with the required location of objects, respectively, on Y coordinates and X and video adder. The known device provides the simultaneous display of a large number of objects anywhere on the screen of the cathode ray tube. Comparison schemes compare the contents of digital counters that fix the position of the beam on the screen and the desired location of the object. In the case of a match from the RAM array characterizing the type of object, the modified address of the object in the ROM, its color and scale are selected. In the ROM, each object is characterized by nine-fold words; the eight bits of each word define the object string, and the nine bits are used to signal the end of the sample of object 2j. A disadvantage of the known devices is that as the number of displayed objects increases, the amount of equipment (storage space) directly proportional increases, since for each displayed object the coordinates X and Y and its address in the ROM must be written into RAM. The purpose of the invention is to simplify the device by reducing the size of the memory block. A device for displaying information on the screen of a cathode ray tube containing the first interface block, the output of which is connected to the information bus of the memory block, the first counter and the first register, the second counter and the second register, the outputs of which are connected to the inputs of the first and second comparison circuits, respectively And the video adder also contains the third, fourth and fifth registers, the first and second switches, the adder, the second gateway block, the decoder and the third counter, the first input of which is connected to the output of the first circuit compared to and the second input is connected to the first input of the first counter, the first inputs of the fifth register and the decoder, the second input of which is connected to the output of the fifth register, the third input of the decoder is connected to the first input of the video adder and the first input of the second counter, the second input of which is connected to the second input the first counter, the outputs of a third of its counter and the decoder are connected to the first and second inputs of the first switch, the output of which is connected to the address bus of the memory block, the information bus of which is connected to the second block of the same The output of which is connected to the inputs of the first, second, third, fourth and fifth registers and the second input of the multivibrator, the third input of which is connected to the third input of the first switch, the first input of the second gateway and the output of the second switch, the first input of which is connected to the output the third register, and the second with the first output of the fourth register, the second output of which is connected to the fourth input of the first switch and the input of the adder, the output of which is connected to the second input of the second interface block, the output Torah comparison circuits connected to the fourth input videosummatora. FIG. 1 shows a block diagram of a device for displaying information on the screen of a cathode ray tube; in fig. 2 is a block diagram of a video adder; in fig. 3 block diagram of the decryption node; in fig. 4 - a symbol on the TV screen. The device contains RAM 1, which combines tables 2-7: table 2 coordinates Y in RAM, table 3 coordinates X in 033, table 4 Placement in RAM, table 5 Frame in RAM, table 6 Output to RAM and table 7 Symbols in RAM, counter 8, counting input 9 of counter 8, device input 10, register 11, counter 12, device inputs 13 and 14, register 15, comparison circuits 16 and 17, register 18, decoder 19, counter 20, address switch 21 , the input 22 of the address switch 21 for accessing the RAM by the microprocessor, the inputs 23-28 of the address switch 21, the register 29 consisting of the bits 30 of the initial information character color, bit 31 of the initial information about the scale of the character, bit 32 of the initial information about the character number, register 33, consisting of the bits 34 of the current information about the color of the character, bit 35 of the current information about the scale of the character, bit 36 current information on the character number, bits 37 of the current information on the line number of the character, the address and information switch 38, the input 39 of the address information switch for transmitting zeros, the input 40 of the address information switch for transmitting information from the register 29, the input 41 of address information switch for transmitting information from bits 34-36 of register 33, internal address information bus 42, adder 43, internal information bus 44, interface block 45, external information bus 46, interface block 47, video accumulator 48, device input 49 , external address bus 50, registers 5154, switch 55, group of elements OR 56, group of elements AND 57, register 58, switch 59, counter 60, register 61 and decoder 62. Device (FIG. 1) consists of RAM 1, whose tables (2-7) are necessary for organizing the display of information on the TV screen. 5214 counter 8 television lines, register 11 lines, counter 12 positions of the beam moving along the television line, register 15, circuit 16 comparing the current and desired position of the X coordinate (position) circuit 17 comparing the current and required position of the coordinate Y (line) register 18 receiving information from table 4, the decoder 19 sign of the presence of a character at a given point of the screen, providing a search for non-zero bits on register 18 and the formation of a binary code of the number of these bits to access in tables 3, 5 and 6 in RAM 1, counter 20 address and for addressing tables 2, 4 and 5, address KONMyTaTopa 21, which generates addresses for accessing RAM 1, register 29, receiving information from table 5, register 33, receiving information from table 6, address information switch 38, connecting to the bus 42 inputs 39.40 or 41, an adder 43, which provides an increase in the input information code by 1, an interface block 45, providing information transfer to RAM 1 during recording and transmission of information to the bus 44 when reading from RAM 1, an interface block 47, providing information transfer in the RAM 1 with s 46, 48 videosummatora forming the image signal output device 49. The reset inputs of counters 8 and 20, a serial input register 18 and one of the successive inputs of decoder 19 are connected to an input device 10, which is connected to the output of television frame scan sync block. The counting input of the counter 12, the second serial input of the decoder 19 and one of the serial inputs of the video adder 48 is connected to the input 13 of the device, which is connected to the output of the clock clock frequency 5.5 MHz of the synchronization unit. The reset input of the counter 12 and the counting input 9 of the counter 8 are connected to the input 14 of the device, which is connected to the output of the television line scan of the synchronization unit. The first input of the comparison circuit 17 is connected to the parallel output of the counter 8, the second input of the comparison circuit 17 is connected to the parallel output of the register 11. The output of the circuit

17 the comparison is connected to the counting input of the counter 20, the first input of the comparison circuit 16 is connected to the parallel code of the counter 12, the second input of the comparison circuit 16 is connected to the parallel output of the register 15, and the output of the comparison circuit 16 is fed to the second serial input of the totalizer 48. The parallel output of the counter 20 connected to the inputs 23 25 of the address switch 21, the parallel output of the register 18 is fed to the input of the decoder 19, the output of which is connected to the inputs 25 - 27 of the address switch 21. The parallel output of the register 29 is connected to the input 40 address information switch 38, the parallel outputs 34 36 of the register 33 to the input 41 of the address information switch 38, the input 39 of the address information switch 38 to the earth bus. The output 37 of the register 33 is connected to the input 28 of the address switch 2t and to the input of the node of modification 43, the output of which is connected to the input of the interface device 45. The external address bus 50 is connected to the input 22 of the address switch 21, the output of which is connected to the address bus of RAM 1, whose information bus is connected to interface devices 45 and 47. External information pAHNA 46 is connected to interface 47, internal information bus 44 connects the output of interface 45, to inputs of registers 11, 15, 18, 29 and 33 and the first parallel input of video adder 48. Internal address information bus 42 connects output address information switch 38 with the input of the interface device 45, the second parallel input of the video accumulator 48 and the input of the address switch 21. The code of the device 49 is connected to the TV.

Counters 8, 12, 20, and 60, registers 11, 15, 18, 29, 33, 51–54, 58, and 61, switches 21, 38, 55, and 59, and decoder 62 are common devices of computing technology and can be any from known standard methods. Their size corresponds to the size of information. The adder 43 can be performed, for example, in the form of a conventional adder. Blocks 45 and 47 mates

performed on chips that are parallel bidirectional-; signal generators for controlling the backbones (buses) in digital computing devices and are 4-channel switches having one bus for receiving information on each channel, one bus for only and one bi-directional bus for receiving and issuing.

Video adder 48 (FIG. 2) contains a register 51 for receiving and transmitting information in a parallel code, a shift register 52 for receiving information in a parallel code and transmitting this information in a serial code, a register 53 for storing background color information for the screen, a register 54 for storing information about the color of the symbol currently displayed on the TV screen and the switch 55. This switch connects output 49 depending on the code at the output of register 52 or to the output of register 53 or register 54. The input of register 54 is connected to the address information second bus 42, and input registers 51 and 53 connected to the data bus 44 ±.

The decoder 19 (FIG. 3) contains a register 58 for receiving and transmitting information in a parallel code, a group of information elements OR 56 from a register 18 and information from an output of register 58, a group of elements And 57, a switch 59 having a number of directions of information transmission equal to register bits 58, counter 60, providing a serial connection of the output of the switch 59 to each register bit 58, a register 61 for receiving and transmitting information in a parallel code, and a decoder 62.

The device works as follows

Suppose that the image of a symbol is necessary on the TV screen (Fig. 4). We assume, for example, that the screen decomposition format is 256x x256, the size of the decomposition elements is 16x16. The symbol can be painted in 7 colors (3 bits) and can be scaled 2 or 4 times (2 bits). For simplicity, let us assume that a black-and-white unscaled symbol is displayed on the television screen. Then on the address bus not 50 and the information bus 46, the processor through the block 47 of the interface writes the following information into RAM 1: in table 2, in the 1st cell the code 0000 in table 3, in the 1st cell to 0000 0010 ,; in table 4, in the 1st whose code CODE 0001 | g; to table 5, to the cell with the corresponding address, code 000 0000 to table 6 - for all bits of zeros; in table 7, the code corresponding to the structure in the 16x16 matrix. Tables 2 and 3 are ordered in ascending order of binary binary codes of coordinates of the C & V symbol nodes, respectively. The symbol node is the upper left corner of the matrix of the decomposition elements of the symbol. Tables 4. and 5 store information about the placement of image objects in this frame. At the same time, each intersection of the coordinates of the nodes of the X and Y symbols on the screen (each pair Xj yj) corresponds to one bit in Table 4 and one cell in Table 5. If a symbol starts at the intersection of coordinates (the symbol node coincides with the pair x; y), then in the corresponding cell of table 4 there should be 1 indicating the presence of a symbol, and the corresponding cell of table 5 should contain information on the number of the symbol (the address of the beginning of the symbol in table 7), its color and scale. The absence of a character in this intersection of coordinates is recorded by the presence of zero in the corresponding cell width of table 4 and zero information in the cell of table 5. From the above it is clear that the information on the presence of characters on this coordinate Y is stored in one cell of table 4. symbol for reference to table 7, which includes the symbol line number, color, and scale. The data recorded in Table 6 is necessary for organizing the line-by-line character output on the television screen. By the beginning of the forward stroke of a television frame sweep, the initial state of the counters is zero, since counters 8 and 20 are zeroed by the reverse stroke of the television frame, and counter 12 by the reverse stroke of the television line. At the beginning of the forward frame stroke, a signal is generated to access table 2 via input 23 of the address switch 21 and address 0000, which is equal to the state of counter 20, to register 11 via the information bus 44 from RAM 1 receives the OOOOOOIIj code defining the television line, which begins: symbol output. Up to this line, i.e. on the zero, first and second television lines, there should be no image. In this case, the register 18 contains zero information, since the register 18 is zeroed by the reverse frame sweep. Then the decoder 19 provides for the prohibition of the operation of the device until the end of the second television line. On the reverse run of the third television line, counter 8 is set to state 0000 0011. Equality of the codes on counter 8 and register 11 triggers the comparison circuit 17, the signal from which forms a reference to table 4 via input 24 of the address switch 21 and at address 0000, equal to the state of the counter 20, the register 000 reads the code 0001, 5. After that, the information from register 18 is added by OR with the information coming from the output of register 58, and is transmitted to the input of register 58 unchanged, since the decoder 62 is turned off and all its outputs have a Log level. 1. Then the register 581 writes the code 0001 (g. In this case, the counter 60 remains in the same state as before the beginning of the operation of the decoder 19 (i.e. in the OOOOj state), since the appearance at the output of the switch 59 The log t inhibits the entry of counter 60. After that, the code from counter 60 is recorded and the 5-clock series of setting pulses is started.The 5-clock series is generated by the horizontal horizontal retraction time and by the signal from the comparison circuit 16, but only in the absence of the code 1111. on the counter 60. In the first cycle at the address register 61 (OOOO), a call is made to table 3 through the course 26 of the address switch 21, and register 15 receives the code 0000 0010, the information 44.

The second clock on register 29 from table 5 receives a code containing bits of color 30 of scale 31 and ci MBona 32 numbers. In the third cycle, table 6 is called and register 33 is written to all bits zero, since up to this point none the object is not displayed on the screen. In the fourth cycle, table 7 is accessed via the input 28 of the address switch 21 at 00 0100 0000, formed in two parts. The first part of the address (six most significant bits) comes from register 29. In this case, the addressable information switchboard ZV is turned on to input 40 with a zero code on the registerZD. The second part of the address (four least significant bits) comes from bits 37 of register 33 and is equal to the bottom code of the line number of the character 0000. At the end of the fourth clock cycle, the video accumulator 48 posts the zero line of the output character. At the fifth cycle the binary number of the character (OOlOOg) is written. in the old digits of the cell of table 6, the four lower digits of the same cell records the OOOIg code corresponding to the incremented line number of the object and coming from the adder 43. At this, preparation for outputting the string of this character is completed.

Simultaneously with the launch of the 5-clock series of products: the decoder 19 is working, but since the remaining bits on register 58 are zero,

the counter 60, having counted to 1111, prohibits the launch of the 5 - cycle series on this television line. During the direct, course of the third television

. the lines according to the signal from the comparison circuit 16, which C1 # abats with equality of codes (OOQO 0010) on counter 12 and register 15, occurs synchronously with the frequency of the clock pulses, the code of the zero line of the symbol is extended to the TV screen. At the beginning of the reverse run of the fourth television line occurs, the reset of the circuit from the comparison circuit 17, according to which the counter 20 is transferred to the next state. Then the next 5 clock series is launched.

In the first cycle, the operation of the circuit is repeated as before, In the second

tact due to a change in the state of counter 20 to register 29 is read from another cell of table 5 of the null information. In the third cycle to register 33, information about the symbol with an incremented string is read from the corresponding cell of table 6 where this information was recorded in the previous 5-cycle series. The presence of non-zero information on the register 33 ensures the connection of the address-information switch 38 to the input 41. Then, in the fourth clock cycle, the call to table 7 occurs at the address coming from register 33, which provides the return of the long character after the next line to table 7 and read. its on video adder 48, In the fifth tact, information is recorded from the register of 33 in the same cell of table 6 as before, and in the younger four digits, the code of the incremented character string is written. The extension of the first character line to the TV screen is similar to the zero one. The operation of the decoding node 19 is carried out in the same way for each television line. The output of the remaining 14 lines of this character is similar. In preparation for the conclusion of the last character string during the 5th cycle, the address information switch 38 is connected to the input 39, which ensures that the symbol information with the incremented string with zero information was previously stored in table 6. In this case, the decoder is inserted 62 and the register 58 is entered through the circuits 56 and 57 of the information from the outputs of the register 58, but O is written instead of 1, thus stopping the display of the rows of this symbol on the TV screen. Further operation of the device is similar to its operation for zero and first television lines. To organize the movement of this symbol on the screen, it is necessary to program the microprocessor to change the coordinate codes Y and X in the corresponding cells of Tables 2 and 3,

Claims (1)

Example, To organize the display of 256 objects in the case of using the proposed device, the following amount of memory is needed; 16x8 128 bits - storage array of coordinates X; 16x8 128 bits - storage array of Y coordinates; 16x16 256 bits - an array of storing the current information about the address of the object in the ROM, color, scale and number of the output line of the object; 16x16 256 bit - storage array of the prize of the presence of an object at a given point on the screen; , 256x12 3072 bits - an array of storing information about the address of an object in ROM; color and scale of the object. The volume of the storage array of information about the content of each object depends on the number of different objects and in the case of using the proposed or known devices will be the same, so the volume of this array can be ignored. Thus, to organize the display of 256 objects in the case of using the proposed device, the required memory capacity is 3840 bits. In the case of using the known device, the following memory space is required to output the same 256 objects: 256x8 2048 bits - X coordinate storage array; 256x8 2048 bits - Y coordinate storage array; 256x12 3072 bits - an array of storing information about an object's address s ROM, color, and scale of an object. Thus, without taking into account the volume of the ROM, the memory size is 7168 bits, which is twice as large as the memory in case of using the proposed device. As the number of objects displayed increases, the difference in memory volumes increases. Along with this technical effect, the use of the invention provides a significant economic effect. For a preliminary assessment of the latter only in particular applications, for example, in reprogrammable TV games, it can be assumed that with eight-color coloring of dynamic objects and a total screen resolution of 256x256 decomposition elements for a bit display, 192 K565RU2 memory microcircuits (1K bit capacity) or 32 K565RUZ memory microcircuits (16K bits capacity), using the proposed device requires only 16 microns K565RU2 memory circuits. Apparatus of the Invention A device for displaying information on a cathode-ray tube screen comprising a first interface block whose output is connected to the information bus of the memory block, a first counter and a first register, a second counter and a second register whose outputs are connected to the inputs of the first and second comparison circuits, respectively, and a video adder, which is tacted by the fact that, in order to simplify the device by reducing the volume of the memory block, it contains the third, fourth and fifth registers, the first and second switches, the adder, - the second interface block, the decoder and the third counter, the first input of which is connected to the output of the first comparison circuit, the second input is connected to the first input of the first counter, the first inputs of the n tgc register and the decoder, the second input of which is connected to the output of the fifth register, the third input of the decoder connected to the first input of the video adder and the first input of the second counter, the second input of which is connected to the second input of the first counter, the outputs of the third counter and the decoder are connected to the first and second inputs of the first switch, the output which is connected to the address bus of the memory unit, the information bus of which is connected to the second interface unit, the output of which is connected to the inputs of the first, second, third, fourth and fifth registers and the second input of the video card. connected to the third input of the first switch, the first input of the second interface block and the output of the second switch, the first input of which is connected to the output of the third register, and the second to the first output of the fourth register, the second output of which is connected to the fourth input of the first switch and the input of the adder, the output of which is connected to the second input of the second interface unit, the output of the second comparison circuit is connected to the fourth input of the video accumulator. (Pue. 3 (Sniffing)