SU1275414A1 - Information input-output device - Google Patents

Abstract

The invention relates to computing technology, in particular to input / output devices of information of digital computing control machines operating in real time. The aim of the invention is to increase the reliability of input / output information. The goal is achieved by introducing into the device a receiving register, a block of majority elements and a group of logic elements ensuring their interconnection. At the same time, increasing the reliability of input / output information is provided due to the possibility of information shift in case of failure of one or several information buses defined by software testing and major (L ti output information. 5 ill.

Description

The invention relates to computing and can be used for input-output information in digital computing control machines operating in real time. .

The purpose of the invention is to increase the reliability of the device by providing undistorted information and correct addressing of information in case of failure of one or several lines of the information bus.

FIG. 1 shows a functional diagram of an information input / output device, FIG. 2 shows the implementation of the majority element block and its connection to the information bus; in FIG. 3 is a diagram of signals characterizing the operation of the device when entering information into a digital computer (DVM); FIG. 4 is a time diagram of a signal when the device is operated for information output; FIG. 5 - the slave algorithm of the device when entering information JB DVR.

The device (Fig. 1) contains a multiplexer 1, a reception register 2, a transceiver 3, a third element FJffl 4, an input address register 5, a block of 6 majority elements, an output address register 7, a memory block 8, information, bus 9, the first 10, the second 11 and third 12 control inputs, the fourth 13 and fifth 14 control inputs, the first 15 and second 16 elements OR, the command register 17, the group of elements OR 18., information inputs 19, information outputs 20 and the exchange channel with the digital computer 21 The block 8 of Memory includes registers 22 and triggers 23.

Block 6 (Fig. 2) contains majority elements 24, In addition, groups of lines 25 are indicated, along which the information input address and information output address (K groups) are given, bit 26 of the information input address and information output address, line (bit ) 27 information bus 9, generated information input and information output address 28, bit 29 of the generated information input or output address, N is the information bus width 9, m the address width of the information input or information output

devices, K is the number of groups of information bus lines 9, to which an address is given (square brackets indicate the whole part of the number).

FIG. 5 p - the number of additional lines of the information bus 9 failed. The timing diagrams of the signals at the control inputs of the device 10-12 both with the input and with the output of information by correspondence

the time diagram of the unified microcomputer interface Electronics-60,

In addition to the signals at inputs 10-12, using the command register 17, which is recorded on the front 1/0 at the first input 10, and the elements OR 15 and 16, signals are generated that define the input or output channel to which the control is addressed. digital computer. These signals are formed from the two most significant bits of the address transmitted through inputs 13 and 14, corresponding to the most significant bits of the internal information bus of the control digital computer. In this way, two-level addressing is organized (the upper two bits of the address define the channel to which the control computer accesses;

The other ones are used for addressing within the channel itself). Two-level addressing, formation, addressing signals from the signals of the internal information bus of the digital computer and higher. as managers, they provide access to any channel if part of the information bus 9 lines fail.

Device for VBOD-vyshod information works as follows.,

The address of the information input 19, from which information is entered, is given to the control digital computer when accessing channel 21 and entered into register 5, from the output of which the address goes to the address inputs of multiplexer 1. Recording to register 5 occurs on the front of the 1/0 signal at input 10 , reading - by the zero signal at the output of the element OR 15, Information from the selected information input 19 / is immediately recorded in the register 2; the appearance of the zero level of the signal at the output of the element OR 15; Input into the control digital computer occurs at the zero level at the same time, at the output of the element OR 13 and at the input 11 of the device (input Input) 5 associated with the control 1151 inputs of the transceiver 3. When outputting information from the digital computer (control word) to the channel 21, it enters through the memory block 8 at the information output The 20 device with the address recorded by the digital computer into the register 7, which is the register with the decoder output, the signals from which are sent to the first inputs of the elements OR 18, determines the choice of the register 22 in the memory block 8, to which when deactivating the control word going on writing. Writing to register 7 occurs on the front of the 1/0 signal at the input 10 of the device. Writing into one or another register 22 of memory block 8 takes place when the single signal at the output of the corresponding element of this register is OR 18, which occurs when there are zero levels of signals at the output of the OR .18, .. third input -12 device (input Output) and at the output of the register 7. associated with the input of the corresponding element OR 18. Register 7 is permanently open at the output. In digital control systems, the protection of information buses (device 9 bus), which includes a large number of lines, is of particular importance. If the number of control lines is small and it is easy to duplicate them, then the number of lines of information bus 9 can reach forty-eight or more. With data bus 9, a large number of buffers (registers, transceivers) are lost, the failures of which lead to the failure of the lines associated with them. A malfunction of one or several lines of information bus 9 is detected as a result of test control performed by the control digital computer. In the event of a malfunction of the information bus lines 9, a failed line is identified. The proposed device allows to provide input-output of correct information in case of failure of part of information bus lines 9. Ensuring correct addressing of information inputs and outputs. When transmitting the address of information inputs 19 and outputs 20, bus 9 is functionally redundant, since several bus lines 9 are sufficient for addressing and the rest are not used. This allows the address of information inputs 19 and outputs 20 to be issued simultaneously to three or more groups of bus lines 9 and to allocate the correct address using a block of 6 majority elements. The number of groups to which the address of information inputs 19 and outputs 20 is assigned is determined by the number of information inputs 19, outputs 20 and bus width 9. How the allocation of the correct address occurs is shown in FIG. 2. At the output of the f-ro majority element 24, whose inputs are connected to the lines through which the t-th bit of the address is transmitted, the correct value of this bit is formed even if some bus lines 9 fail. Similarly, the remaining bits of the address . A malfunction of the address is caused by the failure of half or more lines connected to the inputs of the majority element 24, through which the same address bit is transmitted. Addresses information input 19 and information output are recorded respectively in registers 5 and 7. Ensuring that the correct information is entered. Obtaining the correct input information code is of particular importance for the control digital computer in the automatic control system, since the distortion of even the lower bits of this code leads to a significant reduction in the quality of regulation. Entering the correct information is achieved by a hardware cyclic shift using register 2 of the input digital code. The cyclic shift of the input value digital code recorded in register 2 occurs upon completion of reading the control digital information from the input channel (on the front 0/1 of the signal from the output of the OR 4 element). In the case of the health of all tires 9, the control digital computer simply reads the code of the input value from register 2 via transceiver 3. 8 If one of the bus lines 9 fails, the control digital computer reads information from register 2 twice: the input value code itself is entered and it is cyclically shifted , which allows the processor to get the correct values of the code bits of the input value, which are initially issued to the wrong bus line 9. In the event of several bus lines 9 failing, the control PCM reads the code from register 2 as many times, obtaining values the input value code itself and the same code, but cyclically shifted by one, two or more bits. The information input algorithm is shown in FIG. 5, where n is the number of failed lines. Ensuring that the correct information is output to the information outputs. The control digital computer implies the control word simultaneously on both halves of the bus 9, Less than the information bus 9, the control word can be allowed because the level of quantization error that occurs when the control transforms into analog. form for automatic control systems with feedback is small. If the bus 9 is healthy, the control word is fed to the information outputs from one or the other half of the bus 9, if one or more lines of one half of the bus fails, the control word The information outputs 20 are fed from an operative half of the tire 9, if both halves of the tire 9 fail, the control word comes from the half where the lines corresponding to the slower control word for the control word Fail half of the tire 9 fails. at outputs 20, determines the lower-order bit of the information output address, recorded in register 7, the remaining bits of which are determined directly by the information, to which the control action is applied. The control word being written into the memory block 8 occurs at the simultaneous zero level of the signals at input 2, at the output of the OR 16 element and the output signal of the register 7, the control word at the information output 20 occurs from one of two registers 22 defined by signals from the outputs of the flip-flops 23, which are set to one or another position depending on the younger bit of the information output address when writing the control tree to the corresponding pair of registers 22. Formula of the invention water information containing a multiplexer, the information inputs of which are the information inputs of the device, the output address register and the input address register, whose outputs are connected to the multiplexer address inputs, the input address register entry input is combined with the output address register input input and is the first control input Devices, characterized in that, in order to increase reliability, the device comprises a receiving register, a block of majority elements, a command register, first, second and third elements AND LI, a group of OR elements, a memory unit and a transceiver, the information inputs of the command register are respectively the fourth and fifth control inputs of the device, the control input of the command register is connected to the second inputs of the first and second elements OR, and is the first control input of the device , the outputs of the command register are connected respectively to the first inputs of the first and second elements OR, the output of the first element OR is connected to the input of the receiving register, the input of the register of the input address, the first control input of the transceiver and the first input of the third OR element, the second input connected to the second control input of the transceiver, is the second control input of the device, and the output is connected to the clock input of the receiving register, the outputs of the multiplexer are connected to the information inputs of the receiving register whose outputs are connected to the information inputs of the transceiver, the outputs of which are connected to the inputs of the majority elements block and the information inputs of the memory block and are information tional outputs of the first group unit, the unit outputs the majority of elements are connected to the data inputs of the registers of the input and output addresses, vshoda address register output is connected, us with the first inputs of the corresponding element or group, the second inputs of which are connected to the output of the second OR gate, and third inputs

combined and are the third control input of the device, the outputs of the elements of the RSII group are connected to the corresponding write-read and select memory inputs of the memory block whose outputs are the information outputs of the device of the second group.

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Claims (1)

Claim A device for input-output information containing a multiplexer, the information inputs of which are information inputs of the device, the output address register and the input address register, the outputs of which are connected to the address inputs of the multiplexer, the input input register register input is combined with the read input of the output address register register and is the first control device input, characterized in that, in order to increase reliability, the device contains a receiving register, a majority element block, a command register, first, second and the third OR element, a group of OR elements, a memory unit and a transceiver, information inputs of the command register are the fourth and fifth control inputs of the device, the control input of the command register is connected to the second inputs of the first and second OR elements and is the first control input of the device, the outputs of the command register connected respectively to the first inputs of the first and second OR elements, the output of the first OR element is connected to the input of the receive register entry, the read input register and the input address, the first control input of the transceiver and the first input of the third OR element, the second input of which is connected to the second control input of the transceiver and is the second control input of the device, and the output is connected to the clock input of the receive register, the multiplexer outputs are connected to the information inputs of the receive register, the outputs of which are connected to the information inputs of the transceiver, the outputs of which are connected to the inputs of the block of majority elements and the information inputs of the memory block and are the information outputs of the device of the first group, the outputs of the majority element block are connected to the information inputs of the input and output address registers, the outputs of the output address register are connected to the first inputs of the corresponding elements of the OR group, the second inputs of which are connected to the output of the second OR element, and the third inputs 7 are combined and are the third control input of the device, the outputs of the elements OR groups are connected to the corresponding inputs of the record-count- 8 of sampling and sampling the crystal of the memory block, the outputs of which are information outputs of the device of the second group. ΝχΜκ] (K4) [N / kJ [N / K] 0-27 ..... · '· .------- V --------------- 9 + IE.2 Input digital code from shift register Cyclic sdig information stored in the 6 sdg register In the baud information from the register Cyclical shift of information stored in the shift register Definition of bits of the Entered code corresponding to faulty bits of the information bus P £ l -? ..... j Ret Determining the correct input code i Continued Implementation of _d Regulatory Program Figb