SU1173537A1 - Pulse recurrence rate multiplier - Google Patents

Abstract

MULTIPLACE OF PULSE FOLLOWING PULSE, containing a pulse shaper, the input of which is connected to the input bus, the output - to the input of the control unit, the first output of which is connected to the first input of the OR element, the second input of which is connected to the first input of the trigger, the second input of which is connected to the output of the first counter pulses, the counting input of which is connected to the output of the first element I, the first input of which is connected to the first output of the trigger, the second output of which is connected to the output bus and to the first input of the second element a And, the output of which is connected to the counting input of the second pulse counter, the second input of the first element I is connected to the output of the first frequency divider, the input of which is connected to the reference frequency bus and to the second input of the second element I, the second frequency divider whose output is connected to the counting input The third pulse counter, whose information outputs are connected to the information inputs of the first pulse counter through the first memory register, characterized in that, in order to increase the multiplication accuracy when the input voltage changes second frequency, the second memory register is entered into it, the information inputs of which are connected to the information outputs of the second frequency divider, the counting input of which is connected to the output of the first $ S frequency divider, the reset input — to the second output of the control unit and to the reset input (L of the third counter pulses, the recording input of the first memory register is connected to the recording input of the second memory register and the first input of the OR element, the second input of which is connected to the output of the second pulse counter, the output to the recording inputs of the first and second c pulse counters, and information inputs of the second pulse counter are connected to information outputs of the second memory register. 00 GSL SO

Description

The invention relates to a pulse technique and can be used in automation devices and measurement techniques. The purpose of the invention is to increase the multiplication accuracy when the input frequency is changed by compensating for the error when the input frequency is changed. FIG. Figure 1 shows an electrical structure of a pulse frequency multiplier circuit; 2 shows a control unit embodiment; in fig. 3 - time diagrams of the device, which show the operation of the device. The pulse frequency multiplier contains a pulse former 1. the input of which is connected to the input bus 2, the output is connected to the input of the control unit 3 and the nex river output is connected to the first input of the OR 4 element, the second input of which is connected to the first input of the trigger 5, the second input of which is connected to the output of the first counter of 6 pulses, counting the input of which is connected to the output of the first element And 7, the first input of which is connected to the first output of the trigger 5, the second output of which is connected to the output bus 8 and to the first input of the second element And 9, the output of which is connected to the counting input of the second counter 10 pulses The second input of the first element I 7 is connected to the output of the first frequency divider 11, whose input is connected to the 12 reference frequency and to the BTOjibiM input of the second element 9, the second frequency divider 13, the output of which is connected to the counting input of the third counter 14 pulses, information outputs of which through the first register 15 of memory are connected to information inputs of the first counter of 6 pulses, the second register 16 of memory, whose information inputs are connected to information outputs of the second frequency divider 13, the counting input of which is connected to the output of the first frequency divider 1 1, the reset input — with the second output of the control unit 3 and the reset input of the third pulse counter 14; the recording input of the first memory register 15 is connected to the recording input of the second memory register 16 and the first input of the OR 4 element, the second the input of which is connected to the output of the second pulse counter 10, the output to the write inputs of the first 6 and second K) pulse counters, the information inputs of the second counter of the 10 pulses are connected to the information outputs of the second 16-pt-m register. Control unit 3 consists of two series-connected single vibrators 17 and 18, the nerve input of which is the control unit input, the first output the first output, and the second output the second output of the control unit. The first and second pulse counters are made subtractive, the third - sums) DY1DIM. The device works as follows. The pulses of the multiplied frequency F through the pulse shaper 1 are fed to block 3 and in the single vibrators 17 and 18, respectively, write pulses (Fig. 36) of information are generated in registers 15 and 16 and through element 4 (Fig. Zg) - into counters 6 and 10 (Fig Zv) divider 13 and counter 14. In the initial state, trigger 5 is in the state "O (Fig. ZG)" and the contents of the divider 13 and counter 14 are zero. At the beginning of the i-ro period of the multiplied frequency, the output signal (Fig. 36) of block 3 from the first output is used to overwrite the code combination accumulated in the (i-1) -th period from counter 14 to register 15, and then to counter 6 pulses with a signal (Fig. 3g), which arrived at its second input from the first output of block 3 through element 4. The same pulse is used to overwrite the code combination from divider 13 into register 16 and into counter 10. At the next moment in time, pulse.m (fig. Sv) reset e of the second output of block 3 is reset to "About divider 13 and counter 14, thereby under otavliva them for filling the circuit frequency reference. During the i-ro period of the multiplied frequency, the reference frequency fo is divided by M in divider 11, the pulses with frequency f | fo / M is sent to the counting input of the divider 13. From its output, pulses already at the frequency f2 fi / M are fed to the counting input of the counter 14 In the counter 6, the recorded number NI received by the pulse with the frequency f: / M during the time T in (i -1) -m period of the frequency to be multiplied, pulses (fig. Back) with frequency fi, arriving at the counting input of counter 6 from the output of element 7, which is open to great potential, coming from the inverse output of trigger 5. At the end of the compensation cycle by the output signal ( Fig. Ze) of counter 6: flip-flop 5 (fig. ZJ), covering the ale The ent 7 and the opening element 9, through which the pulses with the frequency fo (fig. Z) arrive at the counting input of the counter 10. At the same time, through the closed element 7 pulses (fig. З. d) with the frequency fi on the counting input of the counter 6 are coming in. Thus, in counter 10, a compensation of the recorded number occurs, after which a pulse appears on its output (Fig. 3k), which flips the trigger 5 to the initial state and the first output pulse is formed (Fig. 3g) with a correction. In this case, the low potential coming from the direct output of the trigger 5, the element 9 is closed, and the high potential coming from the inverse output of the trigger 5, the element 7 opens. With the same output signal (Fig. 3k) of the pulse counter 10, passing through element 4 (Fig. 3g), the readings of the register 15 are recorded in the counter 6 and the readings of the register 16 are recorded in the counter 10. 3 The new compensation cycle begins. The pulses (Fig. A) through element 7 arrive at the counting input of counter 6 until the number entered from register 15 is compensated. At the time of compensation, a pulse appears on the output of counter 6 (Fig. Ze), which flips the trigger 5 in a single state (Fig. ZJ). Trigger 5 opens element 9 and closes element 7. Pulses (Fig. 3i) with frequency b are fed to the counting input of pulse counter 10 until an output pulse is received at its output (Fig. 3c), which throws trigger 5 into the zero state and overwrites the contents of register 15 into counter 6 and the contents of register 16 into counter 10. Then the process repeats during multiplication periods.

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Claims (1)

A PULSE FREQUENCY FREQUENCY MULTIPLIER containing a pulse shaper whose input is connected to the input bus, the output is to the input of the control unit, the first output of which is connected to the first input of the OR element, the second input of which is connected to the first input of the trigger, the second input of which is connected to the output of the first counter pulses, the counting input of which is connected to the output of the first And element, the first input of which is connected to the first output of the trigger, the second output of which is connected to the output bus and with the first input of the second And element, the stroke of which is connected to the counting input of the second pulse counter, the second input of the first element And is connected to the output of the first frequency divider, the input of which is connected to the reference frequency bus and to the second input of the second element And, the second frequency divider, the output of which is connected to the counting input of the third pulse counter , the information outputs of which are connected through the first memory register to the information inputs of the first pulse counter, characterized in that, in order to increase the accuracy of the multiplication when the input frequency is changed, he entered the second memory register, the information inputs of which are connected to the information outputs of the second frequency divider, the counting input of which is connected to the output of the first s of the frequency divider, the reset input - with the second ® output of the control unit and with the reset input l of the third pulse counter, recording input 1 of the first the memory register is connected to the input / record of the second memory register and to the first * input of the OR element, the second input of which q is connected to the output of the second pulse counter, the output to the recording inputs of the first and second imp counters pulses, and the information inputs of the second pulse counter are connected to the information outputs of the second memory register. ί