SU1084901A1 - Device for checking memory block - Google Patents

Abstract

A DEVICE TO CONTROL MEMORY BLOCKS, containing an address counter, the outputs of which are the corresponding outputs of the device, the first shift register, the setting inputs of which are one of the device's inputs and connected to one of the inputs of the comparison unit, the output of the first shift register is connected to one of the inputs of the element block And, the outputs of which are connected to the inputs of the adder, the outputs of the adder are connected to other inputs of the comparison unit, the second shift register, the clock generator, the frequency divider, triggers and elements, distinguished by the fact that, in order to increase its speed and simplify the circuit, the output of the clock generator is connected to the input of the Frequency divider and to the first inputs of the first and second elements And, the output of the frequency divider is connected to the counting input of the first trigger and the first inputs of the third and fourth elements And the first output of the first trigger is connected to the second inputs of the first and third elements And the output of the first element And connected to the clock input of the second shift register, the installation inputs Secondly, they are other inputs of the device, the output of the second shift register is connected to the second input of the second element, the output of which is connected to the clock input of the first shift i register, the second output of the first trigger is connected to the second input of the true element And whose output is connected to the input of the address counter and is the corresponding control output of the device, the outputs of the address counter are connected to the inputs of the fifth And element, the output of which is connected to the first input of the sixth And 30 element, the setup input d second 4 21. The first trigger is connected to the output of the sixth element And, the second input of which is connected to the output of the comparison unit, the input of the clock generator is connected to the first output of the second trigger, the second output of which is the corresponding control output of the device.

Description

The invention relates to computing and can be used to control storage devices.

A device for monitoring memory blocks is known, comprising a register accumulating an adder, an address counter, a constant register, and a comparison block. The control of the memory block is carried out by summing the information and comparing the obtained sum with the given constant 1.

The disadvantage of this device is low control accuracy.

The closest in technical essence to the invention is a device for controlling memory blocks, containing a shift register, the outputs of which are connected to information inputs of the adder, the outputs and control inputs of the adder are connected to the corresponding inputs and outputs of the control unit, an address decoder, information the inputs of which are connected to the corresponding outputs of the address counter, the control output of the address counter is connected to the corresponding input of the control unit and the unit for setting the summing cycles , Control inputs devtfratora address and the address counter are connected to the outputs so.otvetstvuyuschim control unit outputs and inputs of summing cycles specifying connected to respective inputs and outputs of the control unit. The control unit and the task unit for summing cycles contain a clock pulse generator, frequency dividers, device timers, registers, triggers and logic element C2.

The disadvantages of the known device are the low speed associated with the need to perform several cycles of the check sum of the contents of the memory block, as well as its complexity.

The purpose of the invention is to increase the speed and simplify its scheme.

The goal is achieved by the fact that in a device for monitoring memory blocks containing an address counter, the outputs of which are the corresponding outputs of the device, the first shift register, the setup inputs of which are one of the inputs of the device and connected to

one of the inputs of the comparison unit, the output of the first shift register is connected to one of the inputs of the block of elements And whose outputs are connected to the inputs of the adder, outputs (the adder connected to the other inputs of the comparison unit, the second shift register, the clock pulse generator, the frequency divider triggers and

o elements And, the output of the clock pulse generator is connected to the input of the frequency divider and to the first inputs of the first and second elements And, the output of the frequency divider is connected to the counting input

5 of the first trigger and to the first inputs of the third and fourth elements of AND, the first output of the first trigger is connected to the second inputs of the first and third elements of AND, the output of the first

0 of the AND element is connected to the clock input of the second shift register, the setup inputs of which are other inputs of the device, the output of the second shift register is connected to the second input of the second AND element whose output is connected to the clock input of the first shift register; the second output of the first trigger is connected to the second input of the fourth element of the AND, whose output is connected to the input of the address counter and is the corresponding control output of the device, the outputs of the address counter are connected to the inputs of the fifth

5 element And, the output of which is connected to the first input of the sixth element And; the setup input of the second trigger is connected to the output of the sixth element K, the second input of which is connected to the output of the comparison unit, the input of the clock generator is connected to the first output of the second trigger; the second output of which is the corresponding control of the device trick.

Fig. 1 shows a block diagram of a device for monitoring memory blocks; FIG. 2 is a timing diagram of the signals at the outputs of the Nex Orps device nodes; on fihch 3 - structural schemes ..; clock generator and circuits of the initial installation of devices in FIG. 4, the block diagram of the initial installation,

A device for controlling memory blocks contains rm generator 1 clock pulses, - divider 2 frequencies trigger 3f elements 4-7, shift I register 8, initial setting block 9, driver 10 for control pulses, address counter 11, memory block 12, shift register 13, block 14 elements AND, adder 15, block 16 14 elements AND, adder ID, logolog 1. elements And 17 and 18. trig-comparisons, elements And 17 and 18, comparison t, elements and i / and lo, trigger 19, display element 20, sup 19, display element 20, clock generator output 21: pulses, frequency divider output 22 , the outputs 23 and 24 of the trigger 3, the output 25 of the element And 5, the output 26 of the element And 6, the output 27 of the element And 4, the output 28 of the shift register 8, the output 29 of the element And 7 1 the target generator 30, the element And 31, the generator 32, the trigger 33 , button 34 Start, button 35 Stop, input 36 of generator 1, output 37 of generator 32, delay element 38, circuit 39 to input of clock register 8, circuit 40 to input of reg mode Stra 8, bus 41 logs Cesky zero, the NOT element 42, bus 43 logical unit 44 outputs the initial setting unit. The device works as follows. When the Start button is pressed, the trigger 33 is transferred to a single state, and a negative differential (from 1 to O) voltage is applied to the clock input of the ring shift register 8, and at the time the input of register mode 8 there is still a level I corresponding to the recording mode . In this case, the code 111001100010 is entered into it from block 9 of the initial installation. After a time interval determined by the delay element 38, at the input of the register 8 mode, a level O is set corresponding to the shift mode. At the same time, I at the single output of the P-flip-flop 33 is supplied to the input of the element 31. At the output 21 of the clock 1 generator, pulses appear at the inputs of the frequency divider 2 and the elements 4 and 7. At the output 22 of the divider 2 The pulses that arrive at the input of the T-flip-flop 3 and the first inputs of the And 5 and 6 elements. At the outputs 25 and 26 of the And 5 and 6 elements, pulses appear (Fig. 2). The first signal from the output of the element 6 to the address counter 11 is entered one and a control pulse is generated at the output of the imaging unit 10, and the information from the first cell of the tested memory block 12 is written into the ring shift register 13. At the output 10 1 de 27 of the element 4 a series of pulses arrives at the shift input of the annular shift register 8, and the information in it shifts by the number of bits corresponding to the number of pulses in the series at the shift input. At the output of the high bit of register 8, the unit appears in the shift only once, which is caused by the previously recorded code. Therefore, at the output of the And 7 element, only one pulse appears, which shifts the contents of the register 13 by one bit. After the pulse arrives from the And 5 element. Information is shifted through the block 14 of the And elements to the accumulating adder 15. The second 1-1Mpuls from the output element 6 again enters counter 11, a pulse is generated to access block 12, and register 13 records information from the second cell of the memory block. Again, the pulses from the output 27 of the element 4 and 4 shift the contents of the register 8 and, at the output of its higher bit, I appears twice during the shift, which is also due to the previously recorded code pattern. At the output of the K 7 element, two pulses appear, and the information in the register 13 is shifted by two bits. The signal from the output of the element And 5 through the block 14 elements And the information is fed to the adder 15, where it is summed with its contents. Further, in the same way, the information from the third memory cell of the block 12 is coupled with the contents of the adder 15, having previously shifted by three bits, etc. Thus, sequential reading of information from the checked memory block occurs, its shift on the ring register 13 and summation on the adder 15. The information is shifted around the ring, i.e. from the younger to the older ones, and from the oldest to the younger. The outputs of the adder 15 are connected to the inputs of the comparison unit 16, the other inputs of which are connected to the outputs of the checked memory block. At the last address at the output of the element And 17 appears I. If the contents of the last cell of the checked memory block are equal to the contents of the adder, the output of the comparison block 16 is O, and the trigger 19 remains in the zero state. In the last

The memory block should be stored in the memory block, taking into account the selected shift sequence of the read information. In the event of a malfunction of unit 12 at the output of comparator unit 16 at the time of the occurrence of the last address, trigger 19 is set to state I and the display element is triggered. At the same time, the generator stops.

The proposed device is most effective in the control of constant

memory devices, the address control Macrtf of which in dynamic mode presents difficulties. At the same time, a high response rate is ensured, since to carry out monitoring it is sufficient to carry out one cycle of summation. In addition, the proposed technical solution is simpler known, since it does not have a block for setting cycles of summation, and has lower hardware costs to provide a time diagram of the operation of the device.

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Claims (1)

DEVICE FOR MONITORING BLOCKS OF MEMORY, containing an address counter whose outputs are the corresponding outputs of the device, the first shift register, the installation inputs of which are one of the inputs of the device and connected to one of the inputs of the comparison unit, the output of the first shift register is connected to one of the inputs of the block of elements And, the outputs of which are connected to the inputs of the adder, the outputs of the adder are connected to other inputs of the comparison unit, a second shift register, a clock, a frequency divider, a trigger s and AND elements, characterized in that, in order to increase its speed and simplify the circuit, the output of the clock pulse generator is connected to the input of the Frequency divider and to the first inputs of the first and second I elements, the output of the frequency divider is connected to the counting input of the first trigger and to the first the inputs of the third and fourth elements And, the first output of the first trigger is connected to the second inputs of the first and third elements And, the output of the first element And is connected to the clock input of the second shift register, the setting inputs of which are the other inputs of the device, the output of the second shift register is connected to the second input of the second element And, the output of which is connected to the clock input of the first shift register, the second output of the first trigger is connected to the second input of the fourth element And, the output of which is connected to the input of the address counter and is the corresponding control the output of the device, the outputs of the address counter are connected to the inputs of the fifth AND element, the output of which is connected to the first input of the sixth AND element, the installation input of the second trigger li ne to the output of the sixth AND gate, a second input connected to the output of the comparator, the clock input of the generator connected to the first output of the second flip-flop, the second output of which a corresponding control output of the apparatus. >