SU1084996A1 - Device for measuring phase jitter - Google Patents

Abstract

A DEVICE FOR MEASURING PHASE SHITTING, containing a matching unit, an indicator and a series-connected rectifier, a clock selection unit, a frequency detector, an integrator and a quadratic detector, so that, in order to improve the measurement accuracy, a pseudo-random sequence generator, a first switching unit, a control unit and a second switching unit connected in series, a memory unit and a subtraction unit are entered into it, and the output of the matching unit through the first switching unit, The second and third inputs of which are connected respectively to the output of the pseudo-random sequence generator and to the first output of the control unit are connected to the rectifier input, the output of the quadratic detector is connected to the first input of the second switching unit, the second input of which is connected to the second output of the control unit and to the BTOptw input of the block memory, and the second output of the second switching unit SP is connected to the second input of the subtraction unit, the output of which is connected to the input of the indicator.

Description

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a The invention relates to telecommunications and can be used in devices controlling channels of digital transmission systems. A device for measuring phase jitter is known, comprising a matching unit, the output of which is connected via a phase detector to an input of the indicator and to an input of a pilot signal generator, the output of which is connected to a second input of the phase detector, as well as a control unit and a memory block flj. A disadvantage of this device is the low measurement accuracy due to the inherent error of the device. The closest to the invention in technical essence and the achieved result is a device for measuring phase jitter, which contains a matching unit indicator and a series-connected rectifier, a selection unit, no clock frequency, a frequency detector, an integrator and a quadratic detector. The principle of operation of a known device consists in extracting a continuous clock oscillation from a digital linear signal, often followed by a low-frequency phase jitter envelope using a frequency detector and an integrator G2. However, the accuracy of measurement in a known HOM device is, in many respects, determined by the clock extraction unit; theta (SPM). This block extracts the oscillation from a random digital linear signal. A feature of the WHP unit is that when an inaccurate tuning (detuning) of the block at the clock frequency contained in the digital signal, it begins to carry its own phase jitter. The amount of input jitter is proportional to the amount of detuning of the WHF block, which increases the error in measuring the phase jitter which is especially noticeable when measured. Small values of phase jitter. The purpose of the invention is to improve the measurement accuracy. The goal is achieved by introducing a pseudo-random sequence generator, a first switching unit, a control unit, and sequentially into a device for measuring a phase jitter containing a matching unit, an indicator and successively connected rectifier, an HTM unit, a frequency detector, an integrator and a quadratic detector. connected to the second block of co-switching, the memory block and the subtraction block, when ets the output of the matching block through the first switching block, the second and third inputs of which are connected respectively to The output of the pseudo-random sequence and the first output of the control unit is connected to the rectifier input, the output of the quadratic detector is connected to the first input of the second switching unit, the second input of which is connected to the second input of the control unit, and the second output of the second The switching unit is connected to the second input of the subtraction unit, the output of which is connected to the input of the indix-torus. The structural electrical circuit of the device for measuring the phase jitter is shown in the drawing. The device contains a matching unit 1, a rectifier 2, a block of 3 SPM, a frequency detector 4, an integrator 5, a quadratic detector b, an indicator 7, a pseudo-random sequence generator 8, the first switching unit 9, the second switching unit 10, the memory block 11, the block 12 subtraction and control unit 13. The device works as follows. - A digital linear signal is fed to the input of the matching unit 1, from the output of which the signal is fed to the first input of the first switching unit 9. The reference signal from the output of the pseudo-random sequence generator 8 is fed to the second input of the first switching unit 9. Depending on the control signal coming from the first output of the control unit 13 to the third input of the first switching unit 9, the output of the latter has a signal that is present on either the first or the second input. This signal is fed to the input of the rectifier 2, to the output of which, 3 WHF unit, frequency detector 4, integrator 5 and quadratic detector 6 are connected in series. Rectifier 2 serves to convert the bipolar signal into a unipolar signal, and the THB unit 3 converts a random input signal or a pseudo-random signal produced by the pseudo-random signal generator 8 into a continuous sequence of pulses with a repetition frequency equal to the clock frequency of the tested communication system (for example, in a thirty-channel PCMT system) the frequency is 2.048 MHz). An uninterrupted sequence of pulses from the output of a 3 WHP unit, representing a phase-modulated process, is then fed to a frequency detector 4k. Using frequency detector 4 and integrator 5, low-frequency phase jitter is extracted from this phase-modulated oscillation. The low-frequency random signal from the output of integrator 5 is fed to the input quadratic detector 6. Block 3 VCH has a resonant circuit tuned to the clock frequency, and with inaccurate tuning it begins to introduce its own phase phase. The life is proportional to the amount of detuning. To eliminate this signal from the output of the 3 WHP unit through the serially connected frequency detector 4, integrator 5 and quadratic detector B, it is fed to the first input of the second switching unit, to the second input of which a control signal is supplied from the second output of the control unit 13. Depending on this control signal, the second switching unit 10 connects to the output of a quadratic detector 6 either the first input of the memory unit 11 or the second input of the subtraction unit 12. Moreover, in the case when the corresponding control signal arrives from the first output of the control unit 13 to the third input of the first switching unit 9, this block sends a signal from the pseudo-random sequence generator 8 to the input of the rectifier 2, turning off the input signal coming from. output of block 1 matching. A control signal is supplied to the second inputs of the second switching unit 10 and the memory unit 11 from the second output of the control unit 13, which sets the memory unit 11 to the information recording mode, and the second switching unit 10 sets the position at which the second input of the unit 11 The memory is connected to the output of a quadratic detector 6. Moreover, due to the absence of phase jitter of the reference pseudo-random signal produced by the generator 8 of the pseudo-random signal, only the signal can be output at the output of the square detector 6 proportional to the magnitude of the intrinsic jitter of the block. This signal in analog form is memorized by memory block 11. At the same time, the second switching unit 10 disconnects the input of the subtraction unit 12 from the output of the quadratic detector 6. In this mode of operation, the value of its own phase fault and the 3 HTP unit are monitored and stored. In the second mode, the jitter of the input signal at the input of the matching .1 block is measured. At the same time, after the arrival of the control signal from the first output of the control unit 13 to the third input of the first switching unit 9, the latter connects the input of the rectifier 2 to the output of the matching unit 1, turning off the pseudo-random signal generator 8. Pass through the series rectifier 2 and unit 3 SPM, the signal is fed to the input of the frequency detector 4, the output of which is an analog signal proportional to the magnitude of the phase jitter of the input signal. It is summed up with a signal proportional to the own phase jitter of a 3 THF unit. From the second output of the control unit 13, a control signal is supplied to the second inputs of the second switching unit 10 and the memory unit 11. Under the influence of this signal, the memory block 11 goes into storage mode, and the second switching unit 10 goes into a mode in which the first input of the memory block 11 is disconnected from the output of the quadratic detector 6. Instead, the second input of the block 12 is connected to the output of the quadratic detector b subtraction. At the same time, a signal from the output of memory block 11, which is in storage mode, is fed to the first input of subtraction unit 12, since a signal from the output of a quadratic detector is sent to the second input of subtraction unit 12 proportional to the sum of the phase jitter of the input signal unit 1 matching, and the own phase jitter of the 3 WHT unit, and the first input of the subtraction unit 12 receives a signal from the output of the memory block 11 proportional to the value of the own phase jitter of the 3 WHS block recorded in memory block 11 in A previous mode at block 12 subtracting a signal proportional to the sum of the values of the phase jitter of the input signal and the phase jitter own unit 3 Wh subtracted signal proportional to the magnitude of the phase dryzhani 3VTCH own block. At the output of the readout unit 12, only a signal proportional to the magnitude of the phase jitter of the input signal remains. This signal is then fed to the indicator 7. As a result, the signal proportional to the own phase jitter of the 3 THF unit is compensated in the subtraction unit 12. The technical and economic efficiency of the device consists in bending measurement accuracy by reducing the intrinsic error, which makes it possible to detect minor changes in the state of the regenerators in terms of the magnitude of the phase jitter. By reducing the measurement error in 3–5 EE, the proposed S device will provide a measurement of the phase of the digital signal by a factor of K less than will allow it to be taken for measuring such multi-channel communication systems with the use of PCM. 1084996

Claims (1)

DEVICE FOR MEASURING PHASE SHAKING, comprising a matching unit, an indicator and a rectifier connected in series, a clock frequency isolation unit, a frequency detector, an integrator and a quadratic detector, which means that, in order to increase the accuracy of measurements, a generator is introduced into it pseudo-random sequence, the first switching unit, the control unit and the second switching unit connected in series, the memory unit and the subtraction unit, while the output of the matching unit through the first switching unit, the second and t the third inputs of which are connected respectively to the output of the pseudo-random sequence generator and to the first output of the control unit, are connected to the input of the rectifier, the output of the quadratic detector is connected to the first * <input of the second switching unit, the second input of which is connected to the second output of the control unit and to the second input of the memory unit and the second output of the second switching unit is connected to the second input of the subtraction unit, the output of which is connected to the indicator input. SU ... 1084996