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SG126691A1 - Synchronous memory modules and memory systems withselectable clock termination - Google Patents

Synchronous memory modules and memory systems withselectable clock termination

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Publication number
SG126691A1
SG126691A1 SG200201204A SG200201204A SG126691A1 SG 126691 A1 SG126691 A1 SG 126691A1 SG 200201204 A SG200201204 A SG 200201204A SG 200201204 A SG200201204 A SG 200201204A SG 126691 A1 SG126691 A1 SG 126691A1
Authority
SG
Singapore
Prior art keywords
memory
systems
memory modules
clock
withselectable
Prior art date
Application number
SG200201204A
Inventor
Steven A Grundon
Mark William Kellogg
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Priority to SG200201204A priority Critical patent/SG126691A1/en
Publication of SG126691A1 publication Critical patent/SG126691A1/en

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Abstract

Memory systems and/or memory modules allow selectable clock termination between the clock/clock buffer and components of the memory modules. Memory modules can operate in existing (emerging) memory subsystems, as well as meet the low power/low pin count needs of future memory subsystems, with no required changes to the existing/emerging systems. For 184 Pin Registered DIMMs, power savings equate to greater than 200mw/DIMM, and systems are permitted to connect DIMM clocks in serial, similar to address/control lines, thereby increasing the address/control window as well as system read loop- back timings.
SG200201204A 2002-02-28 2002-02-28 Synchronous memory modules and memory systems withselectable clock termination SG126691A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
SG200201204A SG126691A1 (en) 2002-02-28 2002-02-28 Synchronous memory modules and memory systems withselectable clock termination

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG200201204A SG126691A1 (en) 2002-02-28 2002-02-28 Synchronous memory modules and memory systems withselectable clock termination

Publications (1)

Publication Number Publication Date
SG126691A1 true SG126691A1 (en) 2006-11-29

Family

ID=38288495

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200201204A SG126691A1 (en) 2002-02-28 2002-02-28 Synchronous memory modules and memory systems withselectable clock termination

Country Status (1)

Country Link
SG (1) SG126691A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5687330A (en) * 1993-06-18 1997-11-11 Digital Equipment Corporation Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver
EP0476394B1 (en) * 1990-08-31 1998-07-01 Fujitsu Limited Clock distribution system
US6347367B1 (en) * 1999-01-29 2002-02-12 International Business Machines Corp. Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0476394B1 (en) * 1990-08-31 1998-07-01 Fujitsu Limited Clock distribution system
US5687330A (en) * 1993-06-18 1997-11-11 Digital Equipment Corporation Semiconductor process, power supply and temperature compensated system bus integrated interface architecture with precision receiver
US6347367B1 (en) * 1999-01-29 2002-02-12 International Business Machines Corp. Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures

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