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SG11202000763TA - Reconfigurable cache architecture and methods for cache coherency - Google Patents

Reconfigurable cache architecture and methods for cache coherency

Info

Publication number
SG11202000763TA
SG11202000763TA SG11202000763TA SG11202000763TA SG11202000763TA SG 11202000763T A SG11202000763T A SG 11202000763TA SG 11202000763T A SG11202000763T A SG 11202000763TA SG 11202000763T A SG11202000763T A SG 11202000763TA SG 11202000763T A SG11202000763T A SG 11202000763TA
Authority
SG
Singapore
Prior art keywords
cache
methods
reconfigurable
architecture
coherency
Prior art date
Application number
SG11202000763TA
Inventor
Elad Raz
Original Assignee
Next Silicon Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Next Silicon Ltd filed Critical Next Silicon Ltd
Publication of SG11202000763TA publication Critical patent/SG11202000763TA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
SG11202000763TA 2017-08-03 2018-08-03 Reconfigurable cache architecture and methods for cache coherency SG11202000763TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762540854P 2017-08-03 2017-08-03
PCT/US2018/045131 WO2019028327A1 (en) 2017-08-03 2018-08-03 Reconfigurable cache architecture and methods for cache coherency

Publications (1)

Publication Number Publication Date
SG11202000763TA true SG11202000763TA (en) 2020-02-27

Family

ID=65231030

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202000763TA SG11202000763TA (en) 2017-08-03 2018-08-03 Reconfigurable cache architecture and methods for cache coherency

Country Status (8)

Country Link
US (4) US11176041B2 (en)
EP (3) EP4209914B1 (en)
JP (1) JP7126136B2 (en)
KR (2) KR102733065B1 (en)
CN (2) CN111164580B (en)
ES (2) ES2950681T3 (en)
SG (1) SG11202000763TA (en)
WO (1) WO2019028327A1 (en)

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EP4209914B1 (en) 2017-08-03 2025-03-19 Next Silicon Ltd Reconfigurable cache architecture and methods for cache coherency
US10402091B1 (en) * 2018-04-30 2019-09-03 EMC IP Holding Company LLC Managing data in log-structured storage systems
US11294724B2 (en) * 2019-09-27 2022-04-05 Advanced Micro Devices, Inc. Shared resource allocation in a multi-threaded microprocessor
US11216377B2 (en) 2019-12-18 2022-01-04 Nxp Usa, Inc. Hardware accelerator automatic detection of software process migration
CN112306500B (en) * 2020-11-30 2022-06-07 上海交通大学 A compilation method for reducing multi-class memory access conflicts for coarse-grained reconfigurable structures
US12333231B1 (en) 2024-11-03 2025-06-17 Next Silicon Ltd. Reconfigurable integrated circuit (IC) device and a system and method of configuring thereof

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Also Published As

Publication number Publication date
EP3662376A4 (en) 2021-04-07
US20190042427A1 (en) 2019-02-07
US20230376419A1 (en) 2023-11-23
EP4542399A3 (en) 2025-07-02
US11720496B2 (en) 2023-08-08
JP7126136B2 (en) 2022-08-26
KR20200049775A (en) 2020-05-08
CN117271392A (en) 2023-12-22
CN111164580B (en) 2023-10-31
KR20240166047A (en) 2024-11-25
US20220100660A1 (en) 2022-03-31
US11176041B2 (en) 2021-11-16
ES3030265T3 (en) 2025-06-27
EP4209914A1 (en) 2023-07-12
US20250335358A1 (en) 2025-10-30
EP3662376A1 (en) 2020-06-10
JP2020530176A (en) 2020-10-15
KR102733065B1 (en) 2024-11-21
EP3662376B1 (en) 2023-04-05
US12360902B2 (en) 2025-07-15
EP4542399A2 (en) 2025-04-23
WO2019028327A1 (en) 2019-02-07
EP4209914B1 (en) 2025-03-19
ES2950681T3 (en) 2023-10-11
CN111164580A (en) 2020-05-15

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