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SG11201704243UA - Method and apparatus for vector index load and store - Google Patents

Method and apparatus for vector index load and store

Info

Publication number
SG11201704243UA
SG11201704243UA SG11201704243UA SG11201704243UA SG11201704243UA SG 11201704243U A SG11201704243U A SG 11201704243UA SG 11201704243U A SG11201704243U A SG 11201704243UA SG 11201704243U A SG11201704243U A SG 11201704243UA SG 11201704243U A SG11201704243U A SG 11201704243UA
Authority
SG
Singapore
Prior art keywords
store
vector index
index load
load
vector
Prior art date
Application number
SG11201704243UA
Inventor
Ashish Jha
Robert Valentine
Elmoustapha Ould-Ahmed-Vall
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG11201704243UA publication Critical patent/SG11201704243UA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
SG11201704243UA 2014-12-23 2015-11-23 Method and apparatus for vector index load and store SG11201704243UA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/581,289 US9830151B2 (en) 2014-12-23 2014-12-23 Method and apparatus for vector index load and store
PCT/US2015/062057 WO2016105755A1 (en) 2014-12-23 2015-11-23 Method and apparatus for vector index load and store

Publications (1)

Publication Number Publication Date
SG11201704243UA true SG11201704243UA (en) 2017-07-28

Family

ID=56129467

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201704243UA SG11201704243UA (en) 2014-12-23 2015-11-23 Method and apparatus for vector index load and store

Country Status (9)

Country Link
US (1) US9830151B2 (en)
EP (1) EP3238026B1 (en)
JP (1) JP6711480B2 (en)
KR (1) KR102463858B1 (en)
CN (1) CN107003846B (en)
BR (1) BR112017010956A2 (en)
SG (1) SG11201704243UA (en)
TW (1) TWI617978B (en)
WO (1) WO2016105755A1 (en)

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EP3428792B1 (en) * 2017-07-10 2022-05-04 Arm Ltd Testing bit values inside vector elements
US10684858B2 (en) * 2018-06-01 2020-06-16 Intel Corporation Indirect memory fetcher
US20200004535A1 (en) * 2018-06-30 2020-01-02 Intel Corporation Accelerator apparatus and method for decoding and de-serializing bit-packed data
US11175915B2 (en) 2018-10-10 2021-11-16 Micron Technology, Inc. Vector registers implemented in memory
US11340904B2 (en) * 2019-05-20 2022-05-24 Micron Technology, Inc. Vector index registers
US11507374B2 (en) * 2019-05-20 2022-11-22 Micron Technology, Inc. True/false vector index registers and methods of populating thereof
US11327862B2 (en) 2019-05-20 2022-05-10 Micron Technology, Inc. Multi-lane solutions for addressing vector elements using vector index registers
US11403256B2 (en) 2019-05-20 2022-08-02 Micron Technology, Inc. Conditional operations in a vector processor having true and false vector index registers
CN112486980B (en) * 2019-09-12 2025-01-24 阿里巴巴集团控股有限公司 Data storage, retrieval method and device, electronic device, and computer-readable storage medium
CN111158757B (en) * 2019-12-31 2021-11-30 中昊芯英(杭州)科技有限公司 Parallel access device and method and chip
CN111782270B (en) * 2020-06-09 2023-12-19 Oppo广东移动通信有限公司 A data processing method, device and storage medium
KR20220090152A (en) 2020-12-22 2022-06-29 에스케이하이닉스 주식회사 Storage device and operating method thereof
KR20220145656A (en) 2021-04-22 2022-10-31 에스케이하이닉스 주식회사 Host and computing system including thereof
KR102781288B1 (en) * 2022-05-11 2025-03-14 서울시립대학교 산학협력단 Method for processing instruction and processor therefor
CN117289991B (en) * 2022-06-14 2025-09-12 北京有竹居网络技术有限公司 Processor, method, device and storage medium for data processing
US20250168123A1 (en) * 2023-11-17 2025-05-22 International Business Machines Corporation Interrupt handling for received network packets
KR20250148223A (en) 2024-04-05 2025-10-14 주식회사 디노티시아 Method for optimizing vector index storage and apparatus for thereof

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US4722049A (en) * 1985-10-11 1988-01-26 Unisys Corporation Apparatus for out-of-order program execution
US7197625B1 (en) 1997-10-09 2007-03-27 Mips Technologies, Inc. Alignment and ordering of vector elements for single instruction multiple data processing
US7529907B2 (en) * 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
DE60139606D1 (en) * 2000-01-18 2009-10-01 Mips Tech Inc LOADING AND STORAGE OPERATIONS
US7162607B2 (en) * 2001-08-31 2007-01-09 Intel Corporation Apparatus and method for a data storage device with a plurality of randomly located data
US20130212353A1 (en) 2002-02-04 2013-08-15 Tibet MIMAR System for implementing vector look-up table operations in a SIMD processor
JP3659252B2 (en) * 2003-03-28 2005-06-15 セイコーエプソン株式会社 Vector data address reference method and vector processor
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US20070150697A1 (en) 2005-05-10 2007-06-28 Telairity Semiconductor, Inc. Vector processor with multi-pipe vector block matching
US10387151B2 (en) * 2007-12-31 2019-08-20 Intel Corporation Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US8060724B2 (en) * 2008-08-15 2011-11-15 Freescale Semiconductor, Inc. Provision of extended addressing modes in a single instruction multiple data (SIMD) data processor
CN102200905A (en) * 2010-03-26 2011-09-28 Mips技术公司 Microprocessor with compact instruction set architecture
US20120254591A1 (en) * 2011-04-01 2012-10-04 Hughes Christopher J Systems, apparatuses, and methods for stride pattern gathering of data elements and stride pattern scattering of data elements
WO2013095653A1 (en) * 2011-12-23 2013-06-27 Intel Corporation Systems, apparatuses, and methods for performing a conversion of a writemask register to a list of index values in a vector register
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US20140189322A1 (en) 2012-12-28 2014-07-03 Elmoustapha Ould-Ahmed-Vall Systems, Apparatuses, and Methods for Masking Usage Counting

Also Published As

Publication number Publication date
BR112017010956A2 (en) 2018-02-14
CN107003846A (en) 2017-08-01
EP3238026A1 (en) 2017-11-01
TWI617978B (en) 2018-03-11
KR102463858B1 (en) 2022-11-03
KR20170097626A (en) 2017-08-28
WO2016105755A1 (en) 2016-06-30
EP3238026B1 (en) 2019-11-20
EP3238026A4 (en) 2018-08-01
JP6711480B2 (en) 2020-06-17
CN107003846B (en) 2021-02-26
JP2018500660A (en) 2018-01-11
US9830151B2 (en) 2017-11-28
US20160179526A1 (en) 2016-06-23
TW201640331A (en) 2016-11-16

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