[go: up one dir, main page]

SG11201608934PA - Apparatuses and methods for performing multiple memory operations - Google Patents

Apparatuses and methods for performing multiple memory operations

Info

Publication number
SG11201608934PA
SG11201608934PA SG11201608934PA SG11201608934PA SG11201608934PA SG 11201608934P A SG11201608934P A SG 11201608934PA SG 11201608934P A SG11201608934P A SG 11201608934PA SG 11201608934P A SG11201608934P A SG 11201608934PA SG 11201608934P A SG11201608934P A SG 11201608934PA
Authority
SG
Singapore
Prior art keywords
apparatuses
methods
multiple memory
memory operations
performing multiple
Prior art date
Application number
SG11201608934PA
Inventor
Daniele Balluchi
Corrado Villa
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201608934PA publication Critical patent/SG11201608934PA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0061—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0064—Verifying circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0097—Erasing, e.g. resetting, circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Memory System (AREA)
SG11201608934PA 2014-05-06 2015-05-04 Apparatuses and methods for performing multiple memory operations SG11201608934PA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/270,944 US9384830B2 (en) 2014-05-06 2014-05-06 Apparatuses and methods for performing multiple memory operations
PCT/US2015/029108 WO2015171522A1 (en) 2014-05-06 2015-05-04 Apparatuses and methods for performing multiple memory operations

Publications (1)

Publication Number Publication Date
SG11201608934PA true SG11201608934PA (en) 2016-11-29

Family

ID=54368416

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201608934PA SG11201608934PA (en) 2014-05-06 2015-05-04 Apparatuses and methods for performing multiple memory operations

Country Status (8)

Country Link
US (5) US9384830B2 (en)
EP (1) EP3140833A4 (en)
JP (2) JP6434535B2 (en)
KR (2) KR101935119B1 (en)
CN (2) CN110751973A (en)
SG (1) SG11201608934PA (en)
TW (1) TWI576841B (en)
WO (1) WO2015171522A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112151097A (en) * 2019-06-27 2020-12-29 美光科技公司 Apparatus and method for performing simultaneous access operations on different groups of memory cells

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9384830B2 (en) * 2014-05-06 2016-07-05 Micron Technology, Inc. Apparatuses and methods for performing multiple memory operations
US9607705B1 (en) * 2015-09-04 2017-03-28 Micron Technology, Inc. Apparatuses and methods for charging a global access line prior to accessing a memory
US9583160B1 (en) 2015-09-04 2017-02-28 Micron Technology, Inc. Apparatuses including multiple read modes and methods for same
CN107564563B (en) * 2016-06-30 2020-06-09 华邦电子股份有限公司 Memory device and method of operating the same
EP3607023B1 (en) 2017-04-06 2023-06-07 Nissan Chemical America Corporation Hydrocarbon formation treatment micellar solutions
US11210019B2 (en) 2017-08-23 2021-12-28 Micron Technology, Inc. Memory with virtual page size
US10394456B2 (en) 2017-08-23 2019-08-27 Micron Technology, Inc. On demand memory page size
JP2021006595A (en) 2017-09-13 2021-01-21 日産化学株式会社 Crude oil recovery chemical
MX2020004470A (en) 2017-11-03 2020-09-03 Nissan Chemical America Corp Using brine resistant silicon dioxide nanoparticle dispersions to improve oil recovery.
US10467158B2 (en) 2017-11-29 2019-11-05 Micron Technology, Inc. Apparatuses and methods including memory commands for semiconductor memories
US11360704B2 (en) 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
CN115516566A (en) * 2020-03-24 2022-12-23 美光科技公司 Memory device having a one-transistor driver and method of operating the same
KR20220013719A (en) 2020-07-27 2022-02-04 에스케이하이닉스 주식회사 Nonvolatile memory apparatus performing consecutive access operations and an operation method thereof
JP2022049553A (en) 2020-09-16 2022-03-29 キオクシア株式会社 Semiconductor device and method
JP2022049552A (en) 2020-09-16 2022-03-29 キオクシア株式会社 Semiconductor device and method
WO2022174367A1 (en) 2021-02-18 2022-08-25 Micron Technology, Inc. Improved implicit ordered command handling
US12050773B2 (en) * 2021-08-12 2024-07-30 Micron Technology, Inc. Completion flag for memory operations
US12254300B2 (en) * 2022-04-06 2025-03-18 SambaNova Systems, Inc. Merging buffer access operations in a coarse-grained reconfigurable computing system

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2565104B2 (en) * 1993-08-13 1996-12-18 日本電気株式会社 Virtual ground type semiconductor memory device
JPH07169288A (en) * 1993-12-13 1995-07-04 Hitachi Ltd Batch erasable non-volatile memory device
JP3976839B2 (en) * 1996-07-09 2007-09-19 株式会社ルネサステクノロジ Nonvolatile memory system and nonvolatile semiconductor memory
US6453370B1 (en) * 1998-11-16 2002-09-17 Infineion Technologies Ag Using of bank tag registers to avoid a background operation collision in memory systems
JP2000163965A (en) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp Synchronous semiconductor memory device
US6061285A (en) * 1999-11-10 2000-05-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device capable of executing earlier command operation in test mode
US6240040B1 (en) 2000-03-15 2001-05-29 Advanced Micro Devices, Inc. Multiple bank simultaneous operation for a flash memory
JP2007200545A (en) * 2001-01-12 2007-08-09 Renesas Technology Corp Nonvolatile semiconductor memory device
JP2002319287A (en) * 2001-04-20 2002-10-31 Fujitsu Ltd Non-volatile semiconductor memory
US6584034B1 (en) 2001-04-23 2003-06-24 Aplus Flash Technology Inc. Flash memory array structure suitable for multiple simultaneous operations
US20060026260A1 (en) 2004-07-28 2006-02-02 Mullen Jeffrey T Method of communicating between web applications and local client application while maintaining remote user session
US7120051B2 (en) * 2004-12-14 2006-10-10 Sandisk Corporation Pipelined programming of non-volatile memories using early data
US7251160B2 (en) * 2005-03-16 2007-07-31 Sandisk Corporation Non-volatile memory and method with power-saving read and program-verify operations
US7319612B2 (en) 2005-05-18 2008-01-15 Intel Corporation Performing multiple read operations via a single read command
US7212447B2 (en) 2005-08-04 2007-05-01 Micron Technology, Inc. NAND flash memory cell programming
US8134866B2 (en) * 2006-04-06 2012-03-13 Samsung Electronics Co., Ltd. Phase change memory devices and systems, and related programming methods
KR100784866B1 (en) 2006-12-13 2007-12-14 삼성전자주식회사 Nonvolatile Memory Device and Memory Card Including It That Reduces Write Time
US7965546B2 (en) * 2007-04-26 2011-06-21 Super Talent Electronics, Inc. Synchronous page-mode phase-change memory with ECC and RAM cache
KR20100123136A (en) * 2009-05-14 2010-11-24 삼성전자주식회사 Nonvolatile memory device
US7885099B2 (en) 2007-09-18 2011-02-08 Intel Corporation Adaptive wordline programming bias of a phase change memory
JP5049814B2 (en) * 2008-02-14 2012-10-17 株式会社東芝 Data writing method for nonvolatile semiconductor memory device
US8205031B2 (en) * 2008-08-19 2012-06-19 Sonix Technology Co., Ltd. Memory management system and method thereof
KR20100049809A (en) 2008-11-04 2010-05-13 삼성전자주식회사 Method of erasing a non-volatile memory device
US9128699B2 (en) * 2008-12-22 2015-09-08 Intel Corporation Method and system for queuing transfers of multiple non-contiguous address ranges with a single command
US8078848B2 (en) * 2009-01-09 2011-12-13 Micron Technology, Inc. Memory controller having front end and back end channels for modifying commands
KR20100101449A (en) * 2009-03-09 2010-09-17 삼성전자주식회사 Memory device, mask data trasmitting method and input data aligning method of thereof
KR20110013868A (en) 2009-08-04 2011-02-10 삼성전자주식회사 Multiprocessor system with multi-command set operation and priority processing
US20120117317A1 (en) 2009-08-20 2012-05-10 Rambus Inc. Atomic memory device
US9013911B2 (en) * 2011-06-23 2015-04-21 Crossbar, Inc. Memory array architecture with two-terminal memory cells
US8258848B2 (en) * 2010-09-07 2012-09-04 Taiwan Semiconductor Manufacturing Co., Ltd. Level shifter
US9465728B2 (en) * 2010-11-03 2016-10-11 Nvidia Corporation Memory controller adaptable to multiple memory devices
US8737138B2 (en) * 2010-11-18 2014-05-27 Micron Technology, Inc. Memory instruction including parameter to affect operating condition of memory
KR101399230B1 (en) * 2010-12-08 2014-05-27 에스케이하이닉스 주식회사 Programming method of nonvolatile memory device and the nonvolatile memory device
US8547726B2 (en) * 2011-04-04 2013-10-01 Kabushiki Kaisha Toshiba Semiconductor memory device and controlling method thereof
US8607089B2 (en) * 2011-05-19 2013-12-10 Intel Corporation Interface for storage device access over memory bus
US9104547B2 (en) * 2011-08-03 2015-08-11 Micron Technology, Inc. Wear leveling for a memory device
US9087595B2 (en) * 2012-04-20 2015-07-21 Aplus Flash Technology, Inc. Shielding 2-cycle half-page read and program schemes for advanced NAND flash design
JP5853843B2 (en) 2012-04-25 2016-02-09 ソニー株式会社 Storage control device, storage device, and processing method therefor
KR101964261B1 (en) * 2012-05-17 2019-04-01 삼성전자주식회사 Magenetic Random Access Memory
KR20140043560A (en) * 2012-09-24 2014-04-10 삼성전자주식회사 Semiconductor memory device storing memory characteristic information, memory module and memory system having the same and operating method thereof
KR102167689B1 (en) 2014-04-11 2020-10-20 삼성디스플레이 주식회사 Display panel and display device having the same
US9384830B2 (en) * 2014-05-06 2016-07-05 Micron Technology, Inc. Apparatuses and methods for performing multiple memory operations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112151097A (en) * 2019-06-27 2020-12-29 美光科技公司 Apparatus and method for performing simultaneous access operations on different groups of memory cells

Also Published As

Publication number Publication date
US10068649B2 (en) 2018-09-04
US20170256319A1 (en) 2017-09-07
JP2019049976A (en) 2019-03-28
US20160351263A1 (en) 2016-12-01
CN106463172B (en) 2019-10-08
US10311957B2 (en) 2019-06-04
KR102097228B1 (en) 2020-05-28
US20150325288A1 (en) 2015-11-12
JP6853611B2 (en) 2021-03-31
EP3140833A4 (en) 2018-01-10
KR20160144415A (en) 2016-12-16
WO2015171522A1 (en) 2015-11-12
TW201611002A (en) 2016-03-16
CN110751973A (en) 2020-02-04
KR101935119B1 (en) 2019-01-03
US9384830B2 (en) 2016-07-05
US10529428B2 (en) 2020-01-07
US20190244667A1 (en) 2019-08-08
JP6434535B2 (en) 2018-12-05
KR20180137601A (en) 2018-12-27
TWI576841B (en) 2017-04-01
CN106463172A (en) 2017-02-22
EP3140833A1 (en) 2017-03-15
US20190035470A1 (en) 2019-01-31
US9685234B2 (en) 2017-06-20
JP2017524997A (en) 2017-08-31

Similar Documents

Publication Publication Date Title
IL287113A (en) Smyd inhibitors
ZA201804070B (en) Eif4-a-inhibiting compounds and methods related thereto
SG11201608934PA (en) Apparatuses and methods for performing multiple memory operations
PL3215147T3 (en) Neuro-attenuating norketamine compounds and methods
SG10202002324SA (en) Methods for transduction and cell processing
IL248895A0 (en) Phosphatidylinositol -kinase inhibitors
GB201413086D0 (en) Methods
SG10201500398VA (en) Systems and Methods for Creating and Evaluating Experiments
SG11201704473WA (en) New methods and uses
IL251107A0 (en) Compounds and methods
SG11201604447QA (en) Systems and methods for reducing scouring
GB201417185D0 (en) Apparatus and methods
GB201403470D0 (en) Method
GB201408745D0 (en) Methods
PL3134581T3 (en) Method and soil-stabilizing means
GB201702377D0 (en) Access apparatus
GB201416082D0 (en) Method and uses
GB201415685D0 (en) Methods
GB201415778D0 (en) Storage apparatus
GB201421109D0 (en) Insert and method
GB201414433D0 (en) Data distribution method
GB201418154D0 (en) Inhibitors
GB201401023D0 (en) Apparatus and methods
GB201400360D0 (en) Enclosure and method
GB201415559D0 (en) Storage apparatus