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SG11201607286TA - Method for manufacturing bonded wafer - Google Patents

Method for manufacturing bonded wafer

Info

Publication number
SG11201607286TA
SG11201607286TA SG11201607286TA SG11201607286TA SG11201607286TA SG 11201607286T A SG11201607286T A SG 11201607286TA SG 11201607286T A SG11201607286T A SG 11201607286TA SG 11201607286T A SG11201607286T A SG 11201607286TA SG 11201607286T A SG11201607286T A SG 11201607286TA
Authority
SG
Singapore
Prior art keywords
bonded wafer
manufacturing bonded
manufacturing
wafer
bonded
Prior art date
Application number
SG11201607286TA
Inventor
Norihiro Kobayashi
Hiroji Aga
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201607286TA publication Critical patent/SG11201607286TA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041Cleaning
    • H01L21/02043Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052Wet cleaning only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
SG11201607286TA 2014-03-18 2015-02-12 Method for manufacturing bonded wafer SG11201607286TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014054427A JP6036732B2 (en) 2014-03-18 2014-03-18 Manufacturing method of bonded wafer
PCT/JP2015/000635 WO2015141121A1 (en) 2014-03-18 2015-02-12 Method for manufacturing laminated wafer

Publications (1)

Publication Number Publication Date
SG11201607286TA true SG11201607286TA (en) 2016-10-28

Family

ID=54144113

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201607286TA SG11201607286TA (en) 2014-03-18 2015-02-12 Method for manufacturing bonded wafer

Country Status (8)

Country Link
US (1) US9773694B2 (en)
EP (1) EP3104395B1 (en)
JP (1) JP6036732B2 (en)
KR (1) KR102361311B1 (en)
CN (1) CN106062924B (en)
SG (1) SG11201607286TA (en)
TW (1) TWI604502B (en)
WO (1) WO2015141121A1 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3051968B1 (en) 2016-05-25 2018-06-01 Soitec METHOD FOR MANUFACTURING HIGH RESISTIVITY SEMICONDUCTOR SUBSTRATE
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
JP6531743B2 (en) * 2016-09-27 2019-06-19 信越半導体株式会社 Method of manufacturing bonded SOI wafer
JP6686962B2 (en) * 2017-04-25 2020-04-22 信越半導体株式会社 Method for manufacturing bonded wafer
JP6760245B2 (en) * 2017-11-06 2020-09-23 信越半導体株式会社 Method for manufacturing an SOI wafer having a thin film SOI layer
JP7088125B2 (en) * 2019-05-14 2022-06-21 信越半導体株式会社 Coating thickness measurement method and grinding method
JP7251419B2 (en) * 2019-09-11 2023-04-04 信越半導体株式会社 Bonded SOI wafer manufacturing method
US11282739B2 (en) * 2019-12-13 2022-03-22 Globalwafers Co., Ltd. Methods for removing an oxide film from a SOI structure and methods for preparing a SOI structure
FR3106236B1 (en) * 2020-01-15 2021-12-10 Soitec Silicon On Insulator Manufacturing process of an image sensor
JP2021166267A (en) * 2020-04-08 2021-10-14 信越半導体株式会社 Manufacturing method for bonded soi wafer
JP7711625B2 (en) * 2022-05-17 2025-07-23 信越半導体株式会社 Silicon wafer heat treatment method
JP2024168899A (en) * 2023-05-25 2024-12-05 信越半導体株式会社 High mobility substrate having .DELTA.-doped layer and method for manufacturing high mobility substrate

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (en) 1991-09-18 1993-10-29 Commissariat Energie Atomique PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL.
JPH11307472A (en) 1998-04-23 1999-11-05 Shin Etsu Handotai Co Ltd Soi wafer and manufacture soi by hydrogen ion releasing method
JP2000124092A (en) * 1998-10-16 2000-04-28 Shin Etsu Handotai Co Ltd Manufacture of soi wafer by hydrogen-ion implantation stripping method and soi wafer manufactured thereby
JP4526818B2 (en) * 2001-07-17 2010-08-18 信越半導体株式会社 Manufacturing method of bonded wafer
JP4509488B2 (en) * 2003-04-02 2010-07-21 株式会社Sumco Manufacturing method of bonded substrate
CN100437912C (en) * 2003-08-25 2008-11-26 松下电器产业株式会社 Method for forming impurity-introduced layer and method for manufacturing device
JP4552856B2 (en) * 2003-09-05 2010-09-29 株式会社Sumco Manufacturing method of SOI wafer
EP1710836A4 (en) * 2004-01-30 2010-08-18 Sumco Corp Method for manufacturing soi wafer
KR101440930B1 (en) * 2007-04-20 2014-09-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Manufacturing method of SOI substrate
JP5245380B2 (en) * 2007-06-21 2013-07-24 信越半導体株式会社 Manufacturing method of SOI wafer
JP5135935B2 (en) 2007-07-27 2013-02-06 信越半導体株式会社 Manufacturing method of bonded wafer
FR2944645B1 (en) * 2009-04-21 2011-09-16 Soitec Silicon On Insulator METHOD FOR SLITTING A SILICON SUBSTRATE ON INSULATION
FR2957716B1 (en) * 2010-03-18 2012-10-05 Soitec Silicon On Insulator METHOD FOR FINISHING A SEMICONDUCTOR TYPE SUBSTRATE ON INSULATION
JP5703920B2 (en) 2011-04-13 2015-04-22 信越半導体株式会社 Manufacturing method of bonded wafer
JP5927894B2 (en) * 2011-12-15 2016-06-01 信越半導体株式会社 Manufacturing method of SOI wafer
JP2013143407A (en) 2012-01-06 2013-07-22 Shin Etsu Handotai Co Ltd Method of manufacturing laminated soi wafer
JP5991284B2 (en) * 2013-08-23 2016-09-14 信越半導体株式会社 Heat treatment method for silicon wafer

Also Published As

Publication number Publication date
TWI604502B (en) 2017-11-01
JP6036732B2 (en) 2016-11-30
CN106062924A (en) 2016-10-26
EP3104395A4 (en) 2017-10-04
US20160365273A1 (en) 2016-12-15
WO2015141121A1 (en) 2015-09-24
JP2015177150A (en) 2015-10-05
KR102361311B1 (en) 2022-02-10
KR20160134661A (en) 2016-11-23
EP3104395A1 (en) 2016-12-14
CN106062924B (en) 2019-02-15
TW201546875A (en) 2015-12-16
EP3104395B1 (en) 2020-09-09
US9773694B2 (en) 2017-09-26

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