SG11201402727WA - Polymorphic heterogeneous multi-core architecture - Google Patents
Polymorphic heterogeneous multi-core architectureInfo
- Publication number
- SG11201402727WA SG11201402727WA SG11201402727WA SG11201402727WA SG11201402727WA SG 11201402727W A SG11201402727W A SG 11201402727WA SG 11201402727W A SG11201402727W A SG 11201402727WA SG 11201402727W A SG11201402727W A SG 11201402727WA SG 11201402727W A SG11201402727W A SG 11201402727WA
- Authority
- SG
- Singapore
- Prior art keywords
- core architecture
- heterogeneous multi
- polymorphic
- polymorphic heterogeneous
- architecture
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/3009—Thread control instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/3826—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
- G06F9/3828—Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage with global bypass, e.g. between pipelines, between clusters
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
- G06F9/3858—Result writeback, i.e. updating the architectural state or memory
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
- G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
- G06F9/3891—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute organised in groups of units sharing resources, e.g. clusters
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5061—Partitioning or combining of resources
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2209/00—Indexing scheme relating to G06F9/00
- G06F2209/50—Indexing scheme relating to G06F9/50
- G06F2209/5012—Processor sets
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/505—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the load
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Advance Control (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161565559P | 2011-12-01 | 2011-12-01 | |
| PCT/SG2012/000454 WO2013081556A1 (en) | 2011-12-01 | 2012-12-03 | Polymorphic heterogeneous multi-core architecture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11201402727WA true SG11201402727WA (en) | 2014-06-27 |
Family
ID=48535871
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11201402727WA SG11201402727WA (en) | 2011-12-01 | 2012-12-03 | Polymorphic heterogeneous multi-core architecture |
| SG10201604445RA SG10201604445RA (en) | 2011-12-01 | 2012-12-03 | Polymorphic heterogeneous multi-core architecture |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG10201604445RA SG10201604445RA (en) | 2011-12-01 | 2012-12-03 | Polymorphic heterogeneous multi-core architecture |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US9690620B2 (en) |
| CN (1) | CN104011705A (en) |
| SG (2) | SG11201402727WA (en) |
| WO (1) | WO2013081556A1 (en) |
Families Citing this family (38)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130117168A1 (en) | 2011-11-04 | 2013-05-09 | Mark Henrik Sandstrom | Maximizing Throughput of Multi-user Parallel Data Processing Systems |
| US8789065B2 (en) | 2012-06-08 | 2014-07-22 | Throughputer, Inc. | System and method for input data load adaptive parallel processing |
| US8745626B1 (en) * | 2012-12-17 | 2014-06-03 | Throughputer, Inc. | Scheduling application instances to configurable processing cores based on application requirements and resource specification |
| US9448847B2 (en) | 2011-07-15 | 2016-09-20 | Throughputer, Inc. | Concurrent program execution optimization |
| US10140129B2 (en) | 2012-12-28 | 2018-11-27 | Intel Corporation | Processing core having shared front end unit |
| US9361116B2 (en) | 2012-12-28 | 2016-06-07 | Intel Corporation | Apparatus and method for low-latency invocation of accelerators |
| US9417873B2 (en) | 2012-12-28 | 2016-08-16 | Intel Corporation | Apparatus and method for a hybrid latency-throughput processor |
| US10346195B2 (en) | 2012-12-29 | 2019-07-09 | Intel Corporation | Apparatus and method for invocation of a multi threaded accelerator |
| US9361113B2 (en) * | 2013-04-24 | 2016-06-07 | Globalfoundries Inc. | Simultaneous finish of stores and dependent loads |
| US9792252B2 (en) | 2013-05-31 | 2017-10-17 | Microsoft Technology Licensing, Llc | Incorporating a spatial array into one or more programmable processor cores |
| GB2514618B (en) * | 2013-05-31 | 2020-11-11 | Advanced Risc Mach Ltd | Data processing systems |
| CN104462007B (en) * | 2013-09-22 | 2018-10-02 | 南京中兴新软件有限责任公司 | The method and device of buffer consistency between realization multinuclear |
| US9880953B2 (en) | 2015-01-05 | 2018-01-30 | Tuxera Corporation | Systems and methods for network I/O based interrupt steering |
| CN105045564A (en) * | 2015-06-26 | 2015-11-11 | 季锦诚 | Front end dynamic sharing method in graphics processor |
| US9952867B2 (en) | 2015-06-26 | 2018-04-24 | Microsoft Technology Licensing, Llc | Mapping instruction blocks based on block size |
| US10409606B2 (en) | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Verifying branch targets |
| US11755484B2 (en) * | 2015-06-26 | 2023-09-12 | Microsoft Technology Licensing, Llc | Instruction block allocation |
| US20160378491A1 (en) * | 2015-06-26 | 2016-12-29 | Microsoft Technology Licensing, Llc | Determination of target location for transfer of processor control |
| US10191747B2 (en) | 2015-06-26 | 2019-01-29 | Microsoft Technology Licensing, Llc | Locking operand values for groups of instructions executed atomically |
| US10175988B2 (en) | 2015-06-26 | 2019-01-08 | Microsoft Technology Licensing, Llc | Explicit instruction scheduler state information for a processor |
| US9720693B2 (en) | 2015-06-26 | 2017-08-01 | Microsoft Technology Licensing, Llc | Bulk allocation of instruction blocks to a processor instruction window |
| US10409599B2 (en) * | 2015-06-26 | 2019-09-10 | Microsoft Technology Licensing, Llc | Decoding information about a group of instructions including a size of the group of instructions |
| US9946548B2 (en) * | 2015-06-26 | 2018-04-17 | Microsoft Technology Licensing, Llc | Age-based management of instruction blocks in a processor instruction window |
| US10169044B2 (en) * | 2015-06-26 | 2019-01-01 | Microsoft Technology Licensing, Llc | Processing an encoding format field to interpret header information regarding a group of instructions |
| US10346168B2 (en) | 2015-06-26 | 2019-07-09 | Microsoft Technology Licensing, Llc | Decoupled processor instruction window and operand buffer |
| US20160378488A1 (en) * | 2015-06-26 | 2016-12-29 | Microsoft Technology Licensing, Llc | Access to target address |
| US9940136B2 (en) | 2015-06-26 | 2018-04-10 | Microsoft Technology Licensing, Llc | Reuse of decoded instructions |
| US10180840B2 (en) | 2015-09-19 | 2019-01-15 | Microsoft Technology Licensing, Llc | Dynamic generation of null instructions |
| US20170083318A1 (en) * | 2015-09-19 | 2017-03-23 | Microsoft Technology Licensing, Llc | Configuring modes of processor operation |
| US10095519B2 (en) | 2015-09-19 | 2018-10-09 | Microsoft Technology Licensing, Llc | Instruction block address register |
| US10198263B2 (en) | 2015-09-19 | 2019-02-05 | Microsoft Technology Licensing, Llc | Write nullification |
| JP6167193B1 (en) * | 2016-01-25 | 2017-07-19 | 株式会社ドワンゴ | Processor |
| US11106467B2 (en) | 2016-04-28 | 2021-08-31 | Microsoft Technology Licensing, Llc | Incremental scheduler for out-of-order block ISA processors |
| US20180032335A1 (en) * | 2016-07-31 | 2018-02-01 | Microsoft Technology Licensing, Llc | Transactional register file for a processor |
| CN107291535B (en) * | 2017-05-18 | 2020-08-14 | 深圳先进技术研究院 | Resource management method and resource management device of multi-core system and electronic device |
| US11042381B2 (en) | 2018-12-08 | 2021-06-22 | Microsoft Technology Licensing, Llc | Register renaming-based techniques for block-based processors |
| CN113568665B (en) * | 2020-04-29 | 2023-11-17 | 北京希姆计算科技有限公司 | Data processing device |
| CN116300503B (en) * | 2023-03-29 | 2023-08-18 | 广州市平可捷信息科技有限公司 | Multithreading intelligent furniture control method and system |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7398374B2 (en) * | 2002-02-27 | 2008-07-08 | Hewlett-Packard Development Company, L.P. | Multi-cluster processor for processing instructions of one or more instruction threads |
| US7673295B1 (en) * | 2004-04-27 | 2010-03-02 | Sun Microsystems, Inc. | System and method for compile-time non-concurrency analysis |
| TWI348652B (en) * | 2005-10-17 | 2011-09-11 | Via Tech Inc | Driver assisted asynchronous command processing |
| US7948500B2 (en) * | 2007-06-07 | 2011-05-24 | Nvidia Corporation | Extrapolation of nonresident mipmap data using resident mipmap data |
| CN101566955A (en) * | 2008-04-21 | 2009-10-28 | 安捷伦科技有限公司 | Multithreading icon programming system |
| US8347301B2 (en) * | 2008-06-30 | 2013-01-01 | Intel Corporation | Device, system, and method of scheduling tasks of a multithreaded application |
| US8261273B2 (en) * | 2008-09-02 | 2012-09-04 | International Business Machines Corporation | Assigning threads and data of computer program within processor having hardware locality groups |
| US20110040772A1 (en) * | 2009-08-17 | 2011-02-17 | Chen-Yu Sheu | Capability Based Semantic Search System |
| US8539201B2 (en) * | 2009-11-04 | 2013-09-17 | International Business Machines Corporation | Transposing array data on SIMD multi-core processor architectures |
-
2012
- 2012-12-03 SG SG11201402727WA patent/SG11201402727WA/en unknown
- 2012-12-03 SG SG10201604445RA patent/SG10201604445RA/en unknown
- 2012-12-03 CN CN201280059336.4A patent/CN104011705A/en active Pending
- 2012-12-03 US US14/360,263 patent/US9690620B2/en not_active Expired - Fee Related
- 2012-12-03 WO PCT/SG2012/000454 patent/WO2013081556A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US20140331236A1 (en) | 2014-11-06 |
| WO2013081556A1 (en) | 2013-06-06 |
| CN104011705A (en) | 2014-08-27 |
| US9690620B2 (en) | 2017-06-27 |
| SG10201604445RA (en) | 2016-07-28 |
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