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SG10201510137TA - Semiconductor device and method of forming no-flow underfillmaterial around vertical interconnect structure - Google Patents

Semiconductor device and method of forming no-flow underfillmaterial around vertical interconnect structure

Info

Publication number
SG10201510137TA
SG10201510137TA SG10201510137TA SG10201510137TA SG10201510137TA SG 10201510137T A SG10201510137T A SG 10201510137TA SG 10201510137T A SG10201510137T A SG 10201510137TA SG 10201510137T A SG10201510137T A SG 10201510137TA SG 10201510137T A SG10201510137T A SG 10201510137TA
Authority
SG
Singapore
Prior art keywords
underfillmaterial
forming
flow
semiconductor device
interconnect structure
Prior art date
Application number
SG10201510137TA
Inventor
Rui Huang
Heap Hoe Kuan
Yaojian Lin
Seng Guan Chow
Original Assignee
Stats Chippac Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd filed Critical Stats Chippac Ltd
Publication of SG10201510137TA publication Critical patent/SG10201510137TA/en

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
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