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RU94033708A - Method for optimal generation of visual picture - Google Patents

Method for optimal generation of visual picture

Info

Publication number
RU94033708A
RU94033708A RU94033708/09A RU94033708A RU94033708A RU 94033708 A RU94033708 A RU 94033708A RU 94033708/09 A RU94033708/09 A RU 94033708/09A RU 94033708 A RU94033708 A RU 94033708A RU 94033708 A RU94033708 A RU 94033708A
Authority
RU
Russia
Prior art keywords
cost
hardware
frames
cis
implementation
Prior art date
Application number
RU94033708/09A
Other languages
Russian (ru)
Other versions
RU2045095C1 (en
Inventor
В.О. Гроппен
Ru]
А.В. Гницевич
Сун Хюк Хон
Ua]
Kr]
Original Assignee
В.О. Гроппен
Ru]
А.В. Гницевич
Сун Хюк Хон
Ua]
Kr]
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by В.О. Гроппен, Ru], А.В. Гницевич, Сун Хюк Хон, Ua], Kr] filed Critical В.О. Гроппен
Priority to RU9494033708A priority Critical patent/RU2045095C1/en
Priority to KR1019940025753A priority patent/KR960015503A/en
Priority to KR1019940025754A priority patent/KR960015504A/en
Priority to PCT/RU1995/000203 priority patent/WO1996008789A1/en
Application granted granted Critical
Publication of RU2045095C1 publication Critical patent/RU2045095C1/en
Publication of RU94033708A publication Critical patent/RU94033708A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)
  • Nitrogen And Oxygen Or Sulfur-Condensed Heterocyclic Ring Systems (AREA)
  • Television Signal Processing For Recording (AREA)
  • Processing Or Creating Images (AREA)
  • Multi Processors (AREA)

Abstract

FIELD: computer engineering. SUBSTANCE: method involves continuous generation of dot array which corresponds to given sequence of frames by means of uniform processors, which number n conform to equation, where k is number of frames per second, p is number of dots in frame, tis time for generation (processing) one dot, Cis cost of shared components of circuit, Cis cost of single processor and hardware which is devoted to it. Invention contains description of hardware implementation of device which uses principle of parallel processing input information when dot array is processed. It has external memory unit, control unit, input commutator, channel commutators with gates, two buffer memory units, uniform processors, screen memory unit. EFFECT: increased speed, decreased cost of hardware. 1 dwg

Claims (1)

Изобретение относится к вычислительной технике и предназначено для цифрового оптимального синтеза и воспроизведения изображения, звукового сопровождения и других восприятий с возможностью записи на носитель или вывода на экран. Способ заключается в непрерывном восстановлении массива пикселей, образующих заданную последовательность кадров, с помощью однородных процессоров, число п которых выбирается по формуле, указаннолой в описании изобретения. Способ позволяет повысить быстродействие и минимизировать стоимость аппаратных затрат при его осуществлении. Приведен пример осуществления способа устройством, построенным на принципе распараллеливания входной информации при обработке пикселей, включающим в себя внешнюю память, устройство управления, входной коммутатор, канальные коммутаторы с ключами, две буферные памяти, однородные процессоры, память экрана. 1 ил.The invention relates to computer technology and is intended for digital optimal synthesis and reproduction of images, sound and other perceptions with the ability to record on a medium or display. The method consists in continuously restoring an array of pixels forming a given sequence of frames using homogeneous processors, the number n of which is selected according to the formula indicated in the description of the invention. The method improves the speed and minimize the cost of hardware costs during its implementation. An example of the implementation of the method by a device based on the principle of parallelizing input information during pixel processing, including external memory, a control device, an input switch, channel switches with keys, two buffer memories, homogeneous processors, a screen memory, is given. 1 ill.
RU9494033708A 1994-09-14 1994-09-14 Process of optimum formation of visible image RU2045095C1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
RU9494033708A RU2045095C1 (en) 1994-09-14 1994-09-14 Process of optimum formation of visible image
KR1019940025753A KR960015503A (en) 1994-09-14 1994-10-07 Visual information processing device
KR1019940025754A KR960015504A (en) 1994-09-14 1994-10-07 Optimal Processing of Visual Information
PCT/RU1995/000203 WO1996008789A1 (en) 1994-09-14 1995-09-14 Method of optimizing the structure of a visual image

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
RU9494033708A RU2045095C1 (en) 1994-09-14 1994-09-14 Process of optimum formation of visible image

Publications (2)

Publication Number Publication Date
RU2045095C1 RU2045095C1 (en) 1995-09-27
RU94033708A true RU94033708A (en) 1996-07-20

Family

ID=20160495

Family Applications (1)

Application Number Title Priority Date Filing Date
RU9494033708A RU2045095C1 (en) 1994-09-14 1994-09-14 Process of optimum formation of visible image

Country Status (3)

Country Link
KR (2) KR960015504A (en)
RU (1) RU2045095C1 (en)
WO (1) WO1996008789A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2191425C2 (en) * 2000-04-03 2002-10-20 Северо-Кавказский региональный центр информатизации высшей школы Concurrent data processing optimization method for minimizing processing time
RU2191424C2 (en) * 2000-04-03 2002-10-20 Северо-Кавказский региональный центр информатизации высшей школы Method for optimizing concurrent data processing to minimize its cost
RU2229745C2 (en) * 2002-07-24 2004-05-27 Игнатущенко Владислав Валентинович Concurrent active video computing system
RU2212709C1 (en) * 2002-10-03 2003-09-20 Общество с ограниченной ответственностью "Р.Т.С.-Сервис" Method for processing object-oriented interactive video data
RU2212710C1 (en) * 2002-10-03 2003-09-20 Общество с ограниченной ответственностью "Мир Сетей" Method for coding coordinates of video image moving on computer monitor screen
RU2225035C1 (en) * 2003-04-21 2004-02-27 Общество с ограниченной ответственностью "Р.Т.С.-Сервис" Method for encoding coordinates of video image moving on computer monitor screen, device for decoding visual object encoded by this method, and system designed for visualizing active video by means of this device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4809347A (en) * 1986-07-18 1989-02-28 Hughes Aircraft Company Computer vision architecture
US4908751A (en) * 1987-10-15 1990-03-13 Smith Harry F Parallel data processor
SU1522240A1 (en) * 1988-07-21 1989-11-15 Институт автоматики и электрометрии СО АН СССР Image generator
SU1651299A1 (en) * 1989-02-13 1991-05-23 Киевский Политехнический Институт Им.50-Летия Великой Октябрьской Социалистической Революции Video information concurrent processing block
WO1993008525A2 (en) * 1991-10-24 1993-04-29 Intel Corporation Data processing system
GB9206126D0 (en) * 1992-03-20 1992-05-06 Maxys Circuit Technology Limit Parallel vector processor architecture

Also Published As

Publication number Publication date
KR960015503A (en) 1996-05-22
WO1996008789A1 (en) 1996-03-21
KR960015504A (en) 1996-05-22
RU2045095C1 (en) 1995-09-27

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