RU2819403C1 - Vector computing core - Google Patents

Abstract

FIELD: computer engineering.

SUBSTANCE: device comprises a data input buffer, an instruction memory unit, an instruction control unit, a memory device into which are introduced an input switch, data vector memory units, an output switch and an operand switch, a computing device, which includes an operation selection demultiplexer, an arithmetic-logic device, units for performing computationally complex data conversions and a result selection multiplexer, as well as an input data bus, an output data bus, an external control bus, an output control bus, and an output status bus.

EFFECT: increased efficiency due to pipeline processing of vector operations and expansion of set of solved scientific and technical problems.

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Description

TECHNICAL FIELD

The invention relates to the field of computer technology, in particular, to problem-oriented vector processors with a specialized instruction system and high-speed hardware implementation of computationally complex data transformations and can be used to build multi-core high-performance processors and computers based on them, designed to perform labor-intensive scientific algorithms -technical problems that can be parallelized based on data into a large number of independent subtasks.

BACKGROUND ART

A problem-oriented programmable computing module (VM) of multi-threaded processing for multi-stage multi-threaded processing of digital data and a processing method using this module are known (RU No. 2681365 C1, IPC G06F 15/80, G06F 15/16 declared 08/03/2018, published 03/06/2019 , Bull. No. 7), which contains C control units containing a dual-port command memory, a stack of cycles and subroutines, also contains a matrix containing shared memory, a command register, a short message bus, and processor elements, which in turn contain register memory. , shared memory access channels, a group of S operand reading ports, a group of M multi-input arithmetic-logical devices of the first level, a group of P multi-input arithmetic-logical devices of the second level, a selector of results of arithmetic-logical devices and data from memory, a group of X write ports to the register file, control bus and short message bus controller. The VM contains many identical processing elements (PEs) designed to execute the same processing program with different data. The problem orientation consists in choosing the composition of operations, memory volumes at different hierarchical levels of the VM, and the throughput of the communication network based on the computational properties of the target class of algorithms.

The disadvantage of such computing devices is the low data processing performance for performing labor-intensive scientific and technical tasks.

The reasons preventing the achievement of a technical result are that the command system and the set of functional nodes of the PE, which form the computing resource of the computer for multi-threaded processing, provide for the performance of only elementary logical and arithmetic operations with scalar operands. To obtain the results of computationally complex data transformations (CSDC), the computer uses subroutines that contain a large number of elementary operations and are performed for a long time.

A neural network processor is known (US 11586920 B2, IPC G06N 3/08, G06F 15/80, declared 01/21/2021, published 02/21/2023) containing many layers of a neural network, and the processor contains a matrix calculation unit configured so that for each of the plurality of neural network layers, receive a plurality of input weight values and a plurality of activation input data for the neural network layer, and generate a plurality of accumulated values based on the plurality of input weight values and the plurality of activation input data, and a vector computing unit coupled to the matrix computing unit and configured to to, for each of the plurality of neural network layers, apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer. This neural network processor is a highly specialized computer in which high-speed hardware-implemented blocks for matrix multiplication and operations with vectors are used to perform VSPD. The effectiveness of a highly specialized computer is achieved by choosing, when designing, the composition of the operations to be performed, movement routes, types and bit depth of the processed data, based solely on the characteristics of the algorithm being implemented.

The disadvantage of this device is the narrow range of scientific and technical problems that can be solved.

The reasons preventing the achievement of a technical result lie in the specialization of computational blocks focused on a limited class (group) of algorithms.

The closest device of the same purpose to the claimed invention, in terms of the totality of features, is the reconfigurable computing module (RU No. 168565 U1, IPC G06F 15/177, declared 11.21.2016, published 02.08.2017, Bulletin No. 4), adopted as a prototype, built on based on composite CPUs, and containing an external port for information exchange 4, a PCI-Express switch 1, an interface FPGA 2, a group of N computing FPGAs 3 ₁ 3 ₂ , ..., 3 _N , high-speed PCI-Express interfaces 5 and 6 ₁ , 6 ₂ , ..., 6 _N , unit 9 for operational configuration of the interface FPGA, power monitoring and control unit 15, monitoring unit 17, external monitoring and control port JTAG 11, interface FPGA configuration memory 16, bidirectional common bus 14, group of N computing VLSI 8 ₁ , 8 ₂ , ..., 8 _N , a group of N memories 10 ₁ , 10 ₂ , ..., 10 _N starting configurations of computing FPGAs, unit 13 for online reconfiguration of memories of starting configurations of computing FPGAs and synchronization unit 20. In this module, calculations are carried out on N composite computers containing a computing FPGA, a highly specialized computing VLSI and a memory of FPGA configurations. A highly specialized VLSI provides high performance for executing common VSPD application tasks for a group of applications, and the FPGA provides the ability to implement an increased number of applied tasks by implementing application-specific ones VSPD tasks.

The disadvantages of a reconfigurable VM are lower performance than that of highly specialized VMs and the high complexity of programming the FPGA that is part of the composite VM.

The reason preventing the achievement of a technical result is the use of a composite computer, including a highly specialized VLSI and an FPGA with configuration memory, to expand the variety of scientific and technical problems being solved.

OBJECTIVE OF THE INVENTION

The problem to be solved by the proposed invention is to create a high-performance problem-oriented computing core that performs calculations in the form of a programmable sequence of vector operations performed using high-speed devices with hardware implementation of computationally complex data transformations, and is intended for building computers that provide the ability solving a target set of labor-intensive scientific and technical problems.

The technical result of the proposed invention is to increase productivity due to pipeline processing of vector operations and expand the variety of scientific and technical problems that can be solved.

BRIEF DESCRIPTION OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the vector computing core contains a data input buffer 1, an instruction memory unit 2, an instruction control unit 3, a memory device 4 into which an input switch 5 is inserted, data vector memory units 6 ₁ , ... , 6 _N , output switch 7 and operand switch 8, computing device 9, into which an operation selection demultiplexer 10 is introduced, an arithmetic-logical unit 11, blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M and a result selection multiplexer 13, and also introduced an input data bus 14, an output data bus 15, an external control bus 16, an output control bus 17 and an output status bus 18,

wherein the input data bus 14 is connected to the data input buffer 1, which is connected by the control bus 19 to the instruction control unit 3 and the control bus 20 to the instruction memory unit 2,

the output data bus 15 is connected to the output of the switch 7, the external control bus 16 is connected to the corresponding ports of the data input buffer 1, the output control bus 17 and the output status bus 18 are connected to the instruction control unit 3,

in addition, the load data bus 21 is connected to the corresponding output of the data input buffer 1 and the corresponding inputs of the instruction memory unit 2 and the input switch 5 of the memory device 4, which is connected by the first control bus 22 to the data input buffer 1 and the second control bus 23 is connected to the control unit instructions 3,

the instruction memory block 2 is also connected by the corresponding instruction address bus 24 and the instruction code bus 25 to the instruction control unit 3,

the instruction control unit 3 is connected by a control bus 26 to the operand switch 8, the operation task bus 27 is connected to the operation selection demultiplexer 10, the result selection bus 28 is connected to the result selection multiplexer 13, the control bus 29 is connected to the output switch 7 of the memory device 4, and the corresponding outputs instruction control unit 3 are buses of register operands 30 ₁ , ..., 30 _X , which are connected to the corresponding groups of inputs of the operand switch 8,

in addition, the output bus 31 of the input switch 5 of the memory device 4 is connected to the first inputs of the memory blocks of data vectors 6 ₁ , ..., 6 _N , the second inputs of which by corresponding control buses of the same name 32 ₁ , ..., 32 _N are also connected to the input switch 5,

wherein the first buses 33 ₁ , ..., 33 _N for outputting data from the same memory blocks of data vectors 6 ₁ , ..., 6 _N are connected to the corresponding inputs of the output switch 7, which is connected to the corresponding read control buses 34 ₁ , ..., 34 _N is also connected to data vector memory blocks of the same name 6 ₁ , ..., 6 _N ,

the second buses 35 ₁ , ..., 35 _N for outputting data from the memory blocks of data vectors 6 ₁ , ..., 6 _N are connected to the corresponding groups of inputs of the operand switch 8, which is connected by an operand bus 36 to the first inputs of the arithmetic-logical unit 11 and blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M ,

operation selection buses 37 ₀ , ..., 37 _M connect the corresponding outputs of the operation selection demultiplexer 10 with the corresponding inputs of the arithmetic-logical unit 11 and blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M ,

calculation result buses 38 ₀ , ..., 38 _M connect the outputs of the arithmetic-logical unit 11 and blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M with the corresponding inputs of the result selection multiplexer 13, the output of which is via the current result bus 39 is connected to the input switch 5 of the memory device 4.

BRIEF DESCRIPTION OF THE DRAWINGS

In fig. Figure 1 shows a functional diagram of the proposed vector computing core.

In fig. 1 and the following notations are used in the text:

VYa - computing core;

ALU - arithmetic-logical unit;

1 - data input buffer;

2 - instruction memory block;

3 - instruction control unit;

4 - memory device;

5 - input switch;

6 ₁ , ..., 6 _N - memory blocks of data vectors;

7 - output switch;

8 - operand switch;

9 - computing device;

10 - operation selection demultiplexer;

11 - arithmetic-logical unit (ALU);

12 ₁ , ..., 12 _M - blocks for performing computationally complex data transformations (TD);

13 - result selection multiplexer;

14 - input data bus;

15 - output data bus;

16 - external control bus;

17 - output control bus;

18 - status output bus;

19 - control bus for instruction control unit 3;

20 - control bus for instruction memory unit 2;

21 - download data bus;

22 - first control bus of input switch 5;

23 - second control bus of input switch 5;

24 - instruction address bus;

25 - instruction code bus;

26 - control bus for operand switch 8;

27 - operation task bus;

28 - result selection bus;

29 - control bus for output switch 7;

30 ₁ , ..., 30 _X - register operand buses;

31 - output bus of input switch 5;

32 ₁ , ..., 32 _N - control buses for memory blocks of data vectors 6 ₁ , ..., 6 _N ;

33 ₁ , ..., 33 _N - the first data output buses from memory blocks of data vectors 6 ₁ , ..., 6 _N ;

34 ₁ , ..., 34 _N - control buses for reading from memory blocks of data vectors 6 ₁ , ..., 6 _N to output bus 15;

35 ₁ , ..., 35 _N - second data output buses from memory blocks of data vectors 6 ₁ , ..., 6 _N ;

36 - operand bus;

37 ₀ , ..., 37 _M - operation selection buses;

38 ₀ , ..., 38 _M - calculation result buses;

39 - current result bus.

DETAILED DESCRIPTION OF THE INVENTION

The proposed vector computing core (VC) is designed to perform digital data processing algorithms, including computationally complex data transformations, arithmetic operations, bitwise logical operations and shifts. Processing is performed with vectors consisting of L data words of Q bytes. The vectors of the processed data are loaded from the input data bus of 14-bit A bytes. The sequence of operations is determined by the executable program loaded into instruction memory block 2. Input data, intermediate values and processing results are stored as data vectors in data vector memory blocks 6 ₁ , ..., 6 _N , each of which contains a vector of L elements ( words).

The data vectors of the processing results are transferred from the data vector memory blocks 6 ₁ , ..., 6 _N to the output data bus of 15 bits B bytes through the output switch 7.

The external interface of the VY contains an input data bus of 14 bits A bytes, an output data bus of 15 bits B bytes, an external control bus 16, an output control bus 17 and an output status bus 18.

The control bus 16 transmits external commands for writing the program and input data, starting and resuming calculations, and issues the corresponding control signals for reading data from the input data bus 14. The output control bus 17 accompanies valid output data on the output data bus 15 with the corresponding control signals.

Output status bus 18 reflects the state of the main internal devices and VY units at each operating cycle. Output status bus 18 contains signs of loading data from bus 14, issuing data to bus 15, and a signal indicating the absence of downtime in the VL.

Input data buffer 1 is designed to generate data of the required width and output it to the load data bus of 21 bits of C bytes. Input data buffer 1 processes data from the input data bus 14 in accordance with signals from the external control bus 16. An external command is received into the input data buffer 1 via bus 16, specifying the corresponding block into which the executable program or input data vector must be written. Input data buffer 1 decodes an incoming external command, according to which it generates data from the input data bus 14 in specified formats, transfers them to the load data bus 21, and supplies control signals via the control bus 20 to write data to the instruction memory unit 2 or via the control bus 22 to write data to the memory device 4, it supplies control signals via bus 19 to the instruction control unit 3.

Instruction memory block 2 is designed to store instruction codes of the executable program that control the computation process. The program is written to the instruction memory block 2 from the load data bus 21 using control signals from the control bus 20. At the address of the current instruction from bus 24 from the instruction control unit 3, the instruction memory block 2 issues the corresponding instruction code to bus 25.

Instruction control unit 3 is designed to execute a program stored in instruction memory unit 2, which may contain conditional branches. Instruction control unit 3 controls the sequence of sampling instruction codes from instruction memory block 2, forming the addresses of current instructions on address bus 24, decodes instruction codes from bus 25, and generates executive data addresses from data vector memory blocks 6₁, ..., 6_N and generates control signals on the corresponding control buses 23 and 26 - 29. The instruction control unit 3, upon an external command from the control bus 19, can start or resume operation. Instruction control block 3 contains a register file of X registers with a width of D bytes. Data from the registers is used for internal operations of the instruction control unit 3 and can be output to the operand switch 8 via the corresponding buses of the same name 30₁, ..., thirty_X. The instruction control unit 3 generates and issues data validity signals on the output data bus 15 to the control bus 17. In the instruction control unit 3, information about the status of the VY blocks is generated, which is transmitted to the output status bus 18.

Memory device 4 stores input data, intermediate and final results of calculations when executing data processing algorithms. The memory device 4 consists of an input switch 5, memory blocks of data vectors 6 ₁ , ..., 6 _N , an output switch 7 and an operand switch 8.

Memory blocks of data vectors 6 ₁ , ..., 6 _N contain two corresponding ports of the same name for reading to the first buses of 34 ₁ , ..., 34 _N bytes of width and to the second buses of 35 ₁ , ..., 35 _N of width Q bytes with the possibility of parallel reading on both ports. Also, the memory blocks of data vectors 6 ₁ , ..., 6 _N contain one port for writing from the output bus 31 of the input switch of 5 bits of Q bytes. Input switch 5 processes control signals from the first 22 and second 23 control buses and generates control signals on buses 32 ₁ , ..., 32 _N , which control the transfer of data from buses 21 or 39 to output bus 31 to data vector memory units 6 ₁ , ..., 6 _N. The output switch 7 processes control signals from the control bus 29 and generates control signals on buses 34 ₁ , ..., 34 _N , which control reading data from memory blocks of data vectors 6 ₁ , ..., 6 _N to the 15-bit output data bus In bytes.

The computing device 9 performs the main computing work. The computing device 9 contains an ALU 11 and a group of M blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M , which perform pipeline processing of operands from data vectors, as well as an operation selection demultiplexer 10 and a result selection multiplexer 13.

The ALU 11 and the blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M receive the corresponding operation selection signal from the buses 37 ₀ , ..., 37 _M from the operation selection demultiplexer 10, and the input data arrives via the operand bus 36 from the operand switch 8. After performing the calculations, the result values are transmitted to the corresponding (M+1) buses 38 ₀ , ..., 38 _M , which are transmitted to the corresponding information inputs of the results selection multiplexer 13.

The result selection multiplexer 13 uses control signals from bus 28 to transmit result values from buses 38 ₀ , ..., 38 _M to the current result bus of 39 bits of Q bytes.

The proposed vector computing kernel works as follows.

To perform calculations, it is necessary to load the processed data into memory blocks of data vectors 6 ₁ , ..., 6 _N and the calculation program into instruction memory block 2. At the beginning of work, external commands are sent to the external control bus 16 to load the calculation program and processed data. After setting the corresponding command on the control bus 16, data in the appropriate format is supplied to the input data bus 14. The calculation program is loaded from the input data bus 14 into the instruction memory block 2, and the processed data is loaded from the input data bus 14 into the data vector memory blocks 6 ₁ , ..., 6 _N.

After loading the calculation program and the processed data, an external command to start calculations comes via the external control bus 16, which is transmitted to the instruction control unit 3 via the control bus 19. The instruction control unit 3 decodes the incoming command and begins reading instructions from the instruction memory block 2, processes the read instruction , controls the sequence of instruction fetching and generates signals on the output control buses.

Instructions are divided into computational and service. Service instructions control the sequence of instruction fetching; computational instructions determine the signals generated on the output buses of the instruction control unit 3.

Computational instruction fields include a sign of completion of calculations, control parameters for writing data vectors 6 ₁ , ..., 6 _N to memory blocks and reading data vectors 6 ₁ , ..., 6 _N from memory blocks, operand layout parameters, binary code of the computational operation and a sign for output data.

When executing a computational instruction, words of data vectors are sequentially transferred from data vector memory blocks 6 ₁ , ..., 6 _N to the corresponding data buses 35 ₁ , ..., 35 _N of the operand switch 8 and optionally to buses 33 ₁ , ... , 33 _N of output switch 7. Writing and reading data from memory blocks of data vectors 6 ₁ , ..., 6 _N are always performed by complete data vectors consisting of L elements (words).

The operand switch 8, using control signals from the control bus 26, selects data arriving along the X buses of register operands 30 ₁ , ..., 30 _X from the instruction control unit 3 and N buses 35 ₁ , ..., 35 _N output data from memory blocks data vectors 6 ₁ , ..., 6 _N , assembles a composite R-byte operand and supplies it to bus 36 for processing in computing device 9.

The computing device 9, depending on the computational operation code specified in the instruction, processes the composite operand in the ALU 11 or in one of the blocks for performing computationally complex data transformations 12 ₁ , ..., 12 _M. The AND ALU is a two-input one, the operand is represented as two operands of the same width, on which the operation specified in the instruction is performed. Processing of operands in blocks for performing computationally complex data transformations occurs according to the pipeline principle - parallel execution of calculations with various operands at different stages of the pipeline.

The resulting result of the computational operation, depending on the block that performed the operation, ALU 11 or one of 12 ₁ , ..., 12 _M , is transmitted to the corresponding bus 38 ₀ , ..., 38 _M and, according to a signal from the control bus 28, is transmitted to the current bus result 39. Data from the current result bus 39 is transmitted to the input of the input switch 5 of the memory device 4 and, using control signals from bus 23, can be simultaneously written to any subset of memory blocks of data vectors 6 ₁ , ..., 6 _N.

The final or intermediate results of calculations in the form of complete data vectors are read from the memory blocks of data vectors 6 ₁ , ..., 6 _N of the memory device 4 onto the output data bus 15 under the control of signals on the buses 34 ₁ , ..., 34 _N that are formed output switch 7 when processing signals from the control bus 29, while the instruction control unit 3 generates data validity control signals on the output data bus 15 and sets them on the output control bus 17.

The work of the VY continues until all instructions from instruction memory block 2 are processed, or until a sign of completion of calculations is encountered in the instruction being processed.

EXAMPLE OF IMPLEMENTATION OF THE INVENTION

The proposed vector computing core can be implemented as the main computing component of problem-oriented multi-core data processors manufactured in the form of very large integrated circuits (VLSI) using various (without limitation) semiconductor technologies, for example, CMOS technologies with any available technological standards. The multi-core processor must support the interfaces of the proposed vector computing core; other components and functionality of the target processor (external interfaces, organization of interaction of computing cores, control subsystem, etc.) are not required by the proposed vector computing core.

The correct functioning of the computing core was confirmed using a program model of the computer language developed in the SystemC language and a representative set of test tasks.

For the above structural and functional design of a vector computing core, a formalized description was developed in a hardware description language, a formalized description of the computing core was verified using behavioral modeling, and logical and topological design was carried out in a VLSI computer-aided design system, confirming the correct functioning and specified time limits on delays in signal circuits. The completed design stages are sufficient to conclude the feasibility of the proposed computational core as an integral part of a processor VLSI.

Using the software model of the VL and the behavioral modeling of the VL, specified in the hardware description language, more than ten test scientific and technical problems were performed with obtaining the correct result. Due to the fact that test tasks, the feasibility of which on the proposed VL is confirmed by simulation, are a representative subset of the target class of scientific and technical problems, it can be argued that the proposed vector computing kernel ensures the execution of a wider variety of scientific and technical problems.

Cycle-by-cycle modeling of the execution of test scientific and technical tasks made it possible to determine the number of cycles of operation of the VC spent to complete the tasks, and the results of topological design made it possible to predict with high probability the permissible operating clock frequency of the VC. The totality of the obtained experimental results made it possible to evaluate the performance of the VL as sufficient to perform labor-intensive scientific and technical tasks. In comparison with known performance assessments of highly specialized VLSIs, VMs for multi-threaded data processing and reconfigurable VUs when performing the same tasks, the performance of the proposed vector VYA with equal volumes of equipment and identical manufacturing technologies is close to the performance level of highly specialized VLSIs and is multiple times higher than the performance of VMs for multi-threaded data processing and reconfigurable VUs .

Thus, the above information allows us to conclude that the proposed vector computing core corresponds to the claimed technical result - increasing productivity by performing computationally complex data transformations using vector processing on high-speed conveyor devices and expanding the variety of scientific and technical problems being solved.

Claims (11)

A vector computing core containing a data input buffer (1), an instruction memory unit (2), an instruction control unit (3), a memory device (4) into which an input switch (5) is inserted, data vector memory units (6 ₁ , . .., 6 _N ), output switch (7) and operand switch (8), computing device (9), into which an operation selection demultiplexer (10), an arithmetic-logical unit (11), and blocks for performing computationally complex data transformations are introduced (12 ₁ , ..., 12 _M ) and a result selection multiplexer (13), as well as an input data bus (14), an output data bus (15), an external control bus (16), an output control bus (17) and status output bus (18), wherein the input data bus (14) is connected to the data input buffer (1), which is connected by the control bus (19) to the instruction control unit (3) and the control bus (20) to the instruction memory unit (2), the output data bus (15) is connected to the output of the switch (7), the external control bus (16) is connected to the corresponding ports of the data input buffer (1), the output control bus (17) and the output status bus (18) are connected to the instruction control unit ( 3), in addition, the loaded data bus (21) is connected to the corresponding output of the data input buffer (1) and the corresponding inputs of the instruction memory unit (2) and the input switch (5) of the memory device (4), which is connected to the buffer by the first control bus (22) data input (1) and the second control bus (23) is connected to the instruction control unit (3), the instruction memory block (2) is also connected by the corresponding instruction address bus (24) and the instruction code bus (25) to the instruction control unit (3), the instruction control unit (3) is connected to the operand switch (8) by the control bus (26), by the operation command bus (27) by the operation selection demultiplexer (10), by the result selection bus (28) by the result selection multiplexer (13), by the bus control (29) is connected to the output switch (7) of the memory device (4), and the corresponding outputs of the instruction control unit (3) are buses of register operands (30 ₁ , ..., 30 _X ), which are connected to the corresponding groups of inputs of the operand switch (8), In addition, the output bus (31) of the input switch (5) of the memory device (4) is connected to the first inputs of the data vector memory blocks (6 ₁ , ..., 6 _N ), the second inputs of which are the corresponding control buses of the same name (32 ₁ , . .., 32 _N ) are also connected to the input switch (5), wherein the first buses (33 ₁ , ..., 33 _N ) for outputting data from the same memory blocks of data vectors (6 ₁ , ..., 6 _N ) are connected to the corresponding inputs of the output switch (7), which is connected by the corresponding read control buses (34 ₁ , ..., 34 _N ) is also connected to data vector memory blocks of the same name (6 ₁ , ..., 6 _N ), the second buses (35 ₁ , ..., 35 _N ) for outputting data from the memory blocks of data vectors (6 ₁ , ..., 6 _N ) are connected to the corresponding groups of inputs of the operand switch (8), which is connected by the operand bus (36) to the first inputs of the arithmetic-logical unit (11) and blocks for performing computationally complex data transformations (12 ₁ , ..., 12 _M ), operation selection buses (37 ₀ , ..., 37 _M ) connect the corresponding outputs of the operation selection demultiplexer (10) with the corresponding inputs of the arithmetic-logical unit (11) and blocks for performing computationally complex data transformations (12 ₁ , ..., 12 _M ), calculation result buses (38 ₀ , ..., 38 _M ) connect the outputs of the arithmetic-logical unit (11) and blocks for performing computationally complex data transformations (12 ₁ , ..., 12 _M ) with the corresponding inputs of the result selection multiplexer (13 ), the output of which is connected via the current result bus (39) to the input switch (5) of the memory device (4).