RU2809210C1 - Logic converter - Google Patents

Abstract

FIELD: computing technology.

SUBSTANCE: logic converter is designed to implement any of the simple symmetrical Boolean functions τ₂, τ₃, τ₅, τ₆, depending on seven arguments - input binary signals, and can be used in digital computer systems as a means of converting codes. The logic converter contains fifteen majority elements (1₁,… ,1₁₅), and the depth of its diagram is 5.

EFFECT: reducing hardware costs and circuit depth while maintaining the functionality of the prototype.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation equipment, functional units of control systems, etc.

There are known logical converters (see, for example, RF patent 2757817, class G06F7/57, 2021) that contain majority elements and implement any of the simple symmetric Boolean functions , , , , depending on seven arguments - input binary signals.

The reason that prevents the achievement of the technical result indicated below when using known logic converters is the large circuit depth and hardware costs due to the fact that the circuit depth, in particular, of the mentioned analogue is 6 and it contains nineteen majority elements.

The closest device of the same purpose to the claimed invention in terms of the set of features is a logic converter adopted as a prototype (RF patent 2776921, class G06F7/57, 2022), which contains majority elements and implements any of the simple symmetric Boolean functions , , , , depending on seven arguments - input binary signals.

The reasons that prevent the achievement of the technical result indicated below when using the prototype include large circuit depth and hardware costs due to the fact that the prototype circuit depth is 6 and it contains eighteen majority elements.

The technical result of the invention is to reduce hardware costs and circuit depth while maintaining the functionality of the prototype.

The specified technical result in the implementation of the invention is achieved by the fact that in a logic converter containing fifteen majority elements that have three inputs, the outputs of the kth ( ), m -th ( ) and thirteenth majority elements are connected respectively to the second inputs ( )th, ( )th and fourteenth majority elements, and the first inputs of the first, second, sixth and the first input of the third majority elements are connected respectively to the first and second tuning inputs of the logic converter, the peculiarity is that the outputs of the fifth, seventh, eleventh and third inputs ( )th, ( )th, fourteenth majority elements are connected respectively to the second inputs of the sixth, eighth, twelfth and outputs ( )th, ( )th, fifteenth majority elements, and the first inputs of the fifth, ninth and the output of the fourth majority elements are connected, respectively, to the first tuning input and output of the logic converter, the third tuning input of which is connected to the first inputs of the fourth, ( )th, ( )th, fourteenth majority elements.

The drawing shows a diagram of the proposed logic converter.

The logic converter contains majority elements 1 ₁ ,…,1 ₁₅ , which have three inputs each, and the outputs of elements 1 _k ( ), 1 _{k +6} , 1 ₅ , 1 ₁₁ , 1 ₁₃ and the third inputs of elements 1 _j ( ), 1 _{j +6} , 1 ₁₄ are connected respectively to the second inputs of elements 1 _{k +1} , 1 _{k +7} , 1 ₆ , 1 ₁₂ , 1 ₁₄ and the outputs of elements 1 _{4× j -6} , 1 _{2× j +6} , 1 ₁₅ , and the first inputs of elements 1 _{j -2} , 1 _{j +2} , 1 ₉ and the first inputs of elements 1 _{j +4} , 1 _{j +8} , 1 ₄ , 1 ₁₄ are connected, respectively, to the first and third configuration inputs of the logic converter, the second the tuning input and output of which are connected, respectively, to the first input of the third and the output of the fourth majority elements.

The operation of the proposed logic converter is carried out as follows. At its first, second, third tuning inputs, the necessary signals are fixed accordingly constant settings. To the second inputs of elements 1 ₁ , 1 ₇ , the first input of element 1 ₁₃ ; third inputs of elements 1 ₁ , 1 ₇ , second input of element 1 ₁₃ ; third inputs of elements 1 ₂ , 1 ₈ , 1 ₁₃ ; second inputs of elements 1 ₅ , 1 ₁₁ , first input of element 1 ₁₅ ; third inputs of elements 1 ₅ , 1 ₁₁ , second input of element 1 ₁₅ ; the third inputs of elements 1 ₆ , 1 ₁₂ , 1 ₁₅ and the first input of element 1 ₁₀ are supplied respectively binary signals ; ; ; ; ; And ( ). At the output of element 1 _i ( ) we have , Where And ∙ there are respectively signals at its first, second, third inputs and symbols of the operations OR, AND. Consequently, the signal at the output of element 1 ₄ is determined by the expression

,

in which ( ). Thus, at the output of the proposed logic converter we obtain

,

Where there are simple symmetric Boolean functions of seven arguments (see p. 126 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M.: Energia, 1974). In this case, the depth of the proposed logic converter circuit is 5.

The above information allows us to conclude that the proposed logic converter implements any of the simple symmetric Boolean functions , , , , depending on seven arguments - input binary signals, has a smaller circuit depth compared to the prototype and has lower hardware costs compared to it.

Claims (1)

A logic converter designed to implement simple symmetric Boolean functions, containing fifteen majority elements that have three inputs each, and the outputs are the kth ( ), m -th ( ) and thirteenth majority elements are connected respectively to the second inputs ( )th, ( )th and fourteenth majority elements, and the first inputs of the first, second, sixth and the first input of the third majority elements are connected, respectively, to the first and second tuning inputs of the logic converter, characterized in that the outputs of the fifth, seventh, eleventh and third inputs ( )th, ( )th, fourteenth majority elements are connected respectively to the second inputs of the sixth, eighth, twelfth and outputs ( )th, ( )th, fifteenth majority elements, and the first inputs of the fifth, ninth and the output of the fourth majority elements are connected, respectively, to the first tuning input and output of the logic converter, the third tuning input of which is connected to the first inputs of the fourth, ( )th, ( )th, fourteenth majority elements.