RU2843598C1 - Computing node of reconfigurable computing system - Google Patents

Abstract

FIELD: physics.

SUBSTANCE: invention relates to computing nodes of reconfigurable computing systems. Computing node of the reconfigurable computing system comprises Ethernet network switch 8, network input port 9, group of K computing blocks 11₁, …, 11_K and general purpose computer 1 in group of K adapters 2₁, …, 2_K connection of computing units and switch 3 PCI-Express, wherein each adapter of group 2₁, …, 2_K includes: PCI-Express controller 7, interface converter 6, service interface port 4 and operating interface port 5, and in each computing unit from group 11₁, …, 11_K includes monitoring network port 10, cooling control unit 13, monitoring unit 14, power supply control unit 15, computing unit identifier memory 12, receiving port 16 and service interface expansion port 17, receiving port 18, expansion port 19 and relay unit 20 of working interface, and group of N computing modules 22₁, …, 22_N, each of which includes: computing module identifier memory 21, monitoring and automatic control unit 25, computing PLD configuration unit 24, group of M units 26₁, …, 26_M individual control of co-computer, group of M co-calculator 37₁, …, 37_M with individual power supply and group of M computing PLD 23₁, …, 23_M, wherein each co-calculator from group 37₁, …, 37_M includes co-computer interface unit 38, co-computer switch 39 and group of L cores 40₁, …, 40_L of co-calculator, and each computing PLD from group 23₁, …, 23_M includes united into static region 27 receiving unit 28, expansion unit 29 and working interface routing unit 30, automatic control unit 31, co-computer adapter 32 and combined into dynamic region 33 addressable actuating devices switch 34, group of Q adapters 35₁, …, 35_Q addressable actuators and group of Q addressable actuators 36₁, …, 36_Q.

EFFECT: high computational power of a computational node due to increase in the number of computational PLDs.

1 cl, 1 dwg

Description

AREA OF TECHNOLOGY

The invention relates to the field of computer technology, in particular to computing nodes of reconfigurable computing systems intended for solving computationally complex variant problems of discrete mathematics using parallelization and pipelining of computations.

PRIOR ART

A computing node of a problem-oriented computing device is known (RU No. 182316 U1, IPC G06F 15/16, 17/00, declared on 14.06.2018, published on 14.08.2018 Bulletin No. 23), comprising a general-purpose computer 3 with an EtherNet interface and a PCI-Express input-output bus, a PCI-Express switch 4 and a group of K computing accelerator modules 6 ₁ , ..., 6 _K , each of which consists of a PCI-Express switch 7, a group of N interface FPGAs 8 ₁ , ..., 8 _N , a system FPGA 10, configuration memory 13, configuration and monitoring unit 11, a group of N problem-oriented computing VLSIs 19 ₁ , ..., 19 _N , memory 21 of the starting configuration of the interface FPGA, block 18 for configuring the memory of the starting configuration 21 and block 22 for monitoring, power management and generating operating frequencies of problem-oriented computing VLSI.

The disadvantages of this computing node of the reconfigurable computing system are low computing power and limited classes of labor-intensive tasks that can be solved.

The reason that prevents the achievement of the technical result is the use of interface FPGAs 8 ₁ , …, 8 _N for organizing the interaction of the computing VLSI with the general-purpose computer 3, which, in addition to preparing data and analyzing the results of the operation of the computing VLSI, is also engaged in organizing the delivery and analysis of telemetry information about the state of the computing accelerator modules, which leads to downtime of the computing VLSI, which determines the performance of the computing system as a whole.

A slave computing node of a reconfigurable computing system is known (RU No. 2713757 C1, IPC G06F 15/17, declared on 29.04.2019, published on 07.02.2020 Bulletin No. 4), comprising a computer 8, a PCI-Express switch 11, a group of N state memories 9 ₁ , ..., 9 _N , RAM 12, a general-purpose computing device 10 and a group of N reconfigurable computing devices 13 ₁ , ..., 13 _N , each of which contains a PCI-Express switch 19, a group of M computing FPGAs 20 ₁ , ..., 20 _M , an interface FPGA 22, a group of M computing VLSIs 33 ₁ , ..., 33 _M , with a single rectangular radiator installed above them 27, configuration and monitoring unit 23, PCI-Express switch mode control unit 30 19, FPGA configuration memory 24, a group of M individual monitoring and control units 15 ₁ , …, 15M and a group of M start-up configuration memories 35 ₁ , …, 35 _M , a group of M unified footprints 17 ₁ , …, 17 _M for installing the corresponding computing FPGAs 20 ₁ , …, 20 _M , a group of M unified footprints 18 ₁ , …, 18 _M for installing the corresponding computing VLSIs 33 ₁ , …, 33 _M , a group of M buffer memories 37 ₁ , … 37 _M and a group of M controllers 38 ₁ , …, 38 _M for direct access to the memory of the RVR 13 ₁ , …, 13 _N .

The disadvantage of this computing node of the reconfigurable computing system is the inefficient distribution of computing resources between user tasks.

The reasons preventing the achievement of the technical result are the possibility of distributing computing resources between user tasks only with an accuracy of one computing FPGA with a computing VLSI.

The closest device of the same purpose to the claimed invention, based on the set of features adopted as a prototype, is the computing node of a reconfigurable computing system (RU No. 2798443 C1, IPC G06F 15/16, 15/177, declared on 09.12.2022, published on 22.06.2023 Bulletin No. 18), containing a group of N memories 6 ₁ , ..., 6 _N of tasks performed by computing modules, a group of N memories 7 ₁ , ..., 7 _N of the state of computing modules, a general-purpose computer 8 of the computing node, a PCI-Express switch 9 of the computing node, a PCI-Express switch 10 of the computing modules of the computing node, memory 15 of the state of executive devices, memory 25 of partial reconfiguration of executive devices and a group of N computing modules 11 ₁ , ..., 11 _N , each of which contains a group of M computing FPGA 13 ₁ , …, 13 _M with individual power supply and system FPGA 38, PCI-Express switch 12, PCI-Express switch 12 mode control unit 34, computing FPGA configuration unit 35, system FPGA startup configuration memory 36, computing FPGA basic startup configuration unit 37, computing module monitoring and control unit 39, automatic control unit 40, computing module cooling and power supply control unit 41, computing node cooling and power supply control unit 42, computing node cooling fan control and control unit 43, computing node monitoring and control unit 44, computing node power supply control and control unit 45, a group of M individual co-calculator mode control units 26 ₁ , …, 26 _M , a group of M co-calculators 27 ₁ , …, 27 _M with individual power supply, each of which contains an interface unit 28, a switch 29 co-calculators, as well as a group of L computing cores 30 ₁ , ..., 30 _L , wherein each of the M computing FPGAs 13 ₁ , ..., 13 _M comprises, combined in a static region 14 of partial reconfiguration of the computing FPGA, a PCI-Express controller 16, a switch configuration memory 17, a switch control unit 18, an automatic control unit 19, a data buffer memory 20, a result buffer memory 21, a direct memory access controller 22, a computing FPGA switch 23, a co-calculator adapter 24 and, combined in a dynamic region 31 of partial reconfiguration of the computing FPGA, a group of Q executive devices 33 ₁ , ..., 33 _Q and a group of Q adapters of executive devices 32 ₁ , ..., 32 _Q .

The disadvantage of this computing node of the reconfigurable computing system is the lack of the ability to increase the computing power of the computing node by increasing the number of computing FPGAs in its composition.

The reason preventing the achievement of the technical result specified below is the limitation of the number of end users of the high-speed serial PCI_Express interface, which is used for interaction of the general-purpose computer 8 with the computing 13 ₁ , ..., 13 _M and with the system 38 FPGA of the computing modules 11 ₁ , ..., 11 _N by means of the PCI_Express switches 9 and 12, which are the end users of the PCI Express interface of the general-purpose computer 8.

OBJECTIVE OF THE INVENTION

The problem that the proposed invention is aimed at solving is the creation of a simple-to-use computing node of a reconfigurable computing system with dynamic redistribution of computing resources depending on the current flow of tasks that has the required technical characteristics (computing power and exchange speed).

The technical result of the proposed invention is the expansion of the arsenal of means for the same purpose and the provision of the possibility of increasing the computing power of the computing node by increasing the number of computing FPGAs in its composition.

BRIEF DESCRIPTION OF THE ESSENCE OF THE INVENTION

The specified technical result in the implementation of the invention is achieved in that the computing node of the reconfigurable computing system contains an Ethernet network switch 8, an input network port 9, a group of K computing units 11 ₁ , ..., 11 _K and a general-purpose computer 1 as part of a group of K adapters 2 ₁ , ..., 2 _K for connecting computing units and a PCI-Express switch 3,

wherein each adapter from group 2 ₁ , …, 2 _K includes a PCI-Express controller 7, an interface converter 6, a service interface port 4 and a working interface port 5, and each computing block from group 11 ₁ , …, 11 _K includes a network monitoring port 10, a cooling control unit 13, a monitoring unit 14, a power control unit 15, a computing block identifier memory 12, a receiving port 16 and an expansion port 17 of the service interface, a receiving port 18, an expansion port 19 and a retransmission unit 20 of the working interface, and a group of N computing modules 22 ₁ , …, 22 _N , each of which includes a computing module identifier memory 21, a computing FPGA configuration unit 24, a monitoring and automatic control unit 25, a group of M individual co-computer control units 26 ₁ , …, 26 _M , a group of M co-calculators 37 ₁ , …, 37 _M with individual power supply and a group of M computing FPGAs 23 ₁ , …, 23 _M ,

wherein each co-calculator from group 37 ₁ , …, 37 _M includes interface block 38 of the co-calculator, switch 39 of the co-calculator and a group of L computing cores 40 ₁ , …, 40 _L of the co-calculator, and each computing FPGA from group 23 ₁ , …, 23 _M includes, combined into static region 27, receiving block 28, expansion block 29 and block 30 of routing of the working interface, automatic control block 31, adapter 32 of the co-calculator and, combined into dynamic region 33, switch 34 of addressable executive devices, a group of Q adapters 35 ₁ , …, 35 _Q of addressable executive devices and a group of Q addressable executive devices 36 ₁ , …, 36 _Q ,

wherein the Ethernet network switch 8 is connected to the input network port 9, to the network ports 10 for monitoring the computing units 11 ₁ , ..., 11 _K and to the general-purpose computer 1, in which the PCI-Express switch 3 is connected to the controllers 7 PCI-Express adapters 2 ₁ , ..., 2 _K for connecting the computing units, in each of which the PCI-Express controller 7 is connected to the interface converter 6, which is connected to the port 4 of the service interface and to the port 5 of the working interface,

wherein for each of the adapters 2 ₁ , …, 2 _K for connecting the computing units, the ports 4 of the service interface are connected to the receiving ports 16 of the service interface, and the ports 5 of the working interface are connected to the receiving ports 18 of the working interface, of the corresponding computing units 11 ₁ , …, 11 _K of the same name, in which the network ports 10 of monitoring are connected to the monitoring unit 14, which is connected to the memory 12 of the identifier of the computing unit, to the units 24 for configuring the computing FPGAs 23 ₁ , …, 23 _M of the computing modules 22 ₁ , …, 22 _N , to the cooling control unit 13, to the power control unit 15 and to the monitoring and automatic control units 25 of the computing modules 22 ₁ , …, 22 _N , which are connected to the computing FPGAs 23 ₁ , …, 23 _M , with co-computers 37 ₁ , …, 37 _M with individual power supply, with individual control units 26 ₁ , …, 26 _M of the co-computer and with automatic control units 31, which are connected to the individual control units 26 ₁ , …, 26 _M of the co-computer, which are connected to the same-named co-computers 37 ₁ , …, 37 _M with individual power supply, in each of which the interface unit 38 of the co-computer is connected to the switch 39 of the co-computer, which is connected to the L computing cores 40 ₁ , …, 40 _L of the co-computers,

in addition, the interface blocks 38 of the co-calculators 37 ₁ , …, 37 _M are connected to the corresponding adapters 32 of the co-calculators, which in the static region 27 of each of the computing FPGAs 23 ₁ , …, 23 _M are connected to the automatic control block 31 and to the working interface routing block 30, which is connected to the receiving block 28 and to the working interface expansion block 29 in the static region 27 and to the switch 34 of the addressable executive devices, which in the dynamic region 33 of each of the computing FPGAs 23 ₁ , …, 23 _M is connected to the adapters 35 ₁ , …, 35 _Q of the addressable executive devices, which in the dynamic region 33 are connected to the corresponding addressable executive devices 36 ₁ , …, 36 _Q of the same name, each of which is connected to the automatic control block 31 of the bus 41 of the operating frequency lock addressable actuators,

wherein in each of the computing units 11 ₁ , …, 11 _K the receiving port 16 of the service interface is connected to the unit 24 for configuring the computing FPGAs of the first 22 ₁ computing module from the group 22 ₁ , …, 22 _N , the expansion port 17 of the service interface is connected to the unit 24 for configuring the computing FPGAs of the last 22 _N computing module from the group 22 ₁ , …, 22 _N , the units 24 for configuring the computing FPGAs of the computing modules, starting from the first module 22 ₁ to the penultimate module 22 _N-1 from the group 22 ₁ , …, 22 _N , are connected to the units 24 for configuring the computing FPGAs of the subsequent computing modules, starting from the second module 22 ₂ to the last module 22 _N from the group 22 ₁ , …, 22 _N ,

wherein in each computing module from the group 22 ₁ , …, 22 _N the blocks 24 for configuring the computing FPGAs are connected to the memory 21 of the identifier of the computing module,

in addition, in each of the computing blocks 11 ₁ , …, 11 _K the receiving port 18 and the expansion port 19 of the working interface are connected to the working interface retransmission block 20, which is connected to the receiving block 28 of the working interface of the first computing FPGA 23 ₁ from the group 23 ₁ , …, 23 _M of the first computing module 22 ₁ from the group 22 ₁ , …, 22 _N and to the working interface expansion block 29 of the last 23 _M computing FPGA from the group 23 ₁ , …, 23 _M of the last computing module 22 _N from the group 22 ₁ , …, 22 _N ,

wherein for all computing modules, starting from the first module 22 ₁ to the penultimate 22 _N-1 from the group 22 ₁ , …, 22 _M, the blocks 29 of expansion of the working interface of the last computing FPGAs 23 _M from the group 23 ₁ , …, 23 _M are connected to the receiving blocks 28 of the working interface of the first computing FPGAs 23 ₁ from the group 23 ₁ , …, 23 _M of the subsequent computing modules, starting from the second computing module 22 ₂ to the last computing module 22 _N from the group 22 ₁ , …, 22 _N ,

in addition, in each computing module from the group 22 ₁ , …, 22 _N, the blocks 29 of expansion of the working interface of the computing FPGAs, starting from the first computing FPGA 23 ₁ to the penultimate computing FPGA 23 _M-1 from the group 23 ₁ , …, 23 _M , are connected to the receiving blocks 28 of the working interface of the subsequent computing FPGAs, starting from the second computing FPGA 23 ₂ to the last computing FPGA 23 _M from the group 23, …, 23 _M .

BRIEF DESCRIPTION OF DRAWINGS

Fig. 1 shows a functional diagram of the proposed computing node of the reconfigurable computing system.

In Fig. 1 and in the text the following abbreviations and designations are used:

K is the number of computing blocks in a computing node;

N is the number of computing modules in the computing block;

M is the number of computing FPGAs in the computing module;

L - the number of computing cores in the co-computer;

Q - the number of addressable executive devices in computing FPGAs;

1 - general purpose calculator;

2 ₁ , …, 2 _K - a group of K adapters for connecting computing units;

3 - PCI-Express switch;

4 - service interface port;

5 - working interface port;

6 - interface converter;

7 - PCI-Express controller;

8 - Ethernet network switch;

9 - input network port;

10 - network monitoring port;

11₁, …, 11_K- a group of K computing blocks;

12 - memory of the computing unit identifier;

13 - cooling control unit;

14 - monitoring unit;

15 - power control unit;

16 - receiving port of the service interface;

17 - service interface expansion port;

18 - receiving port of the working interface;

19 - working interface expansion port;

20 - working interface relay block;

21 - memory of the computing module identifier;

22 ₁ , …, 22 _N - a group of N computing modules;

23 ₁ , …, 23 _M - a group of M computing FPGAs;

24 - block for configuring computing FPGAs;

25 - monitoring and automatic control unit;

26 ₁ , …, 26 _M - a group of M blocks of individual control of the co-calculator;

27 - static region of partial reconfiguration;

28 - receiving block of the working interface;

29 - working interface expansion block;

30 - working interface routing block;

31 - automatic control unit;

32 - co-calculator adapter;

33 - dynamic region of partial reconfiguration;

34 - switch of addressable executive devices;

35 ₁ , …, 35 _Q - a group of Q adapters of addressable executive devices;

36 ₁ , …, 36 _Q - a group of Q addressable actuators;

37 ₁ , …, 37 _M - a group of M co-calculators with individual power supply;

38 - interface block of the co-calculator;

39 - co-calculator switch;

40 ₁ , …, 40 _L - a group of L computing cores of the co-computer;

41 - bus for blocking the operating frequency of addressable actuators.

DETAILED DESCRIPTION OF THE ESSENCE OF THE INVENTION

A reconfigurable computing system consists of a control server and a plurality of computing nodes connected by a communication environment.

Reconfiguration is a change in the architecture and/or data processing algorithm that allows organizing various schemes of sequential (pipeline), parallel and/or sequential-parallel data processing within a given group of computing facilities.

The computing nodes include a general-purpose computer and computing units, united by a communication environment that ensures interaction between the general-purpose computer and the computing units.

The general-purpose computer includes general-purpose processors, RAM, root complex, PCI-Express switch, and network interfaces.

Computing units are usually structurally implemented in a single housing and include computing modules and autonomous power supply and cooling systems.

The computing module is a high-performance single-board computing accelerator connected to a general-purpose computer via an interaction interface and operating under its control, which contains computing FPGAs (programmable logic integrated circuits) and co-calculators (custom specialized integrated circuits) for the circuit and software implementation of specific labor-intensive algorithms.

The interfaces for interaction between a general-purpose computer and computing FPGAs and co-computers are divided into three main groups:

- working (main) interfaces that exchange data and calculation results (depending on the task being performed, they may require a high exchange rate);

- service (auxiliary) interfaces that configure computing FPGAs and co-calculators using user programs (executed once when changing user programs);

- monitoring interfaces that measure the operating temperature, set temperature protection thresholds, set and control power supply (performed continuously while user programs are running).

The proposed computing node of the reconfigurable computing system is completely self-sufficient, that is, capable of solving both labor-intensive tasks and monitoring the state.

The computing node consists of a general-purpose computer 1, an Ethernet network switch 8, an input network port 9 for connection to the computing system, and a group of K computing blocks 11 ₁ , …, 11 _K , implemented in separate housings and connected to each other by cables.

Network switch 8 Ethernet is intended to organize interaction of general-purpose computer 1 with computing units 11 ₁ , …, 11 _K via network monitoring ports 10 and with the computing system via input network port 9.

General-purpose computer 1, in addition to a universal processor, root complex, network interfaces and memory (not shown in the drawing), contains a PCI-Express switch 3 implemented on the motherboard and a group of K adapters 2 ₁ , …, 2 _K and is intended for configuring computing FPGAs, managing the flow of tasks and monitoring the state of computing blocks 11 ₁ , …, 11 _K .

Adapters from group 2 ₁ , …, 2 _K , intended for connecting corresponding computing units 11 ₁ , …, 11 _K of the same name, are converters of the PCI-Express interface into working and service interfaces, installed in the PCI-Express slots of the motherboard of a general-purpose computer 1, and consist of PCI-Express controllers 7, as well as ports of the service 4 and working 5 interfaces.

Controllers 7 PCI-Express adapters 2 ₁ , …, 2 _K are end users of the PCI Express interface of the general-purpose computer 1 and are intended for receiving processor commands, as well as for organizing data exchange with the memory (not shown in the drawing) of the general-purpose computer 1.

The 6 interface converter is designed to analyze and process processor commands transmitted via the PCI Express interface and to form, depending on the data transmitted by the controller 7, working and service interfaces for interaction with computing units 11 ₁ , …, 11 _K .

The ports of the service 4 and working 5 interfaces are intended for cable connection via the corresponding interfaces to the general-purpose computer 1 of the computing units 11 ₁ , …, 11 _K .

The working interface is a high-speed serial duplex interface based on the use of a pair of typical high-speed transceivers when connecting components using noise-resistant information coding (similar to the implementation of the PCI-Express interface), and is intended for exchanging data and the results of the operation of the computing FPGAs 23 ₁ , …, 23 _M as part of the computing modules 22 ₁ , …, 22 _N of all computing blocks 11 ₁ , …, 11 _K with the general-purpose computer 1 by means of the corresponding adapters 2 ₁ , …, 2 _K . The working interface is implemented using the channel layer protocol of interaction according to the network protocol stack model (Open Systems Interconnection).

The service interface is intended for managing the configuration of the computing FPGAs 23 ₁ , …, 23 _M as part of the computing modules 22 ₁ , …, 22 _N of all computing blocks 11 ₁ , …, 11 _K by the general-purpose computer 1 by means of the corresponding adapters 2 ₁ , …, 2 _K . The service interface is a Fast Ethernet interface at the physical level, using the TCP/IP protocol stack, for implementing the network and transport interaction levels.

The computing units 11 ₁ , …, 11 _K contain in their composition a memory 12 of the computing unit identifier, autonomous power supply and cooling systems (not shown in the drawing), operating under the control of the monitoring unit 14 by means of the cooling control units 13 and power supply 15, as well as a working interface retransmission unit 20, intended for correcting the characteristics of the high-speed signal during cable connection of the adapters 2 ₁ , …, 2 _K of the general-purpose computer 1 to the computing units 11 ₁ , …, 11 _K , and N computing modules 22 ₁ , …, 22 _N .

Memory 12 of the computing unit identifier is intended for storing the unique (factory) number of the computing unit, as well as information about the type of this computing unit (for example: the number and type of computing modules in the unit).

Computing units 11 ₁ , …, 11 _K as part of the computing node operate using cable connections through the corresponding monitoring ports 10, as well as service 16, 17 and working 18, 19 interfaces.

Network monitoring ports 10 are intended for cable connection of computing units 11 ₁ , …, 11 _K to network switch 8 Ethernet.

Receiving ports 16 of the service interface are intended for cable connection to ports 4 of the service interface of adapters 2 ₁ , …, 2 _K of the general-purpose computer 1 of the corresponding computing blocks of the same name 11 ₁ , …, 11 _K .

Expansion ports 17 of the service interface are intended for cable connection to computing units 11 ₁ , …, 11 _K of additional similar computing units 11 (not shown in the drawing).

Receiving ports 18 of the working interface are intended for cable connection to ports 5 of the working interface of adapters 2 ₁ , …, 2 _K of the general-purpose computer 1 of the corresponding computing blocks 11 ₁ , …, 11 _K of the same name.

Expansion ports 19 of the working interface are intended for cable connection to computing units 11 ₁ , …, 11 _K of additional similar computing units 11 (not shown in the drawing).

Computational modules 22 ₁ , …, 22 _N , consisting of M computational FPGAs 23 ₁ , …, 23 _M , memory 21 of the computational module identifier, block 24 for configuring the computational FPGAs, block 25 for monitoring and automatic control, as well as M co-calculators 37 ₁ , …, 37 _M with individual control blocks of the same name 26 ₁ , …, 26 _M , are intended for the implementation of labor-intensive algorithms in solving user problems.

Memory 21 of the computing module identifier is intended for storing the unique (factory) number of the computing module, as well as information about the type of this computing module (for example: the number and type of computing FPGAs in the module, the type of co-computer).

The block 24 for configuring the computing FPGAs 23 ₁ , …, 23 _M is intended for direct connection to the service interface, analysis of its commands and implementation of configuration of the computing FPGAs 23 ₁ , …, 23 _M of the computing modules 22 ₁ , …, 22 _N or retransmission of the interface for neighboring computing modules 22 ₁ , …, 22 _N . Configuration of the computing FPGAs 23 ₁ , …, 23 _M is performed in the modes of the starting configuration (static region) and the working configuration (dynamic region).

The block 25 for monitoring and automatic control of the computing FPGAs 23 ₁ , …, 23 _M is intended for setting temperature protection thresholds, measuring and analyzing the current temperature state and, together with the blocks 26 ₁ , …, 26 _M for individual control of the co-calculator, for controlling the operation of the computing FPGAs 23 ₁ , …, 23 _M and co-calculators 37 ₁ , …, 37 _M .

The computing FPGAs 23 ₁ , …, 23 _M , consisting of a receiving unit 28, an expansion unit 29 and a working interface routing unit 30, an automatic control unit 31 and an adapter 32 of a co-calculator of a static region 27 of partial reconfiguration, a switch 34 of addressable executive devices, a group of Q addressable executive devices 36 ₁ , …, 36 _Q with corresponding like-named adapters 35 ₁ , …, 35 _Q of a dynamic region 33 of partial reconfiguration, are intended for controlling the flow of data transmission of the working interface, organizing interaction with the corresponding like-named co-calculator 37 ₁ , …, 37 _M and hardware implementation of labor-intensive algorithms of user tasks.

The receiving unit 28 of the working interface of the static region 27 of the computing FPGAs 23 ₁ , …, 23 _M is a duplex channel (forward and reverse) for data exchange and is intended for connection to the high-speed serial working interface via the unit 20 for retransmitting the working interface from the adapter 2 of the general-purpose computer 1 or the previous neighboring computing FPGA and for transmitting signals of the internal interface of the computing FPGA.

Block 29 for expanding the working interface of the static region 27 of the computing FPGAs 23 ₁ , …, 23 _M is a duplex channel (forward and reverse) for data exchange and is intended for generating a high-speed serial signal for connecting subsequent adjacent computing FPGAs from the internal signals of the computing FPGA.

The block 30 for routing the working interface of the static region 27 of the computing FPGA 23 ₁ , …, 23 _M is intended for analyzing the state of the receiving working interface and converting the working interface for interaction with the addressable executive devices 36 ₁ , …, 36 _Q through the corresponding adapters 35 ₁ , …, 35 _Q and the switch 34 of the addressable executive devices, with the corresponding co-computer of the same name 37 ₁ , …, 37 _M through the corresponding adapters 32 or for translating the interface to the subsequent neighboring computing FPGA through the block 29 for expanding the working interface.

The automatic control unit 31 of the static region 27 of the computing FPGA 23 ₁ , …, 23 _M is intended to control the flow of tasks and the operating mode of the corresponding co-calculator 37 ₁ , …, 37 _M of the same name depending on its current temperature state, as well as blocking the operating frequency of the corresponding addressable executive devices 36 ₁ , …, 36 _Q via bus 41 depending on the current temperature state of the computing FPGA.

The adapter of the co-calculator 32 of the static region 27 of the computing FPGAs 23 ₁ , …, 23 _M is intended for matching the working interface with the interface of the corresponding co-calculator 37 ₁ , …, 37 _M of the same name.

Dynamic region 33 of partial reconfiguration of computing FPGAs 23 ₁ , …, 23 _M as part of switch 34 of addressable executive devices and a group of Q addressable executive devices 36 ₁ , …, 36 _Q with corresponding adapters 35 ₁ , …, 35 _Q is intended for hardware implementation of labor-intensive algorithms of user tasks and is reconfigured depending on the current flow of tasks.

Co-calculators 37 ₁ , …, 37 _M as part of interface block 38, switch 39 and a group of L computing cores 40 ₁ , …, 40 _L of the co-calculator are intended for software and hardware implementation of labor-intensive algorithms for user tasks.

The proposed computing node implements a three-level monitoring subsystem using automatic control of operating parameters: operational change of the rotation speed of cooling fans, operational stop of data processing by the corresponding computing FPGAs and/or co-calculators, as well as operational disconnection of power from the corresponding computing FPGAs and/or co-calculators depending on their current temperature.

At the first level, local control of the individual power supply of the co-computers 37 ₁ , …, 37 _M is carried out, which assumes both automatic disconnection by the computing FPGAs 23 ₁ , …, 23 _M of the individual power supplies from the corresponding co-computers, and disconnection from them by the monitoring and automatic control unit 25 during the idle period in order to reduce the total power consumption and, consequently, the heat generation of the computing node.

At the second level, local monitoring and control of the state of the computing modules 22 ₁ , …, 22 _N is carried out by the monitoring unit 14, which collects data on the current state of the components of the computing modules involved in the process of performing the calculations, namely the computing FPGAs 23 ₁ , …, 23 _M and the corresponding co-calculators 37 ₁ , …, 37 _M , and also controls their power supply and operating frequencies through the monitoring unit 25.

At the third level, monitoring and control of the state of the computing blocks 11 ₁ , …, 11 _K is carried out by the program of the general-purpose computer 1, as well as the formation of frames of the state of the computing blocks in the corresponding state memories of the general-purpose computer 1 (not shown in the drawing).

The proposed computing node operates as follows.

When the power is turned on, the first to be turned on are the Ethernet network switch 8, the computing units 11 ₁ , …, 11 _K and the general-purpose computer 1. When loading the startup operating system (BIOS) of the general-purpose computer 1, a group of K adapters 2 ₁ , …, 2 _K for connecting the computing units 11 ₁ , …, 11 _K is configured and the resources of the PCI-Express switch 3 and the controllers 7 PCI-Express adapters 2 ₁ , …, 2 _K are distributed in the memory of the general-purpose computer 1 as end devices.

After loading the operating system of the general-purpose computer 1, first of all, the identifiers of the computing units 11 ₁ , …, 11 _K are read from the memory 12 of the identifier of the computing unit via the monitoring interface. Each of the computing units 11 ₁ , …, 11 _K is assigned a number N _BLK (from 1 to K), the power ratings are set and the computing modules 22 ₁ , …, 22 _N are switched on. In this case, power is supplied to all components in the computing modules 22 ₁ , …, 22 _N with the exception of co-computers 37 ₁ , …, 37 _M with individual power supply, to which power is supplied, if necessary, only before starting user tasks.

After this, the identifiers of the computing modules 22 ₁ , …, 22 _M are read from the memory 21 of the identifiers of the corresponding computing modules via the service interface. Each of the computing modules 22 ₁ , …, 22 _N is assigned the number N _MOD (from 1 to N) and the starting configuration of all available computing FPGAs 23 ₁ , …, 23 _M is performed on all computing modules 22 ₁ , …, 22 _N of all computing blocks 11 ₁ , …, 11 _K . The starting configuration is performed in parallel via all channels of the service interface of the adapters 2 ₁ , …, 2 _K , in the presence of a multi-core processor of the general-purpose computer 1

Next, the configuration and performance testing of all channels of the working interface is carried out, which are also carried out in parallel for all adapters 2 ₁ , …, 2 _K in the presence of a multi-core processor of the general-purpose computer 1.

Configuration of dynamic regions 33 of computing FPGAs 23 ₁ , …, 23 _M by user work programs is carried out, depending on the current flow of tasks, immediately before starting tasks independently for each computing FPGA 23 ₁ , …, 23 _M .

The address of the configurable computing FPGA for the service interface is formed from the number N _BLK of the computing block 11 ₁ , …, 11 _K , the number N _MOD of the computing module 22 ₁ , …, 22 _N , its serial number N _FPGA (from 1 to M) on the computing module and is linked to the number of the port N _PCIE of the switch 3 PCI-Express connected to the controllers 7 PCI-Express adapters 2 ₁ , …, 2 _K for connecting computing blocks and the attribute of the service interface N _INT =0.

The address of the computing FPGA for the working interface is formed in the same way as for the service interface, only linked to the working interface feature N _INT =1.

To access the corresponding addressable executive devices 36 ₁ , …, 36 _Q and the co-calculator, the number N _AIU (from 1 to Q) of the addressable executive device is added to the address of the computing FPGA, where N _AIU = 0 corresponds to accessing the co-calculator through adapter 32.

To access the corresponding computing cores 40 ₁ , …, 40 _L of the co-computer, the number of the computing core N _CORE (from 1 to L) is added to the address of the computing FPGA, and in the case of N _CORE = 0, access is made to other resources of the co-computer.

To access the internal resources of the addressable executive devices 36 ₁ , …, 36 _Q and the cores 40 ₁ , …, 40 _L of the co-calculator, the number N _{of the ADR} of these resources (registers, memory buffers, etc.) is added to the address of the computing FPGA.

In addition to the address, the command code N _COP (“write” / “read”), as well as the data size N _DAN are transmitted via the service and working interfaces.

The address field width of the R _PCIE port is 8 in accordance with the PCI-Express standard.

The bit depth of the command code field R _COPE = 1.

The address field bit depth of the interface features R _INT =1.

The bit depths of the remaining components of the address fields R _Y = {R _BLK , R _MOD , R _FPGA , R _AIU , R _CORE , R _ADR } are defined as R _Y = E(log ₂ (X-1)) + 1, where X: = {K, N, M, Q, L, N _ADR }, E(..) is the integer part.

Thus, the control sequence of the command for the service and working interfaces is as follows:

The 24 block for configuring the computing FPGA and the 30 block for routing the working interface decipher the control sequence of the command of the service and working interfaces, respectively, and execute the corresponding commands belonging to them, or transmit the control sequences of the command to the next computing module or the computing FPGA otherwise.

The following commands are transmitted via the direct channel of the service interface: “writing” of control registers and data buffer, as well as “reading” the state of a specified block 24 for configuring computing FPGAs, while the “writing” commands are accompanied by a data block of size where Lmax is the maximum buffer size of block 24 for configuring computing FPGAs.

When executing the "read" command, the data block is absent, and the dimension N _DAN corresponds to the size of the requested information about the state of block 24. The state of block 24 is returned via the reverse channel of the service interface, the format of which is identical to the format of the forward channel interface of the service interface for unambiguous identification of the source of information.

The following commands are transmitted via the direct channel of the working interface: "writing" the control registers and the data buffer at the initial address N _{of the ADR} of the specified N _AIU of the addressed executive device or the N _YAD of the co-calculator core, as well as "reading" the state of the specified N _AIU of the addressed executive device or the N _{YAD of the co-calculator core} and the result buffer at the initial address N _{of the ADR} of the specified N _AIU of the addressed executive device or the N _YAD of the co-calculator core when N _AIU = 0. In this case, the "writing" commands are accompanied by a data block of size N _DAN = {1…Lmax}, where Lmax is the maximum size of the data buffers of the addressed executive device or the co-calculator core. When executing the "read" command, the data block is absent, and the size N _DAN corresponds to the requested size of the state and the result buffer of the addressed executive device or the co-calculator core.

The result from the data buffer and the state of the specified addressed executive device or co-calculator core are returned via the reverse channel of the working interface, the format of which is completely identical to the format of the working interface of the direct channel, that is, the full address from which the sequence comes, only instead of data, the result or state goes for unambiguous identification of the source of information.

In this case, the response to the “read” commands will be the receipt of results and status, and the response to the “write” commands will be the transmission of the command completion status via the direct channel of the working interface, which is necessary for the control program to proceed to the execution of the next command.

In addition, the block 24 for configuring the computing FPGAs 23 ₁ , ..., 23 _M and the block 30 for routing the working interface carry out the transmission of commands received by them via the return channels of the service and, accordingly, working interfaces, and return their own states and results when executing the corresponding commands belonging to them.

In the proposed computing node, as in the prototype, the speed of exchange of user programs with computing FPGAs 23 ₁ , …, 23 _M is determined, first of all, by the speed of interaction with the RAM (not shown in the drawing) of the general-purpose computer 1, the speed of interaction via the working interface, the number of computing FPGAs in the node, and also the ratio of command (one word) and block (several words) interaction. Moreover, the bottleneck limiting the speed of exchange, with a sufficiently large number of computing FPGAs, is, as in the prototype, the RAM on which all transactions are closed during interaction.

However, there are quite broad classes of labor-intensive user tasks that require limited interaction with a general-purpose computer 1 via a working interface and a fairly lengthy process of software and hardware calculations for their implementation, for example, solving systems of linear equations with a distorted right-hand side by a method of completely enumerating the solution options with their verification for compliance with the expected.

In this case, to increase the computing power of the computing node, it is necessary to connect additional computing resources to it, which is easily implemented in the proposed computing node by connecting additional computing units to the expansion ports of the service 17, working 19 interfaces and the network monitoring port 10.

It should be noted that the proposed computing node has significantly fewer PCI-Express end devices, therefore the distribution of physical addresses of the general-purpose computer 1 RAM for their resources and aligned buffers for exchange in the direct memory access mode by the operating system is carried out more easily and does not change with the connection of additional computing units, since the distribution of memory for the addressable executive devices 36 ₁ , ..., 36 _Q and computing cores 40 ₁ , ..., 40 _L is carried out from the user tasks in the area of logical addresses.

The presence of a computing block identifier with a unique number in each additional memory 12 and in the computing blocks 11 ₁ , …, 11 _K , and of a computing module identifier with a unique number in each computing module 22 ₁ , …, 22 _M , ensures unambiguous binding of all computing blocks with computing modules 22 ₁ , …, 22 _N as part of the computing FPGAs 23 ₁ , …, 23 _M by binding the network monitoring port 10 (N _BLK ) to the numbers of the computing FPGAs 23 ₁ , …, 23 _M (N _FPGA ) from the computing modules 22 ₁ , …, 22 _N (N _MOD ).

Thus, a simple connection via the expansion ports of the service 17 and working 19 interfaces, as well as the network ports 10 for monitoring additional computing units with computing modules 22 ₁ , …, 22 _M , which include computing FPGAs 23 ₁ , …, 23 _M , increases the computing power of the proposed computing node.

EXAMPLE OF IMPLEMENTING THE INVENTION

The proposed computing node of the reconfigurable computing system can be implemented on the following elements:

General-purpose computer 1: Intel(R) Xeon(R) E2620V4 2.10 GHz 8 cores processor; 64 Gbyte RAM; 1 Tbyte hard drive; eight Adapters 2 ₁ , …, 2 ₈ , on interface FPGAs implemented on Xilinx chips of the XCAU15P-FFVB676 type with HD-mini SAS x4 768661011 connectors for connecting computing units 11 ₁ , …, 11 ₈ to the working interface, and RJ45 of the HR911105A type from HunRun for connecting to the service interface.

Eight computing blocks 11 ₁ , …, 11 ₈ as part of two computing modules 22 ₁ , …, 22 ₂ , each of which as part of eight computing FPGAs 23 ₁ , …, 23 ₈ - on Xilinx chips of the XCKU15P-FFVA1156 type.

Block 25 for monitoring and automatic control - on MAX6656 microcircuits from Maxim Integrated, TMP461AIRUNT from Texas Instruments.

Blocks 26 ₁ , …, 26 ₈ of individual control of co-calculators - using SI570 microcircuits.

Block 24 for configuring computing FPGAs - using a Fast Ethernet controller type W5500 from WIZnet and a microcontroller (MC) STM32F407V6.

Monitoring unit 14 - on the STM32F407V6 microcircuit.

The above information allows us to conclude that the proposed computing node of the reconfigurable computing system solves the stated problem and corresponds to the declared technical result - expansion of the arsenal of means for the same purpose and ensuring the possibility of increasing the computing power of the computing node by increasing the number of computing FPGAs in its composition.

Claims (11)

The computing node of the reconfigurable computing system contains an Ethernet network switch 8, an input network port 9, a group of K computing blocks 11 ₁ , …, 11 _K and a general-purpose computer 1 as part of a group of K adapters 2 ₁ , …, 2 _K for connecting computing blocks and a PCI-Express switch 3, wherein each adapter from group 2 ₁ , …, 2 _K includes a PCI-Express controller 7, an interface converter 6, a service interface port 4 and a working interface port 5, and each computing block from group 11 ₁ , …, 11 _K includes a network monitoring port 10, a cooling control unit 13, a monitoring unit 14, a power control unit 15, a computing block identifier memory 12, a receiving port 16 and an expansion port 17 of the service interface, a receiving port 18, an expansion port 19 and a retransmission unit 20 of the working interface, and a group of N computing modules 22 ₁ , …, 22 _N , each of which includes a computing module identifier memory 21, a monitoring and automatic control unit 25, a computing FPGA configuration unit 24, a group of M individual co-computer control units 26 ₁ , …, 26 _M , a group of M co-calculators 37 ₁ , …, 37 _M with individual power supply and a group of M computing FPGAs 23 ₁ , …, 23 _M , wherein each co-calculator from group 37 ₁ , …, 37 _M includes interface block 38 of the co-calculator, switch 39 of the co-calculator and a group of L computing cores 40 ₁ , …, 40 _L of the co-calculator, and each computing FPGA from group 23 ₁ , …, 23 _M includes receiving block 28, expansion block 29 and working interface routing block 30, automatic control block 31, adapter 32 of the co-calculator and switch 34 of addressable executive devices combined into dynamic region 33, a group of Q adapters 35 ₁ , …, 35 _Q addressable executive devices and a group of Q addressable executive devices 36 ₁ , …, 36 _Q , wherein the Ethernet network switch 8 is connected to the input network port 9, to the network ports 10 for monitoring the computing units 11 ₁ , ..., 11 _K and to the general-purpose computer 1, in which the PCI-Express switch 3 is connected to the controllers 7 of the PCI-Express adapters 2 ₁ , ..., 2 _K for connecting the computing units, in each of which the PCI-Express controller 7 is connected to the interface converter 6, which is connected to the port 4 of the service interface and the port 5 of the working interface, wherein for each of the adapters 2 ₁ , …, 2 _K for connecting the computing units, the ports 4 of the service interface are connected to the receiving ports 16 of the service interface, and the ports 5 of the working interface are connected to the receiving ports 18 of the working interface, of the corresponding computing units 11 ₁ , …, 11 _K of the same name, in which the network ports 10 of monitoring are connected to the monitoring unit 14, which is connected to the memory 12 of the identifier of the computing unit and the units 24 for configuring the computing FPGAs 23 ₁ , …, 23 _M of the computing modules 22 ₁ , …, 22 _N , with the cooling control unit 13, with the power control unit 15 and the monitoring and automatic control units 25 of the computing modules 22 ₁ , …, 22 _N , which are connected to the computing FPGAs 23 ₁ , …, 23 _M , with the co-calculators 37 ₁ , …, 37 _M with individual power supply, with individual control units 26 ₁ , …, 26 _M of the co-calculator and with automatic control units 31, which are connected to the individual control units 26 ₁ , …, 26 _M of the co-calculator, which are connected to the co-calculators of the same name 37 ₁ , …, 37 _M with individual power supply, in each of which the interface unit 38 of the co-calculator is connected to the switch 39 of the co-calculator, which is connected to the computing cores 40 ₁ , …, 40 _L of the co-calculators, in addition, the interface blocks 38 of the co-calculators 37 ₁ , ..., 37 _M are connected to the corresponding adapters 32 of the co-calculators, which in the static region 27 of each of the computing FPGAs 23 ₁ , ..., 23 _M are connected to the automatic control block 31 and the working interface routing block 30, which is connected to the receiving block 28 and to the working interface expansion block 29 inside the static region 27, and to the switch 34 of the addressable executive devices, which in the dynamic region 33 are connected to the corresponding addressable executive devices 36 ₁ , ..., 36 _Q of the same name, each of which is connected to the automatic control block 31 of the bus 41 of the blocking of the working frequency of the addressable executive devices, wherein in each of the computing units 11 ₁ , …, 11 _K the receiving port 16 of the service interface is connected to the unit 24 for configuring the computing FPGAs of the first 22 ₁ computing module from the group 22 ₁ , …, 22 _N , the expansion port 17 of the service interface is connected to the unit 24 for configuring the computing FPGAs of the last 22 _N computing module from the group 22 ₁ , …, 22 _N , the units 24 for configuring the computing FPGAs of the computing modules, starting from the first module 22 ₁ to the penultimate 22 _N-1 from the group 22 ₁ , …, 22 _N , are connected to the units 24 for configuring the computing FPGAs of the subsequent computing modules, starting from the second module 22 ₂ to the last module 22 _N from the group 22 ₁ , …, 22 _N , wherein in each computing module from the group 22 ₁ , …, 22 _N the blocks 24 for configuring the computing FPGAs are connected to the memory 21 of the identifier of the computing module, in addition, in each of the computing blocks 11 ₁ , …, 11 _K the receiving port 18 and the expansion port 19 of the working interface are connected to the working interface retransmission block 20, which is connected to the receiving block 28 of the working interface of the first computing FPGA 23 ₁ from the group 23 ₁ , …, 23 _M of the first computing module 22 ₁ from the group 22 ₁ , …, 22 _N and to the working interface expansion block 29 of the last 23 _M computing FPGA from the group 23 ₁ , …, 23 _M of the last computing module 22 _N from the group 22 ₁ , …, 22 _N , wherein for all computing modules, starting from the first module 22 ₁ to the penultimate 22 _N-1 from the group 22 ₁ , …, 22 _N, the blocks 29 of expansion of the working interface of the last computing FPGAs 23 _M from the group 23 ₁ , …, 23 _M are connected to the receiving blocks 28 of the working interface of the first computing FPGAs 23 ₁ from the group 23 ₁ , …, 23 _M of the subsequent computing modules, starting from the second computing module 22 ₂ to the last computing module 22 _N from the group 22 ₁ , …, 22 _N , in addition, in each computing module from the group 22 ₁ , …, 22 _N, the blocks 29 of expansion of the working interface of the computing FPGAs, starting from the first computing FPGA 23 ₁ to the penultimate computing FPGA 23 _M-1 from the group 23 ₁ , …, 23 _M are connected to the receiving blocks 28 of the working interface of the subsequent computing FPGAs, starting from the second computing FPGA 23 ₂ to the last computing FPGA 23 _M from the group 23 ₁ , …, 23 _M .