RU2700556C1 - Logic converter - Google Patents

Abstract

FIELD: computer equipment.

SUBSTANCE: invention relates to the computer equipment. Technical result is achieved due to logic converter intended for implementation of simple symmetric Boolean functions containing eight majority elements, wherein first inputs of (i+5)-th, fourth and fifth majority elements are respectively connected to the output of the i-th majority element, the first and second tuning inputs of the logic converter, first, second, (i+2)-th information inputs and first, second outputs of which are respectively connected to second, third inputs of fifth, third inputs of (i+5)-th majority elements and outputs of fourth, eighth majority elements.

EFFECT: providing parallel implementation of simple symmetric Boolean functions.

1 cl, 1 dwg

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Logical converters are known (RF patent 2294007, CL G06F 7/57, 2007; RF patent 2393527, CL G06F 7/57, 2010), which can be used to implement any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ ₄ , τ ₅ depending on five arguments - input binary signals x ₁ , ..., x ₅ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using known logic converters is limited functionality due to the fact that the parallel implementation of the functions τ ₁ , τ ₂ or τ ₄ , τ _{5 is} not performed.

The closest device of the same purpose to the claimed invention in terms of features is the logic converter adopted for the prototype (RF patent 2621281, class G06F 7/00, 2017), which contains eight major elements and implements any of the simple symmetric Boolean functions τ ₁ , τ ₂ , τ ₄ , τ ₅ , depending on five arguments - input binary signals x ₁ , ..., x ₅ ∈ {0,1}.

The reason that impedes the achievement of the technical result indicated below when using the prototype is limited functionality due to the fact that the parallel implementation of the functions τ ₁ , τ ₂ or τ ₄ , τ _{5 is} not performed.

The technical result of the invention is the expansion of functionality by ensuring the parallel implementation of simple symmetric Boolean functions τ ₁ , τ ₂ or τ ₄ , τ ₅ , depending on five arguments - input binary signals.

, (i+4)-го и второй, третий входы первого мажоритарных элементов соединены соответственно с вторыми входами (i+1)-го, (i+5)-го мажоритарных элементов и первым, вторым информационными входами логического преобразователя, (i+2)-й информационный и первый настроечный входы которого подключены соответственно к третьему входу (i+1)-го и первому входу i-го мажоритарных элементов, особенность заключается в том, что первые входы (i+5)-го, четвертого и пятого мажоритарных элементов соединены соответственно с выходом i-го мажоритарного элемента, первым и вторым настроечными входами логического преобразователя, первый, второй, (i+2)-й информационные входы и первый, второй выходы которого подключены соответственно к второму, третьему входам пятого, третьему входу (i+5)-го мажоритарных элементов и выходам четвертого, восьмого мажоритарных элементов.The specified technical result in the implementation of the invention is achieved by the fact that in a logical converter containing eight major elements, the outputs

, (i + 4) -th and second, third inputs of the first majority elements are connected respectively to the second inputs of the (i + 1) -th, (i + 5) -th majority elements and the first, second information inputs of the logic converter, (i + 2) the information and first tuning inputs of which are connected respectively to the third input of the (i + 1) th and first input of the i-th majority elements, the peculiarity is that the first inputs of the (i + 5) th, fourth and fifth majority elements are connected respectively to the output of the i-th majority element, the first and second the logic inputs of the logic converter, the first, second, (i + 2) -th information inputs and the first, second outputs of which are connected respectively to the second, third inputs of the fifth, third input of the (i + 5) -th major elements and the outputs of the fourth, eighth majoritarian elements.

The drawing shows a diagram of the proposed logical Converter.

, 1_i+4 и первый вход элемента 1_i+5 соединены соответственно с вторыми входами элементов 1_i+1, 1_i+5 и выходом элемента 1_i, а первые входы элементов

, 1₅ и выходы элементов 1₄, 1₈ подключены соответственно к первому, второму настроечным входам и первому, второму выходам логического преобразователя, первый и j-й информационные входы которого соединены соответственно с вторыми входами элементов 1₁, 1₅ и третьими входами элементов 1_j-1, 1_j+3.The logical Converter contains the majority elements 1 ₁ , ..., 1 ₈ , and the outputs of the elements

, 1 _{i + 4} and the first input of the element 1 _{i + 5 are} connected respectively to the second inputs of the elements 1 _{i + 1} , 1 _{i + 5} and the output of the element 1 _i , and the first inputs of the elements

, 1 ₅ and the outputs of the elements 1 ₄ , 1 _{8 are} connected respectively to the first, second tuning inputs and the first, second outputs of the logic converter, the first and jth information inputs of which are connected respectively to the second inputs of the elements 1 ₁ , 1 ₅ and the third inputs of the elements 1 _j-1 , 1 _{j + 3} .

имеем

где

и ∨, ⋅, # есть соответственно сигналы на его первом, втором, третьем входах и символы операций ИЛИ, И, Maj. Следовательно, сигналы на выходах элементов 1₄, 1₈ определяются системой выраженийThe work of the proposed logical Converter is as follows. At its first, second tuning inputs, the necessary signals ƒ _l , настройки ₂ ∈ {0,1} of constant tuning are fixed respectively. At its first, ..., fifth information inputs, binary signals x ₁ , ..., x ₅ ∈ {0,1} are supplied, respectively. At the output of the majority element

we have

Where

and ∨, ⋅, # are respectively signals on its first, second, third inputs and symbols of operations OR, AND, Maj. Therefore, the signals at the outputs of the elements 1 ₄ , 1 _{8 are} determined by the system of expressions

. Таким образом, при ƒ₁=1, ƒ₂=0 либо при ƒ₁=0, ƒ₂=1 на первом и втором выходах предлагаемого логического преобразователя соответственно получимwherein

. Thus, for ƒ ₁ = 1, ƒ ₂ = 0 or for ƒ ₁ = 0, ƒ ₂ = 1 at the first and second outputs of the proposed logic converter, we respectively obtain

и

and

or

и

and

where τ ₁ , τ ₂ , τ ₄ , τ ₅ are simple symmetric Boolean functions of five arguments x ₁ , ..., x ₅ (see page 126 in the book Pospelov DA Logical methods of analysis and synthesis of circuits. M .: Energy , 1974).

The above information allows us to conclude that the proposed logical converter has wider functionality compared to the prototype, as it provides parallel implementation of simple symmetric Boolean functions τ ₁ , τ ₂ or τ ₄ , τ ₅ , depending on five arguments - input binary signals.

Claims (1)

A logic converter designed to implement simple symmetric Boolean functions, containing eight majority elements, and the outputs of the ith

, (i + 4) -th and second, third inputs of the first majority element are connected respectively to the second inputs of the (i + 1) -th, (i + 5) -th majority elements and the first, second information inputs of the logic converter, (i + 2) the information and first tuning inputs of which are connected respectively to the third input of the (i + 1) th and first input of the i-th majority elements, characterized in that the first inputs of the (i + 5) -th, fourth and fifth major elements connected respectively to the output of the i-th majority element, the first and second tuning the logic converter, the first, second, (i + 2) -th information inputs and the first, second outputs of which are connected respectively to the second, third inputs of the fifth, third input of the (i + 5) -th major elements and the outputs of the fourth, eighth major elements .

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