RU2782234C2 - Encoding method and encoding device for polar code - Google Patents

Abstract

FIELD: wireless communication.

SUBSTANCE: invention relates to encoding in a wireless communication network. A communication device alternates the first bit sequence to obtain the first alternated sequence with a sequence number starting from a sequence number 0, wherein the first bit sequence contains bits for indication of timing, wherein bits for indication of timing contain a set of bits for indication of a synchronization signal block index (hereinafter – SSBI); wherein the set of bits for indication of SSBI is placed in positions specified by sequence numbers 2, 3, and 5 in the first alternated sequence. Then, devices add d first CRC bits in the first alternated sequence to obtain the second bit sequence, then, the second bit sequence is alternated in accordance with an alternating pattern to obtain the second alternated sequence, and, finally, the second alternated sequence is polarly encoded to obtain an encoded sequence.

EFFECT: increase in the reliability of transmission of a broadcasting channel.

39 cl, 9 dwg

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims the priority of Chinese Patent Application No. 201711148239.3 filed with the National Intellectual Property Office of China on November 17, 2017, titled "ENCODING METHOD AND ENCODING DEVICE FOR POLAR CODE", and Chinese Patent Application No. 201710843554.1, filed with the National Intellectual Property Office of China on September 18, 2017, entitled "ENCODING METHOD AND ENCODING DEVICE FOR POLAR CODE", all of which are hereby incorporated by reference in their entirety.

Technical field

[0002] Embodiments of the present invention relate to the field of encoding and decoding, and more specifically, to a polar encoding method and apparatus.

State of the art

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.[0003] In a communication system, channel coding is typically used to improve the reliability of data transmission to ensure communication quality. The polar code is a coding method that can achieve Shannon throughput with low encoding and decoding complexity. The polar code is a linear block code including information bit(s) and fixed bit(s). The polar code generation matrix is denoted as G _N , and the polar code encoding process is expressed as

. Here

is a binary row vector whose length is

.

[0004] However, when channel coding is performed on a Physical Broadcast Channel (PBCH) using a polar code, there is still room to further improve the transmission reliability of the broadcast channel.

The essence of the invention

[0005] This application provides a polar encoding method, including:

determining that the broadcast signaling payload includes D cyclic redundancy check (CRC) bits and M predictable information bits;

mapping M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and mapping D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, wherein M < K, and all of D, M, and K are positive integers;

performing polar encoding on the mapped bits to obtain encoded encoding bits; and

sending encoded bits.

[0006] This application proposes a polar encoding method, including:

polar encoding device, including:

a processor configured to: determine that the broadcast signaling payload includes D cyclic redundancy check (CRC) bits and M predictable information bits; map M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and map D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, wherein M < K, and all of D, M, and K are positive integers; and

perform polar encoding on the mapped bits to obtain encoded encoding bits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to describe the technical solutions in the embodiments of the present invention in more detail, the accompanying drawings necessary to describe the embodiments of the present invention are briefly described below. Obviously, the accompanying drawings in the following description show only some embodiments of the present invention, and a person skilled in the art can still obtain other drawings from these accompanying drawings without creative effort.

[0008] Figure 1 shows a wireless communication system in accordance with the embodiments described herein;

[0009] FIG. 2 is a schematic structural diagram of a system to which the polar coding method according to the present invention is applicable in a wireless communication environment;

[0010] FIG. 3 is a schematic flowchart of a polar encoding method according to one embodiment of the present invention;

[0011] Fig. 3a is a schematic flowchart of a polar encoding method according to one embodiment of the present invention;

[0012] Fig. 3b is a schematic flowchart of another polar coding method in accordance with one embodiment of the present invention;

[0013] FIG. 4 is a schematic block diagram of a polar encoding device according to one embodiment of the present invention;

[0014] FIG. 5 is a circuit diagram of an access terminal that performs the above polar coding method in a wireless communication system;

[0015] FIG. 6 is a schematic diagram of a system that performs the above polar coding method in a wireless communication environment; and

[0016] FIG. 7 is a schematic diagram of a system that performs the above polar coding method in a wireless communication environment.

Description of Embodiments

[0017] The technical solutions in the embodiments of the present invention are described below in detail with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part, and not all, of the embodiments of the present invention. All other embodiments obtained by a person skilled in the art based on the embodiments of the present invention without creative effort should fall within the protection scope of the present invention.

[0018] Terminology such as "component", "module", and "system" used in this document are used to refer to computer-related facilities, hardware, firmware, combinations of hardware and software, software, or software. that are being executed. For example, a component may be, but is not limited to being, a process that runs on a processor, a processor, an object, an executable, an executable thread, a program, and/or a computer. Both the computing device and the application that runs on the computing device can be components. One or more components may reside in a process and/or executable thread, and a component may be located on one computer and/or distributed between two or more computers. In addition, these components can be executed from various computer-readable media that store various data structures. For example, components may communicate using a local and/or remote process and based on, for example, a signal having one or more data packets (eg, data from two components communicating with another component in a local system, in a distributed system, and/or via network, such as the Internet, communicating with other systems using a signal).

[0019] In addition, embodiments are described with reference to an access terminal. An access terminal may also be referred to as a system, subscriber unit, subscriber station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, user device, or UE (user equipment). The access terminal may be a cellular phone, a cordless phone, a SIP (Session Initiation Protocol) phone, a WLL (wireless local loop), a PDA (personal digital assistant), a handheld device having a wireless communication function, a computing device, or other processing device connected to with a wireless modem. In addition, embodiments are described with reference to a base station. The base station may be configured to communicate with the mobile device. The base station may be a BTS (Base Transceiver Station) in GSM (Global System for Mobile Communications) or CDMA (Code Division Multiple Access) or may be an NB (Node B (NodeB)) in a WCDMA (Wideband Code Division Multiple Access) system or may be an eNB or eNodeB (evolved NodeB) in an LTE (Long Term Evolution) system, relay station or an access point, a base station device in a future 5G network, or the like.

[0020] In addition, each aspect or feature of the present invention may be implemented as a method, apparatus, or product that uses standard programming and/or development techniques. The term "product" as used in this application encompasses a computer program that can be accessed from any computer-readable device, medium or medium. For example, a computer-readable medium may include, but is not limited to: a magnetic storage device (such as a hard disk, floppy disk, or magnetic tape), an optical disc (such as a CD (Compact Disc)) or DVD (Digital Versatile Disk)), a smart card; and a flash memory-based storage device (for example, an EPROM (Erasable Programmable Read-Only Memory), card, memory card, or flash drive). In addition, the various storage media described herein may indicate one or more devices and/or other computer-readable media that are used to store information. The term "computer-readable medium" may include, but is not limited to, a radio channel and various other media that may store, contain, and/or carry instructions and/or data.

[0021] FIG. 1 shows a wireless communication system in accordance with the embodiments described herein. System 100 includes a base station 102. Base station 102 may include multiple sets of antennas. For example, one set of antennas may include antennas 104 and 106, another set of antennas may include antennas 108 and 110, and an additional set may include antennas 112 and 114. Two antennas are shown for each set of antennas. However, more or fewer antennas may be used in each set. Base station 102 may further include a transmitter circuit and a receiver circuit. One skilled in the art can appreciate that both the transmitter circuitry and the receiver circuitry may include a variety of components (eg, a processor, modulator, multiplexer, demodulator, demultiplexer, or antenna) associated with sending and receiving signals.

[0022] Base station 102 may communicate with one or more access terminals (eg, access terminal 116 and access terminal 122). However, it may be appreciated that base station 102 may communicate with virtually any number of access terminals that are similar to access terminals 116 and 122. Access terminals 116 and 122 may be, for example, cell phones, smartphones, laptop computers, portable communications devices, portable computing devices, satellite radios, global positioning systems, PDAs, and/or any other suitable devices capable of communicating in system 100. wireless connection. As shown in FIG. 1, access terminal 116 communicates with antennas 112 and 114. Antennas 112 and 114 send information to access terminal 116 on forward link 118 and receive information from access terminal 116 on reverse link 120. In addition, access terminal 122 communicates with antennas 104 and 106. Antennas 104 and 106 send information to access terminal 122 on forward link 124 and receive information from access terminal 122 on reverse link 126. For example, in an FDD (Frequency Division Duplex) system, the forward link 118 may use a different frequency band than the reverse link 120, and the forward link 124 may use a different frequency band than frequencies used by the reverse link 126. Furthermore, in a TDD (Time Division Duplex) system, forward link 118 and reverse link 120 may use the same frequency band, and forward link 124 and reverse link 126 may use the same the same frequency band.

[0023] Each set of antennas and/or antenna portions intended for communication is referred to as a sector of base station 102. forward links 118 and 124, the base station transmit antenna 102 may use beamforming to improve the signal-to-noise ratio of the forward link 118 of the access terminal 116 and the signal-to-noise ratio of the forward link 124 of the access terminal 122. In addition, compared with a base station that sends to all base station access terminals using a single antenna, when the base station 102 uses beamforming to send to access terminals 116 and 122 that are randomly distributed in the respective coverage area, the mobile the device in the neighboring cell experiences less interference.

[0024] During this time, base station 102, access terminal 116, and/or access terminal 122 may be a wireless communication sending device and/or a wireless communication receiving device. When sending data, the wireless communication sending device may encode the data for transmission. In particular, the wireless communication sending device may have (eg, generate, receive, or store) a specific number of information bits to be sent to the wireless communication receiving device using a channel. Such information bits may be included in a transport block (or multiple transport blocks) of data. The transport block may be segmented to generate multiple code blocks. In addition, the wireless communication sender may use a polar code encoder (not shown) to encode each code block to improve data transmission reliability and further secure communication quality.

[0025] FIG. 2 is a schematic block diagram of a system to which the polar coding method according to the present invention is applicable in a wireless communication environment. System 200 includes a wireless communication device 202. The wireless communication device 202 is shown sending data using a channel. While sending data is shown, wireless device 202 may additionally receive data (for example, wireless device 202 may send and receive data at the same time, wireless device 202 may send and receive data at different times, or a combination of these may be used. two cases, or the like) using a channel. The wireless communication device 202 may be, for example, a base station (e.g., base station 102 shown in Fig. 1), an access terminal (e.g., access terminal 116 shown in Fig. 1, access terminal 122 shown in Fig. 1) or the like.

[0026] The wireless communication device 202 may include a polar code encoder 204, a rate matcher 205, and a transmitter 206. Without fail, when the wireless communication device 202 receives data via a channel, the wireless communication device 202 may also include a receiver. The receiver may exist separately, or may be integrated with the transmitter 206 to form a transceiver.

[0027] The polar code encoder 204 is configured to encode data to be transmitted from the wireless communication device 202 to obtain an encoded polar code.

[0028] In this embodiment of the present invention, the polar encoder 204 is configured to: determine that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits; map M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and map D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, wherein M < K, and all of D, M, and K are positive integers; and perform polar encoding on the mapped bits to obtain encoded coding bits.

[0029] In addition, the transmitter 206 may subsequently transmit, on the channel, an output bit that has been processed by the rate matcher 205 and that has undergone rate matching. For example, transmitter 206 may send appropriate data to another wireless communication device (not shown).

[0030] The specific process in which the aforementioned polar code encoder performs processing is described below in detail. It should be noted that these examples are only intended to help those skilled in the art better understand the embodiments of the present invention, and not to limit the scope of the embodiments of the present invention.

[0031] FIG. 3 is a flow diagram of a polar encoding method in accordance with one embodiment of the present invention. The method shown in Fig. 3 may be performed by a wireless communication device, such as the polar encoder 204 in the wireless communication device shown in FIG. 2. The encoding method in FIG. 3 includes the following steps.

[0032] 301. Determining that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits, where M < K, and both M and K are positive integers.

[0033] It should be understood that broadcast signaling is carried on a broadcast channel, such as a physical broadcast channel (PBCH). The following describes in detail the encoding method using PBCH as an example. However, the present invention is not limited to PBCH.

[0034] The PBCH payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits.

[0035] It should be understood that the PBCH payload is classified into the following four types depending on whether the content of the access service is variable.

[0036] The first type of bits includes reserved bits or similar information bits whose values are completely constant, or bits whose values are directly determined according to the protocol.

[0037] The second type of bits includes information bits whose values remain unchanged, namely information bits that remain unchanged in the Master Information Block (MIB); or alternatively can be understood as information bits whose values in the MIB cannot be directly determined according to the protocol, but must be discovered during network access and remain unchanged. For example, the second type of bits may include one or more of system bandwidth related information, subcarrier information, system configuration numerology indication information supported by the base station (BS), universal control channel information, and the like.

[0038] The third type of bits includes predictable information bits in which the content of the time sequence information is changed, namely, the predictable information part of the MIB in which the content of the time sequence information is changed.

[0039] It should be understood that the use case for bits of the third type does not occur at the initial access stage.

[0040] For example, the third type of bits includes one or more of a system frame number (SFN), a sync sequence number, a SS block SS, a half frame indicator (HFI), and the like.

[0041] The fourth type of bits include unpredictable information bits, namely the unpredictable information part of the MIB, in which information can change at any time. For example, for the control channel configuration information of the current frame, the configuration may appear repeatedly, but may change at any time.

[0042] Unlike bits of the third type, bits of the fourth type must be respectively detected each time.

[0043] For example, the fourth type of bits includes current system configuration parameter numerology indication information and SIB resource indication information.

[0044] If there is a fourth type of MIB information, the corresponding CRC bits also belong to the fourth type of bits.

[0045] It should be understood that if the MIB does not include bits of the fourth type, then the CRC bits may be classified as bits of the third type; or if the MIB does not include bits of the fourth type, then the CRC bits are classified as bits of the fourth type; or if the MIB includes both bits of the third type and bits of the fourth type, then the CRC bits are classified as bits of the fourth type. In this case, when CRC is classified, the following is mainly considered: if there is a third type bit set, then the values of the CRC bits depend on the third type bits in the MIB information; or, if there is a fourth type of bits, then the values of the CRC bit depend on the fourth type bits in the MIB information. Therefore, the above classification is performed for the CRC bits.

[0046] Based on the above classification, the PBCH payload is classified into the above four types of bit sets. It is understood that the PBCH payload may include one or more of the above four types of bit sets.

[0047] Depending on whether the predictable information bit is predictable, the first type to the third type bits may be further classified as predictable information bits, while the fourth type bits may be classified as unpredictable information bits. The M predictable information bits include one or more of the following bit combinations: M ₁ bits of the first type, M ₂ bits of the second type, or M ₃ bits of the third type. The first type bit is a reserved bit. The second type bit includes an information bit, the value of which remains unchanged. The third type bit is a predictable information bit whose value is the content of the time sequence information and is changed. All of M ₁ , M ₂ and M ₃ are positive integers, M ₁ <= M, M ₂ <= M and M ₃ <= M.

[0048] 302. Mapping M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and mapping D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, with M < K, and all of D, M and K are positive integers.

[0049] In general, based on the above classification of the bit sets and the order from the first type to the fourth type, the PBCH payload content is mapped to the polar code information bit set in ascending order of reliability of the subchannels in the information bit set. The specific display method varies according to the different classified types.

[0050] When the same type of content is mapped to subchannels in the polar code information bit set, the order of different bits of the same type may change. For example, the M ₃ bits of the third type include M ₁ system frame number information bits and M ₂ sync block sequence number information bits SS. When the system frame number bits and the sync block sequence number bits SS in bits of the third type are mapped to subchannels in the polar code information bit set, M ₁ system frame number bits are mapped to M ₁ information bits in M low reliability information bits, and M ₂ information bits of the SS block sequence number are mapped to M ₂ low reliability information bits in the remaining information bits of the M low reliability information bits; or M ₂ information bits of the SS block sequence number are mapped to M ₂ information bits in the M low reliability information bits, and M ₁ system frame number bits are mapped to M ₁ low reliability information bits in the remaining information bits of the M low reliability information bits.

[0051] The SS block carries a primary synchronization sequence and a secondary synchronization sequence.

[0052] Broadcast signaling typically includes a few reserved bits that do not actually carry any useful information. Thus, during polar encoding, the bits are classified and the classified type bits are mapped to low reliability information bits according to some rule. Even if the reserved bits change during transmission, correct decoding of the broadcast signaling is not enabled.

[0053] It should also be understood that the form of reliability measurement is not limited in this embodiment of the present invention. For example, one can refer to an existing polar code reliability metric such as bit capacity, Bhattacharya distance parameter, or error probability.

[0054] Optionally, the M predictable information bits include one or more of the following bit combinations: M ₁ bits of the first type, M ₂ bits of the second type, or M ₃ bits of the third type. The first type bit is a reserved bit. The second type bit includes an information bit, the value of which remains unchanged. The third type bit is a predictable information bit whose value is the content of the time sequence information and is changed. All of M ₁ , M ₂ and M ₃ are positive integers, M ₁ <= M, M ₂ <= M and M ₃ <= M.

[0055] Further, optionally, when the M predictable information bits include M ₁ bits of the first type and M ₂ bits of the second type, or include M ₁ reserved bits and M ₃ bits of the second type, the M ₁ bits of the first type are displayed in M ₁ low reliability information bits in M information bits, and

M2 bits of the second type are mapped to M2 low reliability information bits in the remaining information bits of the M information bits; or

M ₁ bits of the first type are mapped to M ₁ low reliability information bits in M information bits, and

The M ₃ bits of the second type are mapped to M 3 low reliability information bits in the remaining information bits of the M information bits.

[0056] Optionally, when the M predictable information bits include M ₁ bits of the first type, M ₂ bits of the second type, and M ₃ bits of the second type, then the M ₁ bits of the first type are mapped to M ₁ low reliability information bits in the M information bits;

M ₂ bits of the second type are mapped to M ₂ low reliability information bits in (MM ₁ ) information bits; and

M ₃ bits of the third type are mapped to M ₃ low reliability information bits in (MM ₁ -M ₂ ) bits.

[0057] The payload further comprises J unpredictable information bits; and

J unpredictable information bits are mapped to J low reliability information bits in (K-M-D) information bits, with J < K and J is a positive integer.

[0058] Possible sequences, described below using examples, for sorting the above four classified types of bit information in ascending order of polar code reliability may include, but are not limited to, one or more of the following:

[0059] Example 1.1: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type, CRC bits.

[0060] Based on the previous example of each type of bits and the above sequence, the example is: first type bits including a reserved bit, second type bits including bandwidth information and universal control channel configuration information, third type bits , including time sequence information, bits of the fourth type, including the SIB indication, CRC bits.

[0061] The bits are mapped to the low reliability position in order of increasing polar code reliability in the above sorting order.

[0062] Example 1.2: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type, CRC bits.

[0063] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including universal control channel configuration information and bandwidth information, third type bits, including time sequence information, bits of the fourth type, including SIB indication, CRC bits.

[0064] In example 1.2, bits of the second type are sorted in internal sequence. Sequences of bits of the same type can be interchanged.

[0065] The bits are mapped to the low reliability position in order of increasing polar code reliability in the above sorting order.

[0066] Example 1.3: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type, CRC bits.

[0067] Based on the previous example of each type of bits and the above sequence, the example is: first type bits including a reserved bit, second type bits including universal control channel configuration information, time sequence information, and bandwidth information, second type bits and third type bits including time sequence information, fourth type bits including SIB indication, CRC bits.

[0068] The difference between the example in this case and the above example is that bits of the second type can be combined with bits of the third type. In other words, in the classified bit sets, the bits of the second type and the bits of the third type are classified as the same type. This type, after combining, may be classified as bits of the second type, or may be classified as bits of the third type. It's not limited here.

[0069] The bits are mapped to the low reliability position in order of increasing polar code reliability in the above sorting order.

[0070] Example 1.4: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type, CRC bits.

[0071] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits, and third type bits including universal control channel configuration information, bandwidth information, and time sequence information, bits of the fourth type, including an indication of SIB, CRC.

[0072] The difference between the example in this case and Example 1.3 above is that bits of the second type can be combined with bits of the third type, and the set of bits after combining includes bits of different types.

[0073] The bits are mapped to the low reliability position in ascending order of polar code reliability in the aforementioned sorting order.

[0074] Example 1.5: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, CRC.

[0075] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including universal control channel configuration information and bandwidth information, third type bits, including time sequence information, CRC.

[0076] The difference between the example in this case and the example above is that the set of bits included in the PBCH payload can be any combination of the above four types of bits. For example, the PBCH payload includes the aforementioned classified first type bits, second type bits, and third type bits. Of course, it's not limited to this. The PBCH payload may alternatively include only classified first type bits, third type bits, and fourth type bits, such as in Example 1.6.

[0077] The bits are mapped to the low reliability position in order of increasing polar code reliability in the above sorting order.

[0078] Example 1.6: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the third type, bits of the fourth type, CRC.

[0079] Based on the previous example of each type of bits and the above sequence, the example is: first type bits including a reserved bit, third type bits including time sequence information, fourth type bits including SIB indication, CRC .

[0080] The difference between the example in this case and the example above is that the set of bits included in the PBCH payload may be any combination of the above four types of bits. For example, the PBCH payload includes the aforementioned classified first type bits, third type bits, and fourth type bits. The PBCH payload may alternatively include classified first type bits and third type bits, such as in Example 1.7.

[0081] Example 1.7: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the third type, CRC.

[0082] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, third type bits including time sequence information, CRC.

[0083] Example 1.8: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, CRC.

[0084] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including bandwidth information, CRC.

[0085] The above set of unions of classified bit types can be freely selected. It's not limited here. In general, the above classification and sorting rules are followed.

[0086] The above mapping method can be implemented by introducing interleaving of the information to be encoded. For example:

[0087] For a polar code whose code length is 512, the total length of the MIB and CRC bits is 72. Therefore, the 72 highest reliability subchannels in the polar code are selected as the set of information bits, and the sequence numbers of the 72 subchannels are sorted as follows in order of increasing reliability : [484; 430; 488; 239; 378; 459; 437; 380; 461; 496; 351; 467; 438; 251; 462; 442; 441; 469; 247; 367; 253; 375; 444; 470; 483; 415; 485; 473; 474; 254; 379; 431; 489; 486; 476; 439; 490; 463; 381; 497; 492; 443; 382; 498; 445; 471; 500; 446; 475; 487; 504; 255; 477; 491; 478; 383; 493; 499; 502; 494; 501; 447; 505; 506; 479; 508; 495; 503; 507; 509; 510; 511].

[0088] The results obtained after the Cyclic Redundancy Check (CRC) performed on the MIB are a ₀ , a ₁ , ..., a ₉ , a ₁₀ , ..., a ₁₄ , a ₁₅ , ..., a _{29 , a 30 ,} .

[0089] The above description may be presented using Fig. 3a. Based on the above mapping method, this application further provides another mapping method, such as the case where D-CRC exists.

[0090] When there is a D-CRC, discrete CRC bits occupy some positions of the subchannels. In this case, from the first type bit to the fourth type bit, the positions of the CRC discrete bits are considered first. In the polar code information bit set, the sub-channels occupied by the CRC bits are eliminated, the remaining sub-channels are sorted in ascending order of reliability, the CRC bits in mapping are eliminated, the remaining bits are classified based on the above four types in the manner in the above embodiments, and then the classification results based on the bits classified types in previous embodiments are mapped to a set of information bits.

[0091] In addition, for example, by eliminating the polar code subchannels occupied by discrete CRC bits, several possible MIB sort sequences are as follows:

[0092] Possible sequences, described below using examples, for sorting the above four classified types of bit information in ascending order of polar code reliability may include, but are not limited to, one or more of the following:

[0093] Example 2.1: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type.

[0094] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including bandwidth information and universal control channel configuration information, third type bits, including time sequence information, bits of the fourth type, including the SIB indication.

[0095] The bits are mapped in the low reliability position, excluding the CRC position, in order of increasing polar code reliability in the above sorting order.

[0096] Example 2.2: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type.

[0097] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including universal control channel configuration information and bandwidth information, third type bits, including time sequence information, bits of the fourth type, including SIB.

[0098] The bits are mapped to the low reliability position excluding the CRC position in order of increasing polar code reliability in the aforementioned sorting order.

[0099] Example 2.3: The sort sequence, in order of increasing polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type.

[00100] Based on the previous example of each bit type and the above sequence, the example is: the first type bits including the reserved bit, the bits obtained after combining the second type bits and the third type bits including the universal control channel configuration information, time sequence information and bandwidth information, bits of the fourth type, including the SIB indication.

[00101] The bits are mapped to the low reliability position excluding the CRC position in order of increasing polar code reliability in the above sorting order.

[00102] The SIB in the above embodiment may be SIB information, or may be SIB resource indication information.

[00103] Example 2.4: The sort sequence, in ascending order of polar code reliability, of bits including the four classified bit types may be:

bits of the first type, bits of the second type, bits of the third type, bits of the fourth type.

[00104] Based on the previous example of each type of bits and the above sequence, the example is: the first type bits including the reserved bit, the bits obtained after combining the second type bits and the third type bits including the universal control channel configuration information, bandwidth information and time sequence information, fourth type bits include SIB.

[00105] The bits are mapped to the low reliability position excluding the CRC position in order of increasing polar code reliability in the above sorting order.

[00106] Example 2.5: The polar code reliability ascending sort sequence may include bits including four classified bit types, may be: first type bits, second type bits, third type bits.

[00107] Based on the previous example of each bit type and the above sequence, the example is: first type bits including a reserved bit, second type bits including universal control channel configuration information and bandwidth information, third type bits, including time sequence information.

[00108] The above may alternatively include first type bits, third type bits, and fourth type bits, where the sequence is: first type bits including a reserved bit, third type bits including time sequence information, and fourth type bits. type, including SIB; or

include first type bits and third type bits, where the corresponding sequence is: first type bits including a reserved bit and third type bits including time sequence information; or

include first type bits and second type bits, where the corresponding sequence is: first bits including the reserved bit, and second type bits including bandwidth information.

[00109] The bits are mapped to the low reliability position excluding the CRC position in order of increasing polar code reliability in the aforementioned sorting order.

[00110] The placement of the CRC position does not strictly meet the above criteria.

[00111] For a polar code whose code length is 512, the total length of the MIB and CRC is 72. Therefore, the 72 highest reliability subchannels in the polar code are selected as the set of information bits. The sorting of the 72 subchannel sequence numbers in order of increasing reliability is the same as described previously.

[00112] The 72 data bits include 24 CRC bits, and the D-CRC interleaver generated using the CRC is as follows:

[1, 3, 6, 9, 12, 14, 16, 18, 19, 21, 23, 26, 27, 28, 30, 31, 34, 35, 37, 40, 42, 46, 47, 48, 0 , 2, 4, 7, 10, 13, 15, 17, 20, 22, 24, 29, 32, 36, 38, 41, 43, 49, 5, 8, 11, 25, 33, 39, 44, 50 , 45, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71].

[00113] Since the length of the MIB part is 72-24=48, the CRC bits obtained after D-CRC interleaving are placed in positions whose sequence numbers are greater than 48 in the previous sequence.

[00114] Based on the combination of the D-CRC interleaving pattern and the set of information bits of the polar position code to place the D-CRC information in the polar code, the following is obtained:

[443, 478, 489, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 509, 510, 511].

[00115] The bits to accommodate the D-CRC are removed from the set of information bits of the polar code. The sorting sequence of the remainder in ascending order of reliability is:

[484, 430, 488, 239, 378, 459, 437, 380, 461, 351, 467, 438, 251, 462, 442, 441, 469, 247, 367, 253, 375, 444, 470, 483, 415 , 485, 473, 474, 254, 379, 431, 486, 476, 439, 490, 463, 381, 382, 445, 471, 446, 475, 487, 255, 477, 383, 447, 479]. The above detailed description can be presented in Fig. 3b.

[00116] The present application further provides an embodiment. Based on the above first embodiment and the second embodiment, discrete CRC bits and other CRC bits are sorted in a specific manner. Discrete CRC bits are sorted by the method in the previous second embodiment, and then the other CRC bits are sorted by the method in the first embodiment. Details are not described here again. In another example, it is assumed that the result obtained after performing a Cyclic Redundancy Check (CRC) on broadcast signaling (signaling carried over the PBCH) is a ₀ , a ₁ , ..., a ₁₃ , a ₁₄ , …, a ₂₃ , a ₂₄ , …, a ₃₉ , where a ₁₄ , …, a ₂₃ are reserved bits (10 bits) and a ₂₄ , …, a ₃₉ correspond to check bits (and may include a mask). The 10 low reliability information bits in the polar code are assumed to be {79, 106, 55, 105, 92, 102, 90, 101, 47, 89}. In this case, when 10 reserved bits are mapped to 10 low reliability information bits, u(79) = a ₁₄ , u(106) = a ₁₅ , u(55) = a ₁₆ , u(105) = a ₁₇ , u( 92) = a ₁₈ , u(102) = a ₁₉ , u(90) = a ₂₀ , u(101) = a ₂₁ , u(47) = a ₂₂ and u(89) = a ₂₃ can be obtained using an interleaver to further complete the process of mapping the reserved bits to information bits. Similarly, to map the remaining broadcast signaling bits to the remaining information bits in the polar code, refer to the above method. To avoid repetition, the details are not described here again.

[00117] 303. Performing Polar code encoding on mapped bits to obtain encoded encoding bits.

[00118] 304. Send encoding bits.

[00119] For example, when a wireless communication device prepares to send broadcast signaling using a channel (Physical Broadcast Channel, PBCH), polar coding may first be performed on the broadcast signal. The result of encoding a polar code can be represented by formula (1):

(1)

(one)

- двоичный вектор-строка, длина которого равна

;

является

матрицей,

,

является длиной кодированных битов кодирования,

,

,

является транспонированной матрицей и

является степенью Кронекера (степенью Kronecker) и определяется как

.where

is a binary row vector whose length is

;

is

matrix,

,

is the length of the encoded coding bits,

,

,

is a transposed matrix and

is the Kronecker degree (Kronecker degree) and is defined as

.

используются для переноса информации (то есть информации, которая должна быть отправлена принимающей стороне). Эти биты называются информационными битами. Набор индексов этих битов обозначен как A. Оставшиеся биты, называемые замороженными битами, имеют фиксированные значения и могут, например, обычно быть установлены в 0.[00120] In the process of encoding a polar code, some bits in

are used to carry information (that is, information to be sent to the receiving party). These bits are called information bits. The index set of these bits is designated as A. The remaining bits, called frozen bits, have fixed values and can, for example, normally be set to 0.

[00121] According to the method in this embodiment of the present invention, M predictable information bits are mapped to M low reliability information bits in K polar code information bits, respectively, and D cyclic redundancy check (CRC) bits are mapped to D high reliability information bits in the remaining information bits from the K information bits to obtain the mapped bits. Then, encoded polar codes can be obtained based on the encoding process shown in formula (1). In other words, encoded coding bits are obtained.

, где

является набором информационных битов в

,

является вектором-строкой, длина которого равна K, K является количеством информационных битов,

является подматрицей, полученной с использованием строки, соответствующий индексам в наборе A в

, и

представляет собой матрицу K*N. [00122] The result of the encoded polar code after the encoding processing is performed using the polar code encoder can be simplified as

, where

is a set of information bits in

,

is a row vector whose length is K, K is the number of information bits,

is a submatrix obtained using the row corresponding to the indices in set A in

, and

is a K*N matrix.

[00123] Based on the above technical solution, at the time of sending broadcast signaling, mapping is first performed based on the reliability values of the information bits in the polar code, and then polar encoding is performed on the mapped bits. In this case, useful bits in the broadcast signaling can be prevented from being mapped to low reliability information bits, which improves the transmission reliability of the broadcast signaling.

[00124] Optionally, in one embodiment, the M low reliability information bits include M information bits whose reliability is less than a predetermined threshold, or the M low reliability information bits include M lowest reliability information bits in the K information bits.

[00125] Optionally, in another embodiment, before the M reserved broadcast signaling bits are respectively mapped to the M low reliability information bits in the K polar code information bits, the K information bits may be sorted first based on the reliability values from the K information bits. In this case, when the M reserved bits of the broadcast signaling are respectively mapped to the M low reliability information bits in the K information bits of the polar code, the M reserved bits may respectively be mapped to the M low reliability information bits in the K information bits based on the sort result.

[00126] For example, the description is made using an example in which the code length of the polar code is 128 bits. The polar code includes 40 information bits. The 40 information bits are sorted in descending order of reliability to obtain sorted indices as follows:

{127, 126, 125, 23, 119, 111, 95, 124, 122, 63, 121, 118, 117, 115, 110, 109, 107, 94, 93, 103, 91, 62, 120, 87, 61 , 116, 114, 59, 108, 113, 79, 106, 55, 105, 92, 102, 90, 101, 47, 89}.

[00127] It is assumed that the length of the broadcast signal is 40 bits. 40 bits include 10 reserved bits. In this case, the 10 reserved bits shall be respectively mapped to information bits corresponding to {79, 106, 55, 105, 92, 102, 90, 101, 47, 89}. The rest of the broadcast signaling bits are mapped to information bits other than the previous 10 bits.

[00128] Optionally, in another embodiment, the information bit reliability value is determined based on the bit capacity, the Bhattacharya distance parameter of the Bhattacharya distance, or the error probability.

[00129] For example, when the bit capacity is used to measure the reliability of information bits, the bit capacity of each information bit in the polar code can be determined first, and the bit capacity value is used to represent the reliability value of the information bit, whereby a bit having a large capacity has a high reliability.

[00130] Alternatively, when the Bhattacharya parameter is used to measure the reliability of information bits, the Bhattacharya parameter of each information bit in the polar code may be determined, and the value of the Bhattacharya parameter is used to represent the reliability value of the information bit, wherein the information bit having a small parameter value Bhattacharya, has high reliability.

[00131] FIG. 4 is a schematic block diagram of a polar encoding device according to one embodiment of the present invention. Encoder 400 in FIG. 4 may be located in a base station or access terminal (eg, base station 102 and access terminal 116) and includes a mapper 401 and an encoder 402.

[00132] The mapper 401 is configured to: map the M reserved broadcast signaling bits, respectively, into M low reliability information bits in the K polar code information bits, and map the remaining broadcast signaling bits into the remaining information bits of the K information bits to obtain mapped bits, where M < K, and both M and K are positive integers.

[00133] It should be understood that broadcast signaling is signaling carried on a broadcast channel, such as a physical broadcast channel (PBCH). Broadcast signaling typically includes a few reserved bits that do not actually carry any useful information. In this case, during the encoding of the polar code, the reserved bits are mapped to low reliability information bits. Even if the reserved bits change during transmission, correct decoding of the broadcast signaling is not enabled.

[00134] It should also be understood that the form of reliability measurement is not limited in this embodiment of the present invention. For example, one can refer to an existing polar code reliability metric such as bit capacity, Bhattacharya distance parameter, or error probability.

[00135] For example, it is assumed that the result obtained after performing a Cyclic Redundancy Check (CRC) on broadcast signaling (signaling carried on the PBCH) is a ₀ , a ₁ , ..., a ₁₃ , a ₁₄ , ..., a ₂₃ , a ₂₄ , ... and a ₃₉ . a ₁₄ , ..., a ₂₃ are reserved bits (10 bits), and a ₂₄ , ..., a ₃₉ correspond to check bits (and may include a mask). The 10 low reliability information bits in the polar code are assumed to contain {79, 106, 55, 105, 92, 102, 90, 101, 47, 89}. In this case, when 10 reserved bits are mapped to 10 information bits of low reliability information bits, u(79) = a ₁₄ , u(106) = a ₁₅ , u(55) = a ₁₆ , u(105) = a ₁₇ , u( 92) = a ₁₈ , u(102) = a ₁₉ , u(90) = a ₂₀ , u(101) = a ₂₁ , u(47) = a ₂₂ and u(89) = a ₂₃ can be obtained using an interleaver to further complete the process of mapping the reserved bits to information bits. Similarly, to map the remaining broadcast signaling bits to the remaining information bits in the polar code, refer to the above method. To avoid repetition, the details are not described here again.

[00136] The encoder 402 is configured to perform polar encoding on the mapped bits to obtain encoded encoding bits.

[00137] Here, for the process of performing polar encoding on the mapped bits by the encoding block, refer to the description in the previous embodiments. To avoid repetition, the details are not described here again.

[00138] Based on the above technical solution, at the time of sending the broadcast signaling, mapping is first performed based on the reliability values of the information bits in the polar code, and then polar encoding is performed on the mapped bits. In this case, useful bits in the broadcast signaling can be prevented from being mapped to low reliability information bits, which improves the transmission reliability of the broadcast signaling.

[00139] Optionally, in one embodiment, the M low reliability information bits include M information bits whose reliability is less than a predetermined threshold, or the M low reliability information bits include M lowest reliability information bits in the K information bits.

[00140] Optionally, in another embodiment, the encoder 400 further includes a sorter 403 .

[00141] The sorter 403 is configured to sort the K information bits based on the reliability values of the K information bits.

[00142] In this case, the encoding unit 402 is specifically configured to map M reserved bits, respectively, to M low reliability information bits in K information bits based on the sort result.

[00143] For example, the description is made using an example in which the code length of the polar code is 128 bits. The polar code includes 40 information bits. The 40 information bits are sorted in descending order of reliability to obtain sorted indices as follows:

{127, 126, 125, 23, 119, 111, 95, 124, 122, 63, 121, 118, 117, 115, 110, 109, 107, 94, 93, 103, 91, 62, 120, 87, 61 , 116, 114, 59, 108, 113, 79, 106, 55, 105, 92, 102, 90, 101, 47, 89}.

[00144] It is assumed that the length of the broadcast signal is 40 bits. 40 bits include 10 reserved bits. In this case, the 10 reserved bits shall be respectively mapped to information bits corresponding to {79, 106, 55, 105, 92, 102, 90, 101, 47, 89}. The remaining broadcast signaling bits are mapped to information bits other than the previous 10 bits.

[00145] Optionally, in another embodiment, the reliability value of the information bit is determined based on the bit capacity, the Bhattacharya parameter of the Bhattacharya distance, or the error probability.

[00146] For example, when the bit capacity is used to measure the reliability of information bits, the bit capacity of each information bit in the polar code can be determined first, and the bit capacity value is used to represent the reliability value of the information bit, where a bit having a large capacity has a high reliability. .

[00147] Alternatively, when the Bhattacharya parameter is used to measure the reliability of information bits, the Bhattacharya parameter of each information bit in the polar code can be determined, and the value of the Bhattacharya parameter is used to represent the reliability value of the information bit, where the information bit having a small Bhattacharya parameter value , has high reliability.

[00148] Optionally, in another embodiment, the encoder 400 further includes an interleaver 404 and a capture unit 405. The interleaver 404 and the capture unit 405 may be located in the rate matcher 205 in the wireless communication device 202 shown in FIG. In this case, the rate matcher 205 and the polar encoder 204 together form a polar encoder 400 .

[00149] The interleaver 404 is configured to perform sorting and congruent interleaving on the encoded coding bits to obtain the interleaved coding bits.

битов перемеженных битов кодирования в циклический буфер на основе предварительно установленного значения

.[00150] The capture unit 405 is configured to input the first

bits interleaved encoding bits into a circular buffer based on a preset value

.

первые

битов закодированных битов, которые получены после инверсионной обработки.[00151] Alternatively, capture unit 405 is configured to: perform inversion processing on the interleaved coding bits; and enter into a circular buffer based on a preset value

first

bits of encoded bits that are obtained after inversion processing.

относится к формату кадра широковещательной сигнализации. Таким образом, этот вариант осуществления настоящего изобретения может дополнительно улучшить кодовую скорость.[00152] It should be understood that the preset value

refers to the broadcast signaling frame format. Thus, this embodiment of the present invention can further improve the code rate.

[00153] Optionally, in another embodiment, the interleaver 404 is specifically configured to: obtain a congruent sequence based on the length of the encoded coding bits; then perform sorting processing on the congruent sequence according to a predetermined rule to obtain a reference sequence and determine a display function based on the congruent sequence and the reference sequence; and finally perform interleaving of the encoded coding bits according to the mapping function to obtain the interleaved coding bits.

[00154] In particular, for the process in which the interleaver 404 performs interleaving on the encoded coding bits, reference should be made to the detailed description in the foregoing embodiment. To avoid repetition, the details are not described here again.

[00155] Optionally, in another embodiment, the interleaver 404 is specifically configured to determine a congruent sequence according to the following formula (3):

,

,

,

(3)

,

(3)

длина кодированных битов кодирования,

,

,

и

- это конкретные параметры, а также

- это конгруэнтная последовательность. where -

length of encoded coding bits,

,

,

and

are specific parameters, and

is a congruent sequence.

- это длина кодированных битов кодирования, означает, что

- это длина кода полярного кода. [00156] It should be understood that what

is the length of the encoded coding bits, means that

is the length of the polar code.

представляет собой модуль,

,

представляет собой множитель,

представляет собой приращение и

представляет собой начальное значение. [00157] In particular, Q is assumed to be a given positive integer. When two integers A and B are individually divided by Q, the resulting remainders are the same. In this case, A and B are said to be congruent for the module Q. Formula (2) is a linear congruent method, where

is a module

,

is a multiplier

is an increment and

represents the initial value.

,

,

, и

.[00158] Optionally, alternatively

,

,

, and

.

[00159] FIG. 5 is a schematic diagram of an access terminal that helps to perform the above polar coding method in a wireless communication system. The access terminal 500 includes a receiver 502. The receiver 502 is configured to: receive a signal from, for example, a receive antenna (not shown), perform a typical operation (e.g., filter, amplify, or downconvert) the received signal, and digitize the adjusted signal to obtaining a discretized signal (samples). Receiver 502 may be, for example, a Minimum Mean Square Error (MMSE) receiver. Access terminal 500 may further include a demodulator 504. Demodulator 504 may be configured to demodulate the received symbol and provide the symbol to processor 506 for channel estimation. Processor 506 may be a dedicated processor configured to parse information received by receiver 502 and/or generate information sent by transmitter 516; or a processor configured to control one or more components of the access terminal 500; and/or a controller configured to parse the information received by the receiver 502, generate the information sent by the transmitter 516, and control one or more components of the access terminal 500.

[00160] The access terminal 500 may further include a memory 508. The memory 508 may be operatively coupled to the processor 506 and store the following data: data to be sent, data received, and any other relevant information associated with performing various actions and functions. described in this document. Memory 508 may additionally store a protocol and/or algorithm associated with the processing of the polar code.

[00161] It is understood that the data storage device (e.g., memory 508) described herein may be volatile memory (short-term storage) or non-volatile memory (long-term storage), or may include both volatile memory and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), electrically erasable programmable read-only memory (Electrically EPROM, EEPROM) or flash memory. The volatile memory may include random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, such as Static Random Access Memory (Static RAM, SRAM), Dynamic Random Access Memory (Dynamic RAM, DRAM), Synchronous Dynamic Random Access Memory (Synchronous DRAM). ) , SDRAM), Dual Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, DDR SDRAM), Enhanced Synchronous Dynamic Random Access Memory (Enhanced SDRAM, ESDRAM), Synchlink DRAM (Synchlink DRAM, SLDRAM), and Direct Access Random Access Memory (Rambus RAM, DR RAM). Memory 508 in the system and method described herein is intended to include, but is not limited to, these storage devices and any other appropriate types of storage devices.

[00162] In addition, the access terminal 500 further includes a polar code encoder 512 and a rate matcher 510. In actual application, receiver 502 may be further connected to rate matcher 510. The rate matcher 510 may be substantially similar to the rate matcher 205 in FIG. Polar code encoder 512 is basically the same as polar code encoder 204 in FIG.

[00163] The polar code encoder 512 may be configured to: determine that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits;

map M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and map D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, wherein M < K, and all of D, M, and K are positive integers; and

perform polar encoding on the mapped bits to obtain encoded encoding bits.

[00164] According to this embodiment of the present invention, when broadcast signaling is sent, it is first determined that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits; M predictable information bits are mapped to M low reliability information bits in K polar code information bits, respectively, D cyclic redundancy check (CRC) bits are mapped to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, with M < K, and all of D, M, and K are positive integers; and polar coding is performed on the mapped bits to obtain coded coding bits, so that the transmission reliability of the broadcast signaling can be improved.

[00165] Optionally, in one embodiment, the M low reliability information bits includes M information bits whose reliability is less than a predetermined threshold, or the M low reliability information bits includes M lowest reliability information bits in the K information bits.

[00166] Optionally, in another embodiment, the M predictable information bits include one or more of the following bit combinations: M ₁ bits of the first type, M ₂ bits of the second type, or M ₃ bits of the third type, where the first type bit is reserved bit, the second type bit includes an information bit whose value remains unchanged, the third type bit is a predictable information bit whose value is the content of the time sequence information and changes, all of M ₁ , M ₂ and M ₃ are positive integers, M ₁ <= M, M ₂ <= M and M ₃ <= M.

[00167] Optionally, in another embodiment, when the M predictable information bits include M ₁ bits of the first type and M ₂ bits of the second type, or include M ₁ reserved bits and M ₃ bits of the second type, M ₁ bits of the first type are mapped to M ₁ low reliability information bits in M information bits.

[00168] Optionally, in another embodiment, M ₂ bits of the second type are mapped to M ₂ low reliability information bits in the remaining information bits of the M information bits; or M ₁ bits of the first type are mapped to M ₁ low reliability information bits in M information bits; and M ₃ bits of the second type are mapped to M ₃ low reliability information bits in the remaining information bits of the M information bits.

[00169] Optionally, in another embodiment, the polar code encoder 512 is specifically configured to: when the M predictable information bits include M ₁ bits of the first type, M ₂ bits of the second type, and M ₃ bits of the second type, display M ₁ bits the first type in M ₁ low reliability information bits in M information bits.

[00170] Optionally, in another embodiment, the polar code encoder 512 is specifically configured to: map M ₂ bits of the second type to M ₂ low reliability information bits in (MM ₁ ) information bits; and

map M ₃ bits of the third type into M ₃ low reliability information bits (MM ₁ -M ₂ ).

[00171] Optionally, in another embodiment, the payload further includes J unpredictable information bits, and the polar code encoder 512 is specifically further configured to map the J unpredictable information bits to J low reliability information bits in (K-M-D) information bits, moreover, J < K, and J is a positive integer.

[00172] Optionally, in another embodiment, the polar code encoder 512 sorts the K information bits based on the reliability values of the K information bits. Then, the polar code encoder 512 maps the M reserved bits, respectively, to the M low reliability information bits in the K information bits based on the sort result.

[00173] Optionally, in another embodiment, the reliability value of the information bit is determined based on the bit capacity, the Bhattacharya parameter of the Bhattacharya distance, or the error probability.

[00174] FIG. 6 is a schematic diagram of a system that helps to perform the above polar coding method in a wireless communication environment. System 600 includes a base station 602 (eg, an access point or NodeB or eNB). Base station 602 includes a receiver 610 that receives a signal from one or more access terminals 604 using a plurality of receive antennas 606 and a transmitter 624 that transmits a signal to one or more access terminals 604 using a transmit antenna 608. Receiver 610 can receive information from the receive antenna 606 and may be operatively coupled to a demodulator 612 that demodulates the received information. A processor 614, similar to the processor described in FIG. 7, is configured to analyze the demodulated symbol. Processor 614 is coupled to memory 616. Memory 616 is configured to store data to be sent to access terminal 604 (or various base stations (not shown)), or data to be received from access terminal 604 (or various base stations). (not shown)) and/or any other relevant information related to performing the various activities and functions described in this document. The processor 614 may be further coupled to a polar code encoder 618 and a rate matcher 620 .

[00175] The polar code encoder 618 may be configured to: determine that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits;

map M predictable information bits to M low reliability information bits to K polar code information bits, respectively, and map D cyclic redundancy check (CRC) bits to D high reliability information bits in the remaining information bits of the K information bits to obtain mapped bits, wherein M < K, and all of D, M, and K are positive integers; and

perform polar encoding on the mapped bits to obtain encoded encoding bits.

[00176] In addition, in system 600, modulator 622 may multiplex a frame for transmission using transmit antenna 608 by transmitter 624 to access terminal 604. It is understood that polar code encoder 618, rate matcher 620, and/or modulator 622 may be part of processor 614 or part of multiple processors (not shown), although they are shown separately from processor 614.

[00177] It should be understood that these embodiments described herein may be implemented by hardware, software, firmware, middleware, microcode, or combinations thereof. For hardware implementation, the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processor (DSP), Digital Signal Processing Device (DSP Device, DSPD), Programmable Logic Device (Programmable Logic Device, PLD), field-programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, other electronic device capable of performing the function in this application, or a combination thereof.

[00178] When the embodiments are implemented with software, firmware, middleware or microcode, program code or code segment, the software, firmware, middleware or microcode, program code or code segment may be stored on a computer-readable medium, such as a storage component. A code segment can represent any combination of a process, function, subroutine, program, procedure, subroutine, module, program component, class, instruction, data structure, or program statement. A code segment may be associated with another code segment or hardware circuit by transmitting and/or receiving information, data, independent variable, parameter, or memory contents. Information, independent variable, parameter, data, etc. may be transferred, forwarded, or sent in any suitable manner, including memory sharing, message passing, token transfer, and network transfer.

[00179] For software implementation, the technologies described herein may be implemented using modules (eg, processes or functions) that perform the functions described herein. The program code may be stored in a memory unit and executed using a processor. The memory unit may be implemented within the processor or external to the processor. When the memory module is implemented outside the processor, the memory module may be communicatively coupled to the processor using various measures known in the art.

[00180] It should be understood that all of the above device embodiments can be implemented in accordance with the steps in the method embodiments. Details are not described here again.

[00181] In embodiments of the present invention, the sequence numbers of the above processes do not indicate the sequence of execution. The execution sequences of the processes should be determined according to the functions and internal logic of the processes and should not be considered as any limitation with respect to the processes for implementing the embodiments of the present invention.

[00182] One skilled in the art may be aware that, in combination with the examples described in the embodiments disclosed in this specification, the blocks and steps of an algorithm may be implemented using electronic hardware, computer software, or a combination of both. In order to clearly describe the interchangeability between hardware and software, the foregoing generally describes the compositions and steps of each example according to function. Whether the functions are performed by hardware or software depends on the particular applications and design constraints of the technical solutions. A person skilled in the art can use various methods to implement the described functions for each particular application, but such an implementation should not be considered to be outside the scope of the present invention.

[00183] One skilled in the art can clearly understand that for the purposes of convenient and concise description of the detailed working process of the aforementioned system, apparatus, and unit, reference may be made to the corresponding process in the aforementioned method embodiments, and the details are not described again here.

[00184] In several embodiments provided herein, it should be understood that the disclosed system, apparatus, and method may be implemented in other ways. For example, the device embodiment described is merely an example. For example, the division into blocks is just a logical division of functions and may be another division in the actual implementation. For example, many blocks or components may be combined or integrated into another system, or some features may be ignored or not performed. In addition, the interconnections or direct connections or communication connections depicted or discussed may be implemented through some interfaces, indirect connections or communication connections between devices or units, or electrical connections, mechanical connections or connections in other forms.

[00185] Blocks described as separate parts may or may not be physically separate, and parts depicted as blocks may or may not be physical blocks, i.e., may be located in the same location or may be distributed over multiple network blocks. . Some or all of the blocks may be selected according to actual needs in order to achieve the objectives of the solutions in the embodiments of the present invention.

[00186] In addition, the functional blocks in the embodiments of the present invention may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units are integrated into one unit. An integrated block may be implemented in the form of hardware or may be implemented in the form of a software function block.

[00187] When an integrated block is implemented in the form of a software functional block and sold or used as a standalone product, the integrated block may be stored on a computer-readable storage medium. Based on such an understanding, the technical solutions according to the present invention essentially or part contributing to the prior art, or all or part of the technical solutions can be implemented in the form of a software product. The software product is stored on a storage medium and includes several instructions for causing a computing device (which may be a personal computer, a server, a network device, or the like) to perform all or parts of the described method steps in embodiments of the present invention. The above storage medium includes any medium that can store program code, such as a USB flash drive, removable hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM), magnetic disc or optical disc.

[00188] The above descriptions are only specific implementations of the present invention, but are not intended to limit the scope of protection of the present invention. Any modification or replacement readily determined by one of ordinary skill in the art within the technical scope disclosed in the present invention shall fall within the scope of the present invention. Therefore, the scope of protection of the present invention should be consistent with the scope of protection of the claims.

[00189] Based on FIG. 2, in an embodiment, the polar code encoder 204 is configured to: determine that the broadcast signaling payload payload includes D cyclic redundancy check (CRC) bits and M predictable information bits; map the M predictable information bits respectively to the M low reliability subchannels in the subchannels corresponding to the K information bits of the polar code, and map the D cyclic redundancy check (CRC) bits to the D high reliability subchannels in the subchannels corresponding to the remaining information bits of the K information bits to obtain mapped bits, where M is less than or equal to (K-D) and all of D, M, and K are positive integers; and perform polar encoding on the mapped bits to obtain encoded bits.

[00190] In addition, the transmitter 206 may subsequently channel the bits that have been processed by the rate matcher 205 . For example, transmitter 206 may send associated data to another wireless communications device (not shown).

[00191] The above M low reliability subchannels in the subchannels corresponding to the K polar code information bits are consistent with the description of the M low reliability information bits in the K polar code information bits in the above embodiments. In order to more clearly describe the relationship between the information bits and the subchannels corresponding to the information bits, the M low reliability information bits in the K information bits of the polar code in the above embodiments may be further described as follows: The K subchannels are selected from the polar code subchannels, the K information bits are mapped to the selected K subchannels, the M low reliability subchannels are then selected from the K subchannels, and the M information bits are mapped to the selected M subchannels.

[00192] The specific process in which the above polar code encoder performs processing is described in detail below.

[00193] In the previous embodiments, the PBCH payload is classified into four types depending on whether the content (content) of the access service is variable. Here, in addition to the above four types of bits, a fifth type of bits is added depending on various scenarios in which the type of bits is changed. The fifth type of bits includes bits of different types of bits in different scenarios. For example, one or more bits that are classified as third type bits carry a certain content type in the first scenario and may be classified as second type bits based on the content that is carried in the first scenario. These bits carry content of a different type in the second scenario and can be classified as third type bits based on the content that is carried in the second scenario. In other words, these bits, which carry different content and belong to different types in different scenarios, are classified as fifth type bits.

[00194] The fifth type bit cases are detailed below based on various scenarios:

[00195] (1) Some bits carry different content and belong to different types in different scenarios. A particular bit type carries one content type in a first scenario and another content type in a second scenario: Some bits carry a particular content type in a first scenario, and one or more bits carry a different content type in a second scenario. In other words, these bits, which carry different content in different scenarios and belong to different types, can be classified as fifth type bits.

[00196] For example, among the bits of the third type in the low frequency application scenario, some bits (eg, sync block index (SSBI)) that represent the time sequence may indicate a configuration that changes frequently. In this case, these bits can be classified as bits of the fourth type. Those bits that represent the time sequence are also used to represent the time sequence in the high frequency scenario. When these bits are used to represent a time sequence, these bits are classified as third type bits. That is, one or more bits are classified as third type bits in the high frequency scenario and may further be classified as fourth type bits in the low frequency scenario. In other words, these bits, which carry different content in different scenarios and belong to different types, are classified as fifth type bits.

[00197] (2) Some bits carry the same content in different scenarios. However, these bits, which carry the same content, are of different types in different scenarios.

[00198] One or more bits are first type bits in some scenarios and are second type bits or fourth type bits in other application scenarios. However, such bits carry the same content. For example, some system configuration information may belong to the fourth type while operating in the same cell. At the time of handover of a cell, such configuration information is notified in advance in a different manner. Therefore, the configuration information is known before decoding and can be classified as first type bits.

[00199] In another example, the pilot density control signaling belongs to the fourth bit type in the wideband application scenario and belongs to the second bit type in the narrowband scenario. Such one or more bits are classified as fifth type bits.

[00200] (3) There is another special case for such bits that carry different content in different scenarios: One or more bits carry the same type of content in the first scenario, but these bits do not carry content in the second scenario. In other words, in different scenarios, a bit may or may not carry content.

[00201] For example, among the bits of the third type, the bits used to indicate the synchronization block index (SSBI) in the high frequency scenario carry no information in the low frequency scenario, and one or more bits may be classified as fifth type bits.

[00202] In another example, some bandwidth configuration indication signaling belongs to the fourth bit type and exists only in the high frequency scenario. The bits used to convey such signaling carry no information in the low frequency scenario. In this case, one or more bits may be classified as fifth type bits.

[00203] The following describes in further detail how bits of the fifth type are mapped to the respective subchannels of the polar code.

[00204] Generally, the M predictable information bits include M ₅ bits of the fifth type, and the mapping of the M ₅ bits of the fifth type to the M low reliability information bits in the M information bits specifically includes:

mapping M ₅ bits of the fifth type to one or more subchannel associations below, wherein the one or more subchannel associations includes:

M ₅ subchannels in subchannels corresponding to (M ₁ +M ₅ ) bits of the first type, M ₅ subchannels in subchannels corresponding to (M ₂ +M ₅ ) bits of the second type, M ₅ subchannels in subchannels corresponding to (M ₃ +M ₅ ) bits of the second type, M ₅ subchannels in subchannels corresponding to (M ₄ +M ₅ ) bits of the fourth type, or M ₅ subchannels between M ₂ subchannels corresponding to M ₂ bits of the second type and M ₃ subchannels corresponding to M ₃ bits of the third type.

[00205] Generally, depending on various application scenarios, the fifth type bit is mapped based on the content carried by the fifth type bit. If the content carried in one or more bits belongs to one of the first type to the fourth type bits, the mapping is performed based on the bit type bit mapping method. Further processing is carried out according to the actual requirement, unless there is a special setting such as a system setting, such as a setting based on the priorities of different scenarios.

[00206] The following describes the aforementioned mapping process further based on the various ways in which bits of the fifth type are classified:

[00207] (1) For the fifth type bit, if the fifth type bit refers to the following case: carrying one content type in the first scenario and carrying another content type in the second scenario, this bit carries one kind of content in the first scenario, and this bit carries different kind of content in the second scenario. A bit carries different content and belongs to different types in different scenarios.

[00208] A fifth type bit may be displayed based on the importance or priority of using one or more bits in an application scenario.

[00209] For example, bits of the third type are one or more bits used to indicate, for example, SSBI in a high frequency scenario. That is, in the high frequency scenario, one or more bits are classified as third type bits. In a low frequency scenario, one or more bits may indicate a configuration that changes frequently. That is, one or more bits can be classified as fourth type bits in the low frequency scenario. Typically, one or more bits are classified as Type 5 bits due to the above characteristics. When such bits are mapped to polar code subchannels: In the high frequency scenario, a bit carries the content of a third type bit, and one or more bits are mapped to subchannel positions corresponding to the third type bits; or, in the low frequency scenario, one or more bits are mapped to subchannel positions corresponding to bits of the fourth type.

[00210] In addition, if these bits are idle in the low band or the values of these bits can be obtained directly, then these one or more bits can be classified as first type bits. In the low frequency scenario, such bits are mapped to subchannel positions corresponding to the first type bits. There is another consideration. If the system and scenario do not support such scenario-based adjustment, then the priorities of the various scenarios should be taken into account at the initial stage of system design. For example, if the low frequency scenario has a higher usage density, then one or more bits in the entire system are processed in a first type bit or a fourth type bit mapping manner. On the contrary, if the high frequency scenario is more important, one or more bits are processed by the third type bit mapping method.

[00211] (2) Some bits carry the same content in different scenarios, but bits that carry the same content are of different types in different scenarios. When such bits are mapped to polar code subchannels, system handoff efficiency may be preferably taken into account during system design, and these bits are then mapped to low reliability positions in polar code subchannels, for example, before a subchannel corresponding to a first type bit, or between a subchannel corresponding to bit of the third type, and a subchannel corresponding to the bit of the fourth type. If the system design does not focus on the handover performance of the cell, the corresponding mapping processing is performed based on the bits of the originally classified bit type.

[00212] In another example, the HFI is re-notified to the terminal in a different manner in a low frequency scenario. In this case, the HFI information also has a bit characteristic of the first type. To map to the polar code subchannel, the HFI information may be mapped to a position before the subchannel corresponding to the first type bit, or mapped to another unreliable position.

[00213] In another example, the pilot density control signaling belongs to the fourth bit type in the wideband application scenario and belongs to the second bit type in the narrowband scenario. The broadband application scenario is used more frequently and has higher load priorities and the like. in system. Therefore, the broadband system design requirements are preferably satisfied to display one or more bits by the fourth type bit mapping method. On the contrary, if the performance of the narrowband device is considered to a greater extent, one or more bits are displayed by the second type of bit mapping method.

[00214] (3) There is another special case for such bits that carry different content in different scenarios: One or more bits carry the same type of content in the first scenario, but those bits do not carry content in the second scenario. In other words, in various scenarios, a bit may or may not carry content.

[00215] The method for mapping one or more bits is specifically as follows: For example, one or more bits used to indicate SSBI in a high frequency scenario does not carry information in a low frequency scenario. In this case, one or more bits may be processed in a first type bit mapping method, i. e. one or more bits are mapped to subchannels corresponding to bits of the first type; or are mapped to the subchannel position after the subchannel corresponding to the first type bit but before the subchannel position corresponding to the third type bit.

[00216] In another example, some bandwidth configuration indication signaling belongs to the fourth bit type and exists only in the high frequency scenario. One or more of the bits used to carry such signaling does not contain information in the low frequency scenario. If high frequency performance is considered to be preferable, then one or more bits may be processed in a first type bit mapping method, or one or more bits may be mapped at a position after the subchannel corresponding to the first type bit but before the subchannel position corresponding to the fourth type bit.

[00217] In general, based on the above classification of the bit sets and the order from the first type to the fifth type, the contents of the PBCH payload are mapped to the polar code information bit set in order of increasing reliability of the subchannels in the information bit set, or mapped to the polar code information bit set in accordance with natural sequence numbers, from beginning to end, of subchannels in the set of information bits. Typically, this application is described based on sorting reliability. The specific display method varies according to the different classified types.

[00218] In addition, for the above mapping methods, since a fifth type of bits is added, when selecting subchannels for displaying five types of bits, it is necessary to consider the subchannel corresponding to the fifth type bit. For example, a mapping based on the above mapping order of M ₅ bits of the fifth type to subchannels corresponding to M ₁ bits of the first type should be understood as: mapping of M ₅ bits of the fifth type to M ₅ subchannels in the subchannels corresponding to (M ₁ +M ₅ ) bits of the first type. Other display modes are understood in a similar way.

[00219] In addition, optionally, one or more bits that are classified as a particular type can still be classified in that type. For example, based on the application scenario of one or more bits, a bit classified as a bit of the fifth type is classified in display and displayed accordingly. This design focuses on system compatibility and consistency, and the characteristics of different scenarios are comprehensively considered with minimal differences.

[00220] For example, one or more bits that are classified as fifth type bits and that are used to indicate SSBI. These one or more bits belong to the third type of bits in the high frequency scenario. In the low frequency scenario, although their use must be specified, one or more bits still belong to the third bit type. For the above high frequency and low frequency application scenarios, one or more bits are further classified and mapped accordingly: If one or more idle bits are not to be used in the future in the low frequency scenario, then those one or more bits are mapped to relatively low reliability positions in the subchannels , corresponding to bits of the third type; or if one or more of the unoccupied bits are for possible future use, then those one or more bits are mapped to a position with relatively high reliability in the channels corresponding to the third type bits.

[00221] Furthermore, in one embodiment of the present application, the Distributed CRC (D-CRC) interleaving process shown in FIG. 7.

[00222] The D-CRC itself needs to be interleaved once, and the mapping process further needs to be interleaved once. Thus, the whole process should be realized by combining two times of interleaving, so that a bit of a particular kind of content after two times of interleaving is mapped to a channel with a particular reliability. A specific flowchart is shown in FIG. 7.

_{[ 00223 ] a 0} , a ₁ , . ₀ , b ₁ , ..., b _k , c ₀ , c ₁ , ..., c _d-1 , and then interleaving by distributed CRC (Distributed-CRC, D-CRC) is performed once to obtain d ₀ , d ₁ , ... , _dk+d-1 .

[00224] D-CRC interleaving has been comprehensively discussed. In order to achieve the possible mapping effect in the table in Fig. 3b, the order of the bits of the various MIB types to be placed in specific trusted positions can be pre-mapped, so that the bits that have undergone CRC connection and D-CRC interleaving, and which are mapped to the subchannels in the polar code correspond to the possible display effect in the table in Fig. 3b. Likewise, one pre-interleaver may be used to perform pre-interleaving on MIB information for which the bit order must be adjusted to achieve a similar effect.

[00225] The following describes in detail the mapping of the polar subchannels of the polar code using the above mapping method in the presence of D-CRC.

[00226] Embodiment 1: The code length of the polar code is 512, and the broadcast signaling payload payload definition includes: cyclic redundancy check (CRC) bits and predictive information bits. The number K of information bits is 56. For cyclic redundancy check (CRC) bits, D-CRC is used as an example, and D is 24 bits. The number M of predictable information bits is less than or equal to (56-24) = 32.

[00227] First, in ascending order of subchannel reliability, the sequence numbers in the set of subchannel sequence numbers corresponding to the information bits start from 0, for a total of 56 bits. The specific set looks like this:

(441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 431 489 486 476 439 490 463 381 497 492 443 382 498 445 471 500 446 487 504 255 477 491 478 383 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493050 5050 5050 5050 508 495 503 507 509 510 511).

[00228] The D-CRC interleaver for K=56 and D=24 is as follows:

(0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55).

[00229] Based on the D-CRC interleaver, 24 sub-channels are selected from the sub-channels corresponding to the above information bits to carry the 24 D-CRC bits. The 24 specific D-CRC bits are mapped to the 24 subchannels below:

(446 478 487 490 491 492 493 494 495 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511).

[00230] Next, for the sequence numbers of the remaining polar subchannels, a total of 32 subchannels are used to carry M predictable information bits, where M is less than or equal to 32:

(441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 431 489 486 476 439 463 381 443 382 445 471 475 255 477 383 447 479).

[00231] A specific way to display M predictable information bits is as follows:

[00232] (1) When the M predictable information bits include fifth type bits and third type bits, where the fifth type bits include SSBI, the third type bits include HFI and SFN, and the fourth type bits include RMSI config and/or reserved bits to be used.

[00233] (a) Considering that Type 5 SSBI bits are known bits in the low band and should not be used, the SSBI bits are classified as Type 1 low band bits and mapped to the three least reliable sub-channels in the above set of 32 sub-channels , and the display looks like this:

SSBI: (247 441 469)

[00234] (b) The third type bits HFI and SFN are mapped to the three lowest reliability subchannels in (32-3), namely 29 subchannels. The specific mapping looks like this:

HFI: 367

SFN: (253 375 444 254 415 470 473 474 483 485)

[00235] Referring to the embodiment shown in FIG. 7, the bit sequence d ₀ , d ₁ , ..., d _k+d-1 is mapped to polar code subchannels by the mapping method described above.

[00236] In addition, optionally, de-derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ ... and _k in FIG. 7 is subjected to the first interleaving and mapping. The details are as follows:

SSBI: (24 6 0)

HFI: 7

SFN: (2 10 30 8 17 18 23 16 20 3)

[00237] (2) Given that Type 5 SSBI bits will be used in the future in the low band, SSBI bits are classified as Type 4 bits. During mapping, the third type bit mapping is considered first. The third type bits HFI and SFN are mapped to the 11 least reliable sub-channels in the above set of 32 sub-channels (HFI and SFN are not further classified in this embodiment). Next, the 21 remaining subchannels are considered and three subchannels are selected from among them for SSBI transfer. The specific relationship of displaying subchannels is as follows:

HFI: (441)

SFN: (247 367 469 253 375 415 444 470 483 485)

SFN: (254 473 474)

[00238] Further, optionally, reverse derivation is performed based on the above relationship of polar subchannel mapping and D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence: b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

HFI: 24

SFN: (6 0 7 2 10 30 8 17 18 23)

SSBI: (16 20 3)

[00239] (3) When the M predictable information bits include second type bits such as RMSI config and third type bits such as HFI, SFN and SSBI:

[00240] First, bits of the second type are considered. Bits of the second type are mapped to eight low reliability subchannels. Then bits of the third type are considered. Bits of the third type are mapped to 14 low reliability subchannels in (32-8), namely 24 subchannels.

[00241] The final display of the subchannels is as follows:

RMSI Config: (247 253 367 375 441 444 469 470)

HFI: 483

SFN: (415 473 485 254 379 431 474 476 486 489)

SSBI: (381 439 463)

[00242] Further, optionally, reverse derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output interleaved MIB sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

RMSI Config: (24 6 0 7 2 10 30 8)

HFI: 17

SFN: (18 23 16 20 3 11 19 29 28 25)

SFN: SSBI: (21 4 12)

[00243] (4) When the M predictable information bits include first type bits such as reserved bits that will not be used and third type bits such as SSBI, HFI and SFN:

[00244] First, bits of the first type are mapped to the three subchannels of the lowest reliability. Then, bits of the third type are mapped to the 14 lowest reliability subchannels in (32-3), namely 29 subchannels. The final display of the subchannels is as follows:

Reserved bits: (247 441 469)

SSBI: (253 367 375)

HFI: 444

SFN: (415 470 483 254 379 431 473 474 485 489)

[00245] Further, optionally, reverse derivation is performed based on the above relationship of polar subchannel mapping and D-CRC interleaving pattern to obtain the corresponding output interleaved MIB sequence: b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , ... and _k in FIG. 7 is subjected to first interleaving and mapping. The details are as follows: After the reserved bits 24 6 0 pass the first interleaving, the reserved bits are located at the positions of the output MIB interleaved sequence. For example, the reserved bits are mapped to bit 24, bit 6, and bit 0 of the interleaved MIB sequence, that is, the reserved bits are placed in b ₀ , b ₆ and b ₂₄ in the MIB sequence:

SSBI: (7 2 10)

HFI: 30

SFN: (8 17 18 23 16 20 3 11 19 29)

[00246] Embodiment 2: The code length of the polar code is 512, and the broadcast signaling payload payload definition includes: cyclic redundancy check (CRC) bits and predictable information bits. The payload further includes one or more bits at preset positions in the polar code subchannels. The number K of information bits is 56. For cyclic redundancy check (CRC) bits, D-CRC is used here as an example and D is 24 bits. The number of bits at preset positions in the polar code subchannels is assumed to be X. The number M of predictable information bits is less than or equal to (56-24-X). First, in ascending order of sub-channel reliability, the sequence numbers in the set of sub-channel sequence numbers corresponding to the information bits, starting from 0, for a total of 56 bits. The specific set is as follows:

(441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 431 489 486 476 439 490 463 381 497 492 443 382 498 445 471 500 446 487 504 255 477 491 478 383 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493050 5050 5050 508 495 503 507 509 510 511).

[00247] The D-CRC interleaver for K=56 and D=24 is as follows:

(0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55).

[00248] Based on the D-CRC interleaver, 24 sub-channels are selected from the sub-channels corresponding to the above information bits to carry 24 D-CRC bits. The 24 specific D-CRC bits are mapped to the 24 subchannels below:

(446 478 487 490 491 492 493 494 495 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511).

[00249] X subchannels are then selected from the remaining polar subchannel sequence numbers, 32 subchannels in total, to carry bits at preset positions in the polar code subchannels. For example:

[00250] (1) Three SSBI bits are used to carry bits at preset positions in polar code subchannels. In this case, the three SSBI bits are placed in leading positions, namely (247, 253, 254), in the natural subchannel sequence of the information bits of the polar code. The remaining (32-3), namely 29, subchannels are mapped to M predictable information bits in ways of mapping first type bits to fourth type bits.

[00251] The final display of the subchannel is as follows:

SSBI: (247 253 254)

HFI: 441

SFN: (367 375 469 415 444 470 473 474 483 485)

[00252] In addition, optionally, de-derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequences a ₀ , a ₁ ... and _k in FIG. 7 is subjected to the first interleaving and mapping. The details are as follows:

SSBI: (0 2 3)

HFI: 24

SFN: (6 7 10 30 8 17 18 23 16 20)

[00253] (2) One bit of the "cell barring flag" and three SSBI bits are used to carry bits at preset positions in the polar code subchannels. In this case, the "Cell Inhibit Flag" bit and the three SSBI bits are placed in leading positions, namely (247 253 254 255), in the natural subchannel sequence of the polar code information bits. For the mapping method of the remaining subchannels that carry M predictable information bits, the mapping is performed by the mapping methods of the first type bits to the fourth type bits.

[00254] The final display of the subchannel is as follows:

Cell Inhibit: 247

SSBI: (253 254 255)

HFI: 441

SFN: (367 375 469 415 444 470 473 474 483 485)

[00255] In addition, optionally, de-derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ ... and _k in FIG. 7 is subjected to the first interleaving and mapping. The details are as follows:

Cell Deny: 0

SSBI: (2 3 5)

HFI: 24

SFN: (6 7 10 30 8 17 18 23 16 20)

[00256] (3) One bit of the Cell Inhibit Flag and three SSBI bits are used to carry bits at preset positions in the polar code subchannels. In this case, the three SSBI bits are placed in leading positions, namely (247, 253, 254), in the natural subchannel sequence of the information bits of the polar code. The "cell prohibition flag" is placed in a relatively forward position. Since the value of the "Cell Inhibit Flag" may vary, placing the "Cell Inhibit Flag" in a position with relatively high reliability contributes to the overall performance. For example, "Cell Inhibit Flag" is placed at position 255. For the mapping method of the remaining sub-channels that carry M predictable information bits, the mapping is performed by the mapping methods of the first type bits to the fourth type bits. Details are not repeated.

[00257] In the above Embodiment 1 and Embodiment 2, detailed descriptions are made using an example in which the number of K information bits is 56. The following is further detailed using an example in which the number of K information bits is 64.

[00258] Embodiment 3: The polar code code length of the polar code is 512, and the broadcast signaling payload payload definition includes: cyclic redundancy check (CRC) bits and predictable information bits. The number K of information bits is 64. For cyclic redundancy check (CRC) bits, D-CRC is used here as an example, and D is 24 bits. The number M of predictable information bits is less than or equal to (64-24)=40.

[00259] First, in ascending order of subchannel reliability, the sequence numbers in the set of subchannel sequence numbers corresponding to the information bits start from 0, for a total of 64 bits. The specific set looks like this:

(461 496 351 467 438 251 462 442 441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 431 489 486 476 439 490 463 381 497 492 443 382 498 445 471 500 446 475 487 504 255 477 491 478 383 493 499 502 494 501 447 505 506 479 508 495 503 507 509 510 511).

[00260] The D-CRC interleaver for K=64 and D=24 is as follows:

(1 4 6 8 10 11 13 15 18 19 20 22 23 26 27 29 32 34 38 39 40 2 5 7 9 12 14 16 21 24 28 30 33 35 41 0 3 17 25 31 36 42 47 43 4 8 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63)

[00261] Based on the D-CRC interleaver, 24 sub-channels are selected from the sub-channels corresponding to the above information bits to carry 24 D-CRC bits. The 24 specific D-CRC bits are mapped to the 24 subchannels below:

(445 477 489 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511).

[00262] Next, for the remaining polar subchannel sequence numbers, there are a total of 40 subchannels used to carry M predictable information bits, where M is less than or equal to 40:

(461 351 467 438 251 462 442 441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 486 476 439 490 463 381 443 382 471 475 487 255 478 383 447 479).

[00263] (1) When the M predictable information bits include fifth type bits and third type bits, where the fifth type bits include SSBI, the third type bits include HFI and SFN, and the fourth type bits include RMSI config and/ or the reserved ones to be used:

[00264] (a) Given that Type 5 SSBI bits are known bits in the low band and should not be used, the SSBI bits are classified as Type 1 bits in the low band and mapped to three low reliability subchannels in the above set of 40 subchannels, and mapping is this:

SSBI: (351 461 467)

[00265] (b) The third type bits HFI and SFN are mapped to three low reliability subchannels in (40-3), namely 37 subchannels. The specific display is:

HFI: 438

SFN: (251 442 462 247 253 367 375 441 444 469)

[00266] With reference to the embodiment shown in FIG. 7, the bit sequence d ₀ , d ₁ , ..., d _k+d-1 is mapped to polar code subchannels in the above mapping method.

[00267] In addition, optionally, de-derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

SSBI: (7 11 14)

HFI: 27

SFN: (4 9 34 32 16 1 13 6 15 39)

[00268] (2) Considering that type 5 SSBI bits will be used in the low band in the future, SSBI bits are classified as type 4 bits. When mapping, the third type bit mapping is considered first. Bits of the third type HFI and SFN are mapped to the 11 lowest reliability subchannels in the above set of 32 subchannels (HFI and SFN are not further classified in this embodiment). Next, the remaining subchannels are considered and three subchannels are selected from among them for SSBI transport. The specific relationship of subchannel display is as follows:

HFI: 461

SFN: (351 438 467 247 251 367 441 442 462 469)

SSBI: (253 375 444)

[00269] Further, optionally, reverse derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

HFI: 7

SFN: (11 14 27 4 9 34 32 16 1 13)

SSBI: (6 15 39)

[00270] (3) When M predictable information bits include second type bits such as RMSI config and third type bits such as HFI, SFN and SSBI:

[00271] Bits of the second type are considered first. Bits of the second type are mapped to the eight subchannels of the lowest reliability. Then bits of the third type are considered. Bits of the third type are mapped to 14 low reliability subchannels in the remaining subchannels.

RMSI config: in the front position (where the RMSI configuration belongs to the second type):

RMSI configurations, HFI, SFN, SSBI, …

[00272] The final display of the subchannels is as follows:

RMSI Config: (251 351 438 441 442 461 462 467)

HFI: 469

SFN: (247 253 367 375 415 444 470 473 483 485)

SSBI: (254 379 474)

[00273] Further, optionally, reverse derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output interleaved MIB sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

RMSI Config: (7 11 14 27 4 9 34 32)

HFI: 16

SFN1: (1 13 6 15 39 21 17 23 25 28)

SSBI: (30 8 18)

[00274] (4) When M predictable information bits include first type bits such as reserved bits that will not be used and third type bits such as SSBI, HFI and SFN:

[00275] First, bits of the first type are mapped to three low reliability subchannels in the above 40 subchannels. The third type bits are then mapped to the 14 lowest reliability subchannels in the remaining subchannels. The final display of the subchannel is as follows:

[00276] The final subchannel mapping is as follows:

Reserved bits: (351 461 467)

SSBI: (251 438 462)

HFI: 442

SFN: (247 441 469 253 367 375 415 444 470 483)

[00277] Further, optionally, reverse derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output interleaved MIB sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, and _k in Fig. 7 is first interleaved and displayed. The details are as follows:

Reserved bits: (7 11 14)

SSBI: (27 4 9)

HFI: 34

SFN: (32 16 1 13 6 15 39 21 17 23)

[00278] Embodiment 4: The code length of the polar code is 512, and the broadcast signaling payload payload definition includes: cyclic redundancy check (CRC) bits, predictable information bits, and bits at preset positions in polar code subchannels. The number K of information bits is 64. For cyclic redundancy check (CRC) bits, D-CRC is used here as an example and D is 24 bits. The number of bits at preset positions in the polar code subchannels is assumed to be X. The number M of predictable information bits is less than or equal to (64-24-X).

[00279] First, in ascending order of subchannel reliability, the sequence numbers in the subchannel sequence number set corresponding to the information bits, starting from 0, for a total of 64 bits. The specific set is as follows:

(441 469 247 367 253 375 444 470 483 415 485 473 474 254 379 431 489 486 476 439 490 463 381 497 492 443 382 498 445 471 500 446 487 504 255 477 491 478 383 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493 493050 5050 5050 508 495 503 507 509 510 511).

[00280] The D-CRC interleaver for K=64 and D=24 is as follows:

(1 4 6 8 10 11 13 15 18 19 20 22 23 26 27 29 32 34 38 39 40 2 5 7 9 12 14 16 21 24 28 30 33 35 41 0 3 17 25 31 36 42 47 43 4 8 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63).

[00281] Based on the D-CRC interleaver, 24 sub-channels are selected from the sub-channels corresponding to the above information bits to carry 24 D-CRC bits. The 24 specific D-CRC bits are mapped to the 24 subchannels below:

(446 478 487 490 491 492 493 494 495 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511).

[00282] Next, X subchannels are selected from the remaining polar subchannel sequence numbers, for a total of 40 subchannels, to carry bits at preset positions in the polar code subchannels. For example:

[00283] (1) Three SSBI bits are used to carry bits at preset positions in polar code subchannels. In this case, the three SSBI bits are placed in leading positions, namely (247 251 253), in the natural subchannel sequence of the information bits of the polar code. The remaining subchannels are mapped to M predictable information bits according to the mapping methods of the first type bits to the fourth type bits.

[00284] The final display of the subchannel is as follows:

SSBI: (247 251 253)

HFI: 461

SFN: (351 438 467 367 375 441 442 444 462 469)

[00285] Further, optionally, reverse derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output interleaved MIB sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, and _k in Fig. 7 is first interleaved and displayed. The details are as follows:

SSBI: (1 4 6)

HFI: 7

SFN: (11 14 27 9 34 32 16 13 15 39)

[00286] (2) One Cell Inhibit Flag bit and three SSBI bits are used to carry bits at preset positions in polar code subchannels. In this case, the "Cell Inhibit Flag" bit and the three SSBI bits are placed in leading positions, namely (247 253 254 255), in the natural subchannel sequence of the polar code information bits. For the mapping method of the remaining subchannels that carry M predictable information bits, the mapping is performed in the mapping methods of the first type bits to the fourth type bits. The final display of the subchannels is as follows:

Cell Inhibit: 247

SSBI: (251 253 254)

HFI: 461

SFN: (351 438 467 367 375 441 442 444 462 469)

[00287] In addition, optionally, de-derivation is performed based on the above polar subchannel mapping relationship and the D-CRC interleaving pattern to obtain the corresponding output MIB interleaved sequence b ₀ , b ₁ , ..., b _k after the MIB sequence a ₀ , a ₁ , …, a _k in Fig. 7 is first interleaved and displayed. The details are as follows:

Cell barring: 1

SSBI: (4 6 8)

HFI: 7

SFN1: (11 14 27 9 34 32 16 13 15 39)

(3) One Cell Inhibit Flag bit and three SSBI bits are used to carry bits at preset positions in polar code subchannels. In this case, the three SSBI bits are placed in leading positions, namely (247 251 253), in the natural subchannel sequence of the information bits of the polar code. The "cell prohibition flag" is located in a relatively forward position. Since the value of the "Cell Inhibit Flag" may vary, placing the "Cell Inhibit Flag" in a position with relatively high reliability contributes to the overall performance. For example, "Cell Inhibit Flag" is placed at position 255. For the mapping method of the remaining sub-channels that carry M predictable information bits, the mapping is performed in the mapping methods of the first type bits to the fourth type bits. Details are not repeated.

Claims (72)

1. A method for polar coding, comprising the steps of: enter a sequence of bits, and the sequence of bits contains bits that contain the index block synchronization (SSBI); perform interleaving on the bit sequence, and output the interleaved bit sequence, wherein the SSBI is mapped to a sequence set corresponding to the interleaved bit sequence, and the sequence set is {2, 3, 5}, where {2, 3, 5} are sequence numbers of positions in an interleaved sequence for placing bits therein to indicate SSBI; appending d cyclic redundancy check (CRC) bits to the interleaved bit sequence to obtain a concatenated bit sequence, where d is a positive integer; interleaving the connected bit sequence based on a distributed cyclic redundancy check (D-CRC) interleaving pattern to output the D-CRC interleaved bit sequence; performing polar encoding on the D-CRC-interleaved bit sequence to obtain a polar-encoded bit sequence; and a polar-coded bit sequence is output. 2. The encoding method of claim 1, wherein the bits further comprise a half frame indicator (HFI), the method further comprising mapping the HFI to the lowest natural bit in the information bit set, the information bit set being the set bits, which is obtained by sorting, in ascending order, the natural sequence numbers of the subchannels corresponding to the information bits. 3. The encoding method according to claim 1, wherein performing polar coding with respect to the D-CRC interleaved bit sequence specifically comprises mapping bits in the D-CRC interleaved bit sequence to polar subchannels of the remaining subchannels except for subchannels d bits. CRC. 4. The encoding method according to claim 1, wherein d is 24. 5. The encoding method according to any one of claims 1 to 4, wherein the D-CRC interleaving pattern is: (0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55). 6. The encoding method according to claim 1, wherein when the bits contain an SFN, a part of the SFN is mapped to a subset in a sequence set corresponding to the interleaved bit sequence, and the subset contains {10, 30, 8, 17, 18, 23, 16} or the subset contains {6, 10, 30, 8, 17, 18, 23}. 7. The encoding method according to claim 1, wherein performing polar encoding with respect to the D-CRC interleaved bit sequence to obtain a polar-encoded bit sequence comprises encoding the D-CRC interleaved bit sequence according to an encoding formula to obtain a polarly - encoded bit sequence, and the length of the polar-encoded bit sequence is N, while the encoding formula is x _one ^N =u _one ^N G _N , where u ₁ ^N = (u ₁ , u ₂ , …, u _N ) is a binary row vector representing a D-CRC interleaved bit sequence, x ₁ ^N = (x ₁ , x ₂ , …, x _N ) - polar -encoded bit sequence, G _N is a matrix for generating a polar code, consisting of N rows and N columns. 8. A polar encoding device comprising a processor and a memory, wherein the memory stores a group of programs, the processor is configured to call the programs stored in the memory, and, when the programs are executed, the processor executes the method according to any one of claims 1-7. 9. A computer-readable storage medium containing instructions, wherein, when the instructions are executed in the computer, the computer executes the method according to any one of claims 1-7. 10. Device for encoding, containing means for obtaining a first bit sequence, the first bit sequence comprising bits comprising a synchronization signal block index (SSBI); means for interleaving the first bit sequence to obtain an interleaved sequence, wherein the bits containing the SSBI are placed in a set in an interleaved sequence, which set is {2, 3, 5}; means for adding d cyclic redundancy check (CRC) bits to the interleaved sequence to obtain a second bit sequence, wherein d is a positive integer; means for performing distributed CRC interleaving (D-CRC) on the second bit sequence according to the D-CRC interleaving pattern to obtain a second interleaved sequence; means for polar encoding the second interleaved sequence to obtain an encoded sequence; and a means for outputting the encoded sequence. 11. The apparatus of claim 10, wherein the bits further comprise a half-frame indicator (HFI), wherein the HFI is placed at the lowest bit position in the information bit set, the information bit set being the bit set that is obtained by sorting, in order increasing, natural sequence numbers of subchannels corresponding to polar information bits. 12. The apparatus of claim 10, wherein the means for performing D-CRC interleaving with respect to the second bit sequence further comprises that at least one bit for indicating timing in the second bit sequence is located at at least one bit position, corresponding to the remaining polar subchannels except for the subchannels d of the CRC bits. 13. The device according to claim 10, while d is equal to 24. 14. An apparatus according to any one of claims 10-13, wherein the interleaving pattern is: (0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55). 15. The apparatus of claim 10, wherein the bits further comprise a set of bits for specifying a system frame number (SFN), wherein part of the set of bits for specifying an SFN is placed in a set which set contains {10, 30, 8, 17, 18, 23 ,16} or {6, 10, 30, 8, 17, 18, 23}. 16. The apparatus of claim 10, wherein the means for polar encoding the second interleaved sequence to obtain the encoded sequence is further configured to encode the second interleaved sequence according to an encoding formula to obtain an encoded sequence, wherein the length of the encoded sequence is N, wherein the encoding formula is x _one ^N =u _one ^N G _N , where u ₁ ^N = (u ₁ , u ₂ , …, u _N ) is a binary row vector representing a D-CRC interleaved bit sequence, x ₁ ^N = (x ₁ , x ₂ , …, x _N ) - polar -encoded bit sequence, G _N is a matrix for generating a polar code, consisting of N rows and N columns. 17. A polar decoding method performed by a communication device in a wireless communication network, the method comprising: a coded sequence is received, wherein the coded sequence is obtained by performing polar coding on the first interleaved sequence, the first interleaved sequence is obtained by interleaving the first bit sequence according to the interleaving pattern, the first bit sequence is obtained by adding a series of cyclic redundancy check (CRC) bits to a second interleaved sequence, wherein the second interleaved sequence is obtained by interleaving a second bit sequence containing bits for indicating timing, wherein the bits for indicating timing contain a set of bits for indicating a synchronization signal block index (SSBI), and the second interleaved sequence has sequence numbers , starting at sequence number 0, the bits from the bit set to indicate SSBI are placed at the positions indicated by sequence numbers 2, 3, and 5 in the second oh interleaved sequence; performing polar decoding of the encoded sequence to obtain a decoded sequence; and output the decoded sequence. 18. The method of claim 17, wherein the bits for indicating timing further comprise one bit for indicating a half-frame indicator (HFI), wherein the one bit for indicating HFI is placed at the position indicated by the lowest sequence number in the second interleaved sequence. 19. The method of claim 18, wherein the lowest sequence number in the second interleaved sequence is 0. 20. The method of claim 17, wherein the number of CRC bits is 24. 21. The method of claim 17, wherein the interleaving pattern is: (0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55). 22. The method of claim 17, wherein the bits for indicating the timing further comprise a set of bits for indicating a system frame number (SFN), wherein part of the set of bits for indicating the SFN is placed partly at the positions indicated by sequence numbers 6, 10, 30, 8 , 17, 18, 23 in the second interleaved sequence. 23. A communication device in a wireless communication system capable of polar decoding and comprising at least one processor and a memory that stores program instructions for execution by at least one processor, wherein the program instructions, when executed by at least one processor, instruct the device : receive an encoded sequence, wherein the encoded sequence is obtained by performing polar encoding on the first interleaved sequence, the first interleaved sequence is obtained by interleaving the first bit sequence according to the interleaving pattern, the first bit sequence is obtained by adding a series of cyclic redundancy check (CRC) bits to a second interleaved sequence, wherein the second interleaved sequence is obtained by interleaving a second bit sequence containing bits for indicating timing, wherein the bits for indicating timing contain a set of bits for indicating a synchronization signal block index (SSBI), and the second interleaved sequence has sequence numbers , starting at sequence number 0, the bits from the bit set to indicate SSBI are placed at the positions indicated by sequence numbers 2, 3, and 5 in the second oh interleaved sequence; perform polar decoding of the encoded sequence to obtain a decoded sequence; and output the decoded sequence. 24. The apparatus of claim 23, wherein the bits for indicating timing further comprise one bit for indicating a half-frame indicator (HFI), with one bit for indicating HFI placed at the position indicated by the lowest sequence number in the second interleaved sequence. 25. The apparatus of claim 24, wherein the lowest sequence number in the second interleaved sequence is 0. 26. The apparatus of claim 23, wherein the number of CRC bits is 24. 27. The apparatus of claim 24, wherein the interleaving pattern is: (0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55). 28. The device according to claim 24, wherein the bits for specifying the timing further comprise a set of bits for specifying a system frame number (SFN), wherein part of the set of bits for specifying the SFN is placed partly at positions indicated by sequence numbers 6, 10, 30, 8 , 17, 18, 23 in the second interleaved sequence. 29. The apparatus of claim 23, wherein the apparatus is a base station or a user terminal. 30. A communication device configured for polar decoding, the device comprising: an input interface circuit, a logic circuit, and an output interface circuit; wherein the input interface circuit is configured to receive a coded sequence, wherein the coded sequence is obtained by performing polar coding on the first interleaved sequence, wherein the first interleaved sequence is obtained by interleaving the first bit sequence according to the interleaving pattern, wherein the first bit sequence is obtained by adding a row cyclic redundancy check (CRC) bits to a second interleaved sequence, wherein the second interleaved sequence is obtained by interleaving a second bit sequence containing bits for indicating timing, wherein the bits for indicating timing contain a set of bits for indicating a synchronization signal block index (SSBI) , and the second interleaved sequence has sequence numbers starting at sequence number 0, bits from the bit set for indicating SSBI are placed in positions indicated by serial numbers 2, 3 and 5 in the second interleaved sequence; wherein the logic circuitry is configured to perform polar decoding of the encoded sequence to obtain a decoded sequence; and wherein the output interface circuit is configured to output the decoded sequence. 31. The apparatus of claim 30, wherein the bits for indicating timing further comprise one bit for indicating a half-frame indicator (HFI), the one bit for indicating HFI being placed at the position indicated by the lowest sequence number in the second interleaved sequence. 32. The apparatus of claim 31, wherein the lowest sequence number in the second interleaved sequence is 0. 33. The apparatus of claim 30, wherein the number of CRC bits is 24. 34. The apparatus of claim 30, wherein the interleaving pattern is: (0 2 3 5 7 10 11 12 14 15 18 19 21 24 26 30 31 32 1 4 6 8 13 16 20 22 25 27 33 9 17 23 28 34 29 35 36 37 38 39 40 41 42 43 46 44 49 50 51 52 53 54 55). 35. The device according to claim 32, wherein the bits for specifying the timing further comprise a set of bits for specifying a system frame number (SFN), wherein part of the set of bits for specifying the SFN is placed partly at positions indicated by sequence numbers 6, 10, 30, 8 , 17, 18, 23 in the second interleaved sequence. 36. A non-volatile computer-readable storage medium that stores program codes for execution by one or more processors in a communication device, the program codes containing instructions for: receiving a coded sequence, wherein the coded sequence is obtained by performing polar coding on the first interleaved sequence, wherein the first interleaved sequence is obtained by interleaving the first bit sequence according to the interleaving pattern, wherein the first bit sequence is obtained by adding a series of cyclic redundancy check (CRC) bits to a second interleaved sequence, wherein the second interleaved sequence is obtained by interleaving a second bit sequence containing bits for indicating timing, wherein the bits for indicating timing contain a set of bits for indicating a synchronization signal block index (SSBI), and the second interleaved sequence has sequence numbers , starting at sequence number 0, the bits from the bit set to indicate SSBI are placed at the positions indicated by sequence numbers 2, 3, and 5 in the second interleaved sequence; performing polar decoding of the encoded sequence to obtain a decoded sequence; and output of the decoded sequence. 37. The non-volatile computer-readable storage medium of claim 36, wherein the bits for indicating timing further comprise one bit for indicating a half-frame indicator (HFI), with one bit for indicating HFI placed at the position indicated by the lowest sequence number in the second interleaved sequence. 38. The non-volatile computer-readable storage medium of claim 37, wherein the lowest sequence number in the second interleaved sequence is 0. 39. The long-term computer-readable storage medium according to claim 37, wherein the bits for indicating the timing further comprise a set of bits for indicating a system frame number (SFN), wherein part of the set of bits for indicating the SFN is placed partly at positions indicated by sequence numbers 6, 10, 30, 8, 17, 18, 23 in the second interleaved sequence.

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