RU2633126C2 - Strengthening mechanism of transfer and/or configuration of one protocol of inter-connections for another protocol of inter-connections - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: LLI master with interconnection architecture, containing: a processor for generating a transaction not compatible with LLI; the conversion logic associated with the processor and designed to convert a transaction that is not LLI compliant to an LLI package; and an LLI controller associated with the conversion logic. The LLI controller is for communicating the device with the interconnect architecture with the LLI communication channel and the LLI controller is for transmitting the symbol corresponding to the LLI packet over the LLI channel in which the transaction is selected from the PCI configuration transaction and the PCIE configuration transaction and in which the conversion logic should convert transaction configuration in the LLI service package.

EFFECT: improved security of data transmission.

22 cl, 10 dwg

Description

FIELD OF THE INVENTION

The embodiments described herein typically relate to interconnects. In particular, embodiments described herein generally relate to listing and / or configuration of devices connected by interconnects.

Brief Description of the Drawings

The invention may be best understood by referring to the following description and accompanying drawings, used to explain embodiments of the invention. In the drawings:

FIG. 1 is a block diagram of an embodiment of an LLI environment comprising an embodiment of an LLI master connected to an embodiment of an LLI slave via an LLI communication channel;

FIG. 2 is a flowchart of an embodiment of a method that may be executed by an LLI master;

FIG. 3 is a flowchart of an embodiment of a method that may be performed by an LLI slave;

FIG. 4 is a block diagram of exemplary embodiments of corresponding PCIE-LLI transformations;

FIG. 5 is a block diagram of an embodiment of an integrated logic for localizing a PCIE root complex;

FIG. 6 is a block diagram of an embodiment of a mobile wireless device in which embodiments of the invention may be present;

FIG. 7 is an embodiment of a PCIe compatible interconnect architecture comprising a multi-level stack;

FIG. 8 is an embodiment of various protocols to be transmitted at various physical layers of an interconnect architecture;

FIG. 9 is an embodiment of a low voltage computer platform;

FIG. 10 is an embodiment of a block diagram of a computer system.

Detailed Description of Embodiments

Methods, devices, and systems for enhancing the enumeration and / or configuration mechanism of one interconnect protocol for another interconnect protocol are disclosed herein. In the following description, numerous specific details are set forth (for example, specific interconnection protocols, transaction types, transaction transformation types, logical implementations, logical separation / integration details, sequence of operations, types and relationships of system components, etc.). However, it should be understood that embodiments of the invention may be practiced without these specific details. In other cases, well-known schemes, structures and technologies are not shown in detail, so as not to interfere with the understanding of the present description.

The Mobile Industry Processor Interface (MIPI ^® ) Alliance is an open membership organization with the goal of defining and promoting open technical requirements for interfaces within mobile terminals. The MIPI Low Latency Interfaces (LLI) Working Group has created the MIPI® Alliance Low Latency Interface (LLI) specifications. For simplicity, this specification will here also be referred to as MIPI LLI or simply LLI.

LLI is a low-latency interface designed to connect devices (e.g., a mobile device or terminal) at the interconnect level (e.g., via the Open Core Protocol (OCP), Advanced Microcontroller Bus Architecture, AMBA ^® ) , etc.) using memory-mapped transactions. The LLI Link is a bi-directional interface that allows any device to initiate transactions. LLI is a point-to-point interconnect that allows devices to communicate on separate microcircuits, as if the device located on the remote microcircuit were on the local microcircuit. The LLI specification is expressed as a multi-level transaction-level protocol in which targets and initiators located on chips connected by the LLI are able to exchange transactions essentially without software intervention, which helps to achieve low latency. LLI also typically exhibits low power consumption, which tends to make LLI suitable for cell phones, tablets and other battery-powered mobile devices. The only limitation for the LLI is that it currently does not have enough mechanism to list and configure devices connected to LLI links.

In FIG. 1 is a block diagram of an embodiment of an LLI environment 100 that includes an embodiment of an LLI master 101 associated with an embodiment of an LLI slave 120 by an LLI communication channel 115. The terms “master” and “slave” are used for compatibility with LLI specifications. The master device can also be a host device or just the first device, and the slave device can also be a slave device or just a second device. The LLI master can be configured to control the LLI slave. In some embodiments, the LLI master and slave devices may be different chips, arrays, integrated circuits, or potentially different packages.

Examples of suitable LLI master devices include, but are not limited to, application processor chips and chip application processor systems (SoCs). Examples of suitable LLI slaves are, in particular, coprocessor chips, wireless modem chips (e.g., cellular modem chips, wireless local area network (WLAN) modems, etc.) and data storage chips (e.g., flash memory chips) to name a few examples. As shown, the LLI slave device may be a wireless modem, data storage device, coprocessor, or other resource 126 that is used by the LLI master. LLI master and slave components can be displayed in memory to facilitate device addressing. The LLI master may be configured to control the entire system memory card.

The LLI master includes a processor 102, an LLI controller 106, and a memory controller 109. The processor, the LLI controller, and the memory controller all communicate with each other or otherwise when communicating with each other using one or more buses or other interconnects 105. The memory controller communicates or connects to the memory 111. The LLI controller 106 communicates or connects with one end of the LLI link 115. The LLI controller is configured to communicate a master device with an LLI communication channel. The LLI slave 120 also includes an LLI controller 121 that communicates or connects to the other end of the LLI communication channel 115.

In some embodiments, the enumeration and / or configuration mechanism of the first interconnect protocol may be reinforced or reused for a second, different interconnect protocol. In one embodiment, the second interconnect protocol may not have an inherent configuration and / or enumeration mechanism. In another embodiment, the second interconnect protocol may have an enumeration and / or configuration mechanism, but it may not be as good, extensive, comprehensive, well designed, well tested, flexible, or fast as the mechanism of the first interconnect protocol. In yet another embodiment, the second interconnect protocol may have an enumeration and / or configuration mechanism, but for some other reason it may be desirable to use the enumeration and / or configuration mechanism of the first protocol (for example, because it has a feature not found in another protocol, familiar with him or he is preferred, etc.).

As will be further described below, in some embodiments, a mechanism for listing and / or configuration of a peripheral component interconnect (Peripheral Component Interconnect, PCI), express peripheral component interconnect (Peripheral Component Interconnect Express, PCIE), or enhanced peripheral component interconnect (Peripheral Component Interconnect extended, PCI-X) can be reinforced and / or reused for the MIPI LLI, although the scope of the invention is not limited to this. In other embodiments, an Internet protocol enumeration and / or configuration mechanism other than PCI, PCIE, or PCI-X can be reinforced or reused for LLI, such as a future version of PCI, PCIE, or PCI-X, a derivative version PCI, PCIE, or PCI-X, a protocol associated with PCI, PCIE, or PCI-X, a protocol similar to PCI, PCIE, or PCI-X, a replacement for PCI, PCIE, or PCI-X, or a protocol with enumeration and / or configuration capabilities comparable to PCI, PCIE, or PCI-X. Alternatively, alternatively, other protocols with enumeration and / or configuration capabilities may be used, such as, for example, Universal Serial Bus (USB) protocols, other protocols derived from USB or connected to USB, or other developed in future protocols. The terms “peripheral component interconnect protocol”, “PCI based protocol” and the like, as used herein, are collectively referred to as PCI, PCIE, PCI-X and other PCI based protocols or derivatives of PCI. In other further embodiments, the PCI, PCI-X, PCIE enumeration and / or configuration mechanism, or some other interconnect protocol, may be enhanced or reused for a non-LLI interconnect protocol (for example, a future version or derivative LLI protocol or another interconnect protocol that has limited enumeration and / or configuration capabilities). In other embodiments, Unified Protocol (Unipro), digRF, SuperSpeed Inter-Chip (SSIC), or others, may be used instead of LLI. In the embodiments described herein, PCIE is often used as an example protocol, although it should be understood that PCIE can alternatively be replaced by PCI or PCI-X or USB or another appropriate interconnect protocol having an enumeration and configuration mechanism. In addition, in the embodiments described below, the LLI is often used as an example protocol, although it should be understood that the LLI may alternatively be replaced by a future version of the LLI, a derived LLI protocol, an LLI-related protocol, a protocol similar to LLI, or another interconnect protocol that may benefit from the enhancement and / or reuse of the enumeration and configuration capabilities of a different interconnect protocol.

Referring again to FIG. 1, the memory 111 has a PCIE module 112. Alternatively, the memory may have a module of another interconnect protocol that is different from LLI (e.g., PCI, PCI-X, PCI-based protocol, USB, etc.). In some embodiments, the PCIE module may be configured to control communication through the PCIE bus. The PCIE bus is not shown and in reality it may not be the PCIE bus, as will be explained later. For example, a PCIE module may contain a PCIE bus driver, a PCIE software stack, or similar functionality. In some embodiments, the PCIE module may comprise a substantially standard PCIE bus driver, a PCIE software stack, or at least a portion of them sufficient to enumerate and / or configure, as described herein. Various large operating systems typically contain standard PCIE bus drivers and / or PCIE software stacks suitable for embodiments.

Standard PCIE bus drivers and / or PCIE software stacks typically have a mechanism for listing and configuring devices connected to PCIE buses. The shown module has a PCIE enumeration module 113, which is useful for listing a PCIE to list one or more LLI slaves to an LLI master. For example, the PCIE enumeration module may contain instructions, a control program, subroutines, or procedures that allow the processor to open or discover devices connected to the PCIE buses, to reveal or discover the capabilities of devices connected to the PCIE buses, to open or discover the resources that the devices will use, connected to PCIE buses (for example, how much memory the devices will use), types and numbers of supported breakers, type and number of functions in each device, etc. . The PCIE module shown also has a PCIE configuration module 114, useful for PCIE configuration. For example, a PCIE configuration module may contain instructions, a control program, routines or procedures that allow the processor to configure devices attached to the PCIE buses, for example, by configuring memory address ranges, by configuring interrupt vectors, by modifying PCIE configuration registers and / or capability structures, etc. d. Although individual PCIE enumeration and configuration modules have been shown, other embodiments may combine these modules into a single module. In other embodiments, a PCIE enumeration module may be contained without a PCIE configuration module, or a PCIE configuration module may be contained without a PCIE enumeration module.

In some embodiments, PCIE enumeration modules 113 and PCIE configuration modules 114 may be substantially standard and may be useful to perform substantially standard enumeration and configuration. In some embodiments, the LL1 master 101 can amplify or reuse essentially the standard PCIE enumeration modules and / or PCIE configuration modules to enumerate and / or configure the LLI slave 120 120 through the LLI communication channel 115. In some embodiments, this can help to avoid the need to develop new enumeration and / or configuration mechanisms specifically for the LLI, which can help to avoid or at least reduce development time and costs. In addition, PCIE enumeration modules and configurations tend to be well designed, tested, and understood. In addition, they are already widely available through several large operating systems. In addition, PCIE uses standardized enumeration and configuration mechanisms. The use of such standardized mechanisms can help to avoid the development of specialized and / or proprietary enumeration mechanisms and / or configuration mechanisms, which may tend to reduce device interoperability.

Referring again to FIG. 1, the processor 102 may execute instructions from the PCIE enumeration module 113 and / or the PCIE configuration module 114 (for example, as part of an operating system executed on the processor) that can configure the processor to have a PCIE enumeration module / mechanism / logic 103 and / or module / mechanism / logic 104 of the PCIE configuration, respectively. In some embodiments, this may cause the processor to form and provide a transaction 110 based on a PCIE or PCI. That is, the processor can form and represent a transaction having an interconnect protocol other than LLI. The PCIE module / mechanism / logic and / or the PCIE module / mechanism / configuration logic can provide PCIE or PCI based transactions 110 to the LLI controller 106 of the LLI of the LLI master via one or more interconnects 105.

The LLI controller comprises an embodiment of the PCIE-LLI transform logic 107 that is coupled to the processor 102. In another embodiment, the PCIE-LLI transform logic 107 may be separate from the LLI controller 106, but associated with the LLI controller 106 (eg, connected or logically located between the LLI controller and the processor). PCIE-LLI conversion logic 107 may accept PCIE transactions 110. In some embodiments, PCIE-LLI transform logic 107 may be configured to implement PCIE-LLI transforms and LLI-PCIE transforms. Alternatively, PCI-LLI translation logic may be contained for conversion between PCI (or another PCI-based protocol) and LLI, or other logic for conversion between the LLI and another interconnect protocol other than LLI may be contained. The PCIE-LLI conversion logic 107 may be configured to convert the received PCIE transactions 110 into corresponding LLI transactions, LLI compatible data packets or formats 128 that implement or represent PCIE software transactions. In some embodiments, the conversion may comprise mapping bits or fields of PCIE transactions to corresponding bits or fields of LLI packets or LLI compatible data formats. Specific examples of how this can be done will be described hereinafter. PCIE-LLI conversion logic may then provide LLI packets or other LLI data formats 128 compatible with the associated LLI stack logic 108. In some embodiments, the implementation of the LLI stack logic may alternatively represent a substantially standard LLI stack that includes a transaction layer, a data link layer, a PHY adapter layer, and one or more M-PHYs. In some embodiments, PCIE-LLI translation logic may be configured to provide LLI transactions that it generates at the transaction level of logic 108 of the LLI stack. The LLI stack logic can convert the received LLI packets to the corresponding MIPI symbols and then the M-PHYs of the LLI stack logic 108 and / or the LLI controller 106 can transmit MIPI symbols 116 received from LLI packets 128) that implement or represent PCIE transactions 110 on line 115 communication LLI. Accordingly, in some embodiments, PCIE transactions used for enumeration and / or configuration can be transmitted over the LLI link as MIPI symbols that were received from LLI packets.

The LLI slave 120 comprises an LLI controller 121. The LLI controller connects to the other opposite end of the LLI communication channel 115 and is configured to connect the LLI slave to the LLI communication channel. The LLI controller 121 comprises LLI stack logic 122. In some embodiments, the LLI stack logic 122 may further represent an essentially standard LLI stack that contains a transaction layer, a data link layer, a PHY adapter layer, and one or more M-PHYs. The M-PHYs of the LLI stack logic 122 may receive MIPI symbols (derived from LLI packets 128) from the LLI link 112 that carry out or represent PCIE transactions 110. The LLI stack logic 122 may process MIPI symbols and generate LLI transactions, packets, or other LLI compatible data formats 129. The transaction level of the LLI stack logic 122 may provide LLI transactions or packets 129 for an embodiment of the PCIE-LLI transform logic 123. Alternatively, LLI transactions or packets may be provided for PCI-LLI translation logic or for logic to perform conversion between the LLI protocol and a non-LLI protocol other than PCI and PCIE.

In the drawing, PCIE-LLI conversion logic 123 is part of controller 121 LL1. In another embodiment, the PCIE-LLI transform logic 123 may be separate from the LLI controller 121, but associated with the LLI controller 121 (for example, coupled or logically located between the LLI controller and the embodiment of the PCIE endpoint logic 125). PCIE-LLI transform logic 123 is configured to implement PCIE-LLI transforms and LLI-PCIE transforms. Alternatively, other PCI-based conversions or other transformations may be performed as described here elsewhere. PCIE-LLI conversion logic may convert received LLI transactions or packets 129 that implement or represent PCIE transactions 110 into corresponding PCIE transactions 124. In some embodiments, the implementation may include mapping bits or fields of LLI packets to accommodate the corresponding bits or fields of transaction PCIE. Specific examples of such transformations will be further discussed below.

The PCIE-LLI conversion logic 123 is associated with an embodiment of the PCIE endpoint logic 125 125. Alternatively, instead of the PCIE endpoint logic, the PCI endpoint logic can be used or the endpoint logic of a different interconnect protocol other than LLI, PCI, and PCIE can be used. PCIE-LLI conversion logic 123 can provide PCIE transactions 124, it generates PCIE endpoint logic 125. In some embodiments, PCIE transactions 124 provided for the PCIE endpoint logic may be identical or at least substantially identical to PCIE transactions 110 originally provided from processor 101 (for example, bits in the packet fields of a PCIE transaction 124 may be identical to the bits in the fields of the transaction packet 110 PCIE). In some embodiments of the endpoint logic, the PCIE may have as much PCIE logic as it can be with a normal PCIE device connected to the PCIE bus. Alternatively, the PCIE endpoint logic may have at least as many PCIE logic as is necessary to maintain the desired enumeration and / or configuration required for a particular embodiment. For example, in some embodiments, the implementation of the PCIE endpoint logic may comprise PCIE compatible configuration registers (or other PCI-based ones) (e.g., PCIE index registers, etc.) and capability structures that may be implemented with the possibility of using the embodiments described herein. As another example, in some embodiments, the implementation of the PCIE endpoint logic may comprise memory / transaction processing / implementation logic and / or PCIE configuration transaction / maintenance logic. In some embodiments, the PCIE endpoint logic may be input to the LLI slave even though the LLI slave does not need to have PCIE buses and / or the PCIE endpoint logic does not have to be connected to the PCIE bus.

In some embodiments, PCIE endpoint logic may represent the integrated endpoint logic of the PCIE root complex. In PCIE, a host device is also sometimes referred to as an integrated root complex device. A remote device is sometimes referred to as an endpoint or endpoint of a root complex. Historically, in PCI, the host device and the remote device were different chips installed on the circuit board. The PCIE also allows the endpoint device to integrate onto the chip or matrix with the root complex device instead of being on a separate remote chip. Such an integrated device is also sometimes referred to in the art as an integrated endpoint device of a root complex. The device of the root complex and the integrated device of the end point of the root complex are integrated together on the microcircuit or on the matrix. In the case of integrated PCIE root endpoint logic, the host processor may not even know or be aware of the LLI entering the communication channel process, but rather can communicate with the root endpoint endpoint integrated device as if it were integrated by the processor on the chip or to the matrix.

In some embodiments, PCIE transactions 110 and / or PCIE transactions 124 may be used to list and / or configure the LLI slave 120. In the case of a configuration, PCIE transactions 124 may be configured to modify the configuration registers and / or capability structures based on the PCIE (or other PCI based) of the slave. In some embodiments, for example, in the case of some enumeration, PCIE transactions 124 may cause or result in PCIE endpoint logic generating backward PCIE 124 transactions 124 to be transmitted to the LLI master. These PCIE transactions 124 can be provided to the LLI controller 121 by the slave device, transmitted by the LLI stack logic as MIPI symbols via the LLI communication channel 115, received as MIPI symbols by the LLI stack of the master device LLI controller 106, to efficiently jump back to the previously described. The slave PCIE-LLI conversion logic 123 may convert PCIE packets or transactions 124 into corresponding LLI packets. MIPI symbols 116 that carry out or represent PCIE transactions 124 can be transmitted over the LLL communication channel. PCIE-LLI conversion logic 107 of the host device can convert LLI packets recovered from these MIPI symbols received through the LLI communication channel to corresponding PCIE transactions 110. These PCIE transactions 110 may be identical or at least substantially identical (e.g., functionally equivalent) to the originally sent PCIE transactions 124.

In FIG. 2 is a flowchart of an embodiment of a method 230 that may be executed by an LLI master. In some embodiments, the operations and / or method shown in FIG. 2 can be executed by the LL1 master 101 or inside the LL1 master 101 shown in FIG. 1. The components, features, and specific optional details described herein for LL1 master 101 are also optionally applied to operations and / or method 230 that may be performed in embodiments and / or within LLI master 101. Alternatively, the operations and / or method shown in FIG. 2 can be performed by a similar and / or completely different LLI master than that shown in FIG. 1. In addition, the LLI master shown in FIG. 1 may perform operations and / or methods in exactly the same way, similarly or completely differently than in FIG. 2.

The method comprises forming, in block 231, a transaction executed by a protocol other than the LLI inside the LLI master. In some embodiments, transactions may be performed using the PCI protocol, the PCIE protocol, another PCI-based protocol, or another protocol other than the LLI. In some embodiments, the transaction may be part of at least the listing of the LLI slave associated with the LLI communication channel, or the configuration of the LLI slave associated with the LLI communication channel.

The method comprises converting, in a transaction block 232, which is implemented by a non-LLI interconnect protocol, into an LLI packet or transaction. In some embodiments, the LLI packet may carry out or represent a formed PCI-based transaction. In some embodiments, the implementation may comprise mapping bits or fields of the generated PCI-based transaction to the corresponding bits or fields of the LLI packet. In some embodiments, an LLI packet may be provided for the transaction level of an optionally standard LLI stack.

The method also comprises transmitting in block 233 MIPI symbols received from the LLI packet through the LLI communication channel. In some embodiments, MIPI symbols may be implemented or presented, and may be used to transmit a PCI-based originally generated transaction or other transaction performed using an interconnect protocol other than LLI.

In FIG. 3 is a flowchart of an embodiment of a method 335 that may be executed by an LLI slave. In some embodiments, the operations and / or method shown in FIG. 3 may be performed by the LLI slave 120 shown in FIG. 1, or inside it. The components, features, and specific optional details described herein for the LL1 slave 120 are also optionally applied to operations and / or to the method 335, which in embodiments may be performed by or within the LLI slave 120. Alternatively, the operations and / or method shown in FIG. 3 can be performed by a similar or completely different LLI slave than that shown in FIG. 1, or inside it. In addition, the LLI slave shown in FIG. 1 may perform operations and / or methods the same, similar, or completely different from those shown in FIG. 2.

The method comprises receiving, in block 336, the MIPI symbol that was received from the LLI packet over the LLI link of the LLI slave. In some embodiments, the received MIPI symbol may implement or represent, and may be used to transmit, a transaction based on a PCI protocol or another interconnect protocol other than LLI.

The method comprises, in block 337, converting the LLI packet, which corresponds and / or is obtained from the received MIPI symbol, to a transaction that has a different interconnect protocol than the LLI. In some embodiments, the LLI packet may be converted into a transaction using the PCI protocol, the PCIE protocol, or another protocol other than the LLI. In some embodiments, the transform may comprise mapping bits or fields of an LLI packet to corresponding bits or fields of a transaction.

The method comprises, at block 338, a transaction service that is performed using an interconnect protocol other than the LLI. In some embodiments, a transaction may be served by PCI endpoint logic or PCIE endpoint logic. In some embodiments, transaction service can be performed in conjunction with at least configuring the LLI slave or listing the LLI slave to the LLI master.

In FIG. 2-3 illustrate methods in which a master device generates transactions and transmits symbols representing these transactions to the slave device. Alternatively, as mentioned earlier, analogue reverse methods are also considered in which the slave generates transactions and transmits the symbols representing these transactions to the master. In some embodiments, this can be done essentially as described above for FIG. one.

In FIG. 4 is a block diagram of exemplary embodiments of an example of corresponding PCIE-LLI transforms 440. An embodiment of the PCIE-LLI conversion logic 407 of the master device and an embodiment of the PCIE-LLI conversion logic 423 of the slave device are shown. In some embodiments, the host PCIE-LLI conversion logic 407 and / or the slave PCIE-LLI conversion logic 423 shown in FIG. 4, respectively, can be inserted into the LLI master 101 and / or the LLI slave 120 shown in FIG. 1. Alternatively, the PCIE-LLI conversion logic 407 of the master device and / or the PCIE-LLI conversion logic 423 of the slave device 423 shown in FIG. 4, respectively, can be inserted into similar or different LLI masters and slaves other than those shown in FIG. 1. In addition, the LLI master 101 and / or slave 120 shown in FIG. 1 may be similar or different from other PCIE-LLI conversion logic shown in FIG. four.

The processor 402 of the host device may transmit the memory-mapped downstream transaction 441 further to the memory-mapped transaction to the PCIE-LLI conversion logic of the PCIE-LLI of the host device, the transaction packet conversion logic LL2. The term "downstream" is used here to refer to the direction from the master to the slave. In contrast, the term “upstream” is used here to refer to the direction from the slave to the master. Conversion logic 442 may be configured to convert the downstream mapped transaction 441 into a corresponding downstream LLI transaction packet 443. The downstream LLI transaction packet 443 may be transmitted to the slave PCIE-LLI conversion logic 423.

The LLI transaction packet in the conversion logic of the memory-mapped transaction of the PCIE-LLI conversion logic of the slave device may receive the LLI transaction packet 443 in the downstream transaction. Conversion logic 444 may be configured to convert the downstream LLI transaction packet 443 into a corresponding mapped downstream transaction 445. A mapped downstream transaction 445 may be transmitted to the PCIE endpoint logic 425 of the slave.

The slave PCIE endpoint logic 425 may transmit the memory mapped transaction 446 in an upstream direction in the memory mapped transaction to the LLIE transaction packet transform logic 447 of the slave PCIE-LLI transform logic. Conversion logic 447 may be configured to convert the memory-mapped transaction 446 in the upstream into the corresponding LLI transaction packet 448 448 in the upstream. An upstream LLI transaction packet 448 may be transmitted in the direction of the PCIE-LLI transform logic of the host device.

The logic 449 converting the LLI transaction packet into a memory-mapped transaction of the PCIE-LLI transformation logic of the host device may receive the LLI transaction packet 448 in the upstream. Conversion logic 449 may be configured to convert the LLI transaction packet 448 in the upstream into the corresponding in-memory mapped transaction 450 in the upstream. An upstream mapped transaction 450 may be transferred to the host processor 402.

The processor 402 of the host device may transfer the PCIE configuration transaction 451 in the downstream direction in the direction of the PCIE configuration transaction to the PCIE-LLI conversion logic of the PCIE-LLI transformation logic of the host device. LLI does not currently support configuration transactions. In some embodiments, PCIE configuration transactions can be mapped to LLI service packets that can be transmitted over an LLI link. Conversion logic 452 may be configured to convert downstream PCIE configuration transaction 451 to a corresponding downstream LLI service packet 453. Downstream LLI service packet 453 may be transmitted in the direction of the PCIE-LLI conversion logic of the slave.

Logic 454 converting the LLI service packet to the PCIE configuration transaction of the slave PCIE-LLI conversion logic can receive the downstream LLI service packet 453. Conversion logic 454 may be configured to convert the downstream LLI service packet 453 into the corresponding downstream PCIE configuration transaction 455. Downstream PCIE configuration transaction 455 may be sent in the direction of the logic 425 of the PCIE endpoint of the slave.

The slave PCIE endpoint logic 425 may transmit the reported message interrupt 456 in the upstream direction of the reported message interrupt to the PCIE-LLI conversion logic of the slave device conversion logic LLI conversion transaction logic 457. Conversion logic 457 may be configured to convert the reported upstream message interrupt 456 to the corresponding upstream LLI service packet 458. An upstream LLI service packet 458 may be transmitted in the direction of the PCIE-LLI transform logic of the host device.

The LLI service transaction to the message interrupt conversion logic 459 of the message of the PCIE-LLI transformation logic of the host device can receive the LLI service transaction 458 in the upstream. Conversion logic 459 may be configured to convert the upstream LLI service transaction 458 into a corresponding upstream message message interrupt 460. A reported upstream message interruption 460 may be transmitted in the direction of the host processor 402.

To further illustrate how PCIE transactions can be converted to LLI transaction-level packets, it may be useful to consider a few illustrative examples. Mapped reads and other mapped transactions may not have a useful data load. In such cases, most of the fields in the LLI packet (for example, the 73-bit LLI command request packet) can be populated based on the corresponding fields of the PCIE transaction (for example, the 48-bit PCIE request header format). For example, the PCIE transaction address and length fields can be mapped directly to the corresponding LLI transaction level length and address fields. Other fields, such as Requester ID (Requestor ID, Tag, and BE) fields, can be set statically. Other fields, such as memory attributes, can be sent as part of consecutive fields. Now let's look at the records displayed in the memory or other displayed in memory transactions that have a payload of data. A PCIE write request transaction can be converted to an LLI command request packet as described immediately before. Additionally, each 64 bits of the PCIE data payload can be converted to LLI write data request packet. A similar approach can be used for read reactions. Now consider PCIE configuration transactions. PCIE configuration transaction (for example, 48-bit PCIE configuration request transaction) can be converted to LLI service packet (for example, 73-bit address request packet LLI service records.) Certain fields, such as the numeric fields Requester ID, Tag, Bus / Dev / Fn, can be set statically. A register number can be sent as part of the address. Other fields, if necessary, can be sent as part of an unused address field.

In FIG. 5 is a block diagram of an embodiment of integrated logic 525 of an endpoint of a PCIE root complex. In some embodiments, the endpoint logic 525 shown in FIG. 5 may be inserted into the LLI slave 120 shown in FIG. 1. Alternatively, the endpoint logic 525 may be introduced in a similar or completely different manner from that shown in FIG. 1 LLI slave. In addition, the LLI slave shown in FIG. 1 may contain the same, similar or completely different endpoint logic compared to FIG. 5.

The endpoint logic contains logic in the memory-mapped PCIE service transactions 562 and logic for initiating the memory-mapped PCIE transactions 563. Endpoint logic also contains logic in transactions 564 of the PCIE configuration and PCIE compatible configuration registers and capability structures 565. Endpoint logic also contains logic to signal the signaling interruptions of 566 PCIE compatible messages. In some embodiments, each of these logics may be similar to substantially the same or the same logic in the standard Root-Complex PCIE Integrated Endpoint Logic. In some embodiments, the LLI slave device that contains the endpoint logic may not have a PCIE bus, and / or the endpoint logic may not be connected or communicate with the PCIE bus, even if one is present.

In FIG. 6 is a block diagram of an embodiment of a mobile wireless device 670 into which embodiments of the invention may be incorporated. In various embodiments, the mobile wireless device may include a laptop, tablet, smartphone, cell phone, digital audio player, or other mobile wireless device known in the art. In some embodiments, the LLI master and / or slave devices shown in FIG. 1 may be contained in the mobile wireless device shown in FIG. 6. Alternatively, the LLI master and / or slave shown in FIG. 1 may be contained in a device similar to or completely different from that shown in FIG. 6. In addition, the device shown in FIG. 6 may contain the same, similar, or completely different LLI masters and / or slaves compared to FIG. one.

The mobile wireless device comprises an application processor system on a chip (SoC) 601. The SoC has a processor 602 and an LLC controller 606. The SoC may comprise an embodiment of the conversion logic as disclosed herein elsewhere. The cellular modem 620A having an antenna also has an LLI controller 621A coupled to the LLC controller 606 by the LLI link 615A. A 620 V WiFi modem having an antenna also has a 621 V LLI controller connected to the 606 LLC 606 controller through a 615 V LLI link. Some, but not all wireless devices use dipole antennas. The volatile or non-volatile memory 620C has an LLI 621C controller connected to the LLC controller 606 via a LLI communication channel 615C. One example of volatile memory found in some, but not all, devices is dynamic random access memory (DRAM). One example of long-term memory found in some, but not all, devices is flash memory. The input / output (I / O) device 620D has an LLI controller 621D coupled to an LLC controller 606 via a communication channel 615D. A few examples of suitable input / output devices are, in particular, a speaker or other audio output devices, a keyboard output, an output to a display, input via a touch screen, output to a vibration transducer, and the like. Any cellular modem, WiFi modem, volatile or non-volatile memory, or I / O device may include embodiments of the conversion logic and endpoint logic disclosed here elsewhere. The mobile wireless device also includes a power supply chip 671, which is connected to the SoC 601. The power supply chip is connected to a battery 672 configured to power the mobile wireless device.

In FIG. 7 shows an embodiment of a multi-layer protocol stack. The layered protocol stack 700 contains any form of layered communication stack, such as the Quick Path Interconnect (QPI) stack, the PCie stack, the next generation high-performance computing interconnect stack, or another layered stack. In one embodiment, the protocol stack 700 is a PCie protocol stack containing a transaction layer 705, a data link layer 710, and a physical layer 720. An interface may be represented as a communication protocol stack 700. The presentation in the form of a stack of communication protocols may also be referred to in relation to a module or interface that implements / contains a protocol stack.

PCI Express uses packets to transfer information between components. Packets are formed at the Transaction Layer level 705 and at the Data Link Layer level 710 in order to transfer information from the transmission component to the receiving component. As the transmitted packets go through other layers, they expand with the additional information needed to process packets at these layers. On the receiving side, the reverse process takes place and the packets are converted from their representation at the physical layer 720 (Physical Layer) into a representation at the level 710 of the Data Link Layer and, finally, (for transaction-level packets, Transaction Layer Packet) into a form, which can be processed at the level of 705 transactions of the receiving device.

In one embodiment, transaction level 705 should provide an interface between the device processing core and the interconnect architecture, such as data link layer 710 and physical layer 720. In this regard, the primary responsibility of transaction level 705 is the assembly and disassembly of packets (that is, packets transaction level or TLP). Broadcast level 705 typically manages credit-based flow management for TLPs. PCie implements split transactions, that is, request and response transactions split in time, allowing the communication channel to carry out other traffic, while the target device is collecting data for the response.

In addition, PCie uses credit-based flow control. In this scheme, the device advertises the initial amount of credit for each of the receive buffers at the level of 705 transactions. An external device at the opposite end of the communication channel, such as the controller hub 115 shown in FIG. 1, counts the number of credits spent by each TLP. A transaction can be transferred if the transaction does not exceed the credit limit. After receiving the answer, the amount of credit is restored. The advantage of the credit scheme is that the delay in repaying the loan does not affect the characteristics, provided that the credit limit is not reached.

In one embodiment, the four transaction address spaces comprise a configuration address space, a memory address space, an I / O address space, and a message address space. Memory space transactions contain one or more read and write requests to transfer data to and from the mapped memory location. In one embodiment, memory space transactions are capable of using two different address formats, for example, a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Configuration space transactions are used to access the configuration space of PCIe devices. Transactions in the configuration space contain read requests and write requests. Message space transactions (or simply messages) are defined to support in-band communication between PCIe agents.

Therefore, in one embodiment, the transaction layer 705 assembles the header / payload 706 of the packet. The format for the current packet headers / payloads can be found in the PCIe specification on the PCIe specification website.

In FIG. 8 shows an embodiment of an example protocol stack for one or more of the interfaces discussed herein. For example, an interconnect may include a physical layer (PHY) to provide electrical / physical communications, while higher layers, such as a protocol, transaction, application or communication layer, may provide additional communications functionality. Here, the MPHY 850 is capable of being implemented with many different protocol layers, such as DigRF 855, UniPro 860, LLI 865, SSIC 870 (i.e., 3 USB protocols) or PCIe 875 (i.e. Mobile Express). The physical layer also contains D-PHY 805. The protocol layer also contains CSI 810 and DSI 815. The application layer also contains CSI 811, CSI 816, CSI 856, CSI 861, CSI 867, CSI 871 and CSI 876.

In FIG. 9 shows an embodiment of a low power computing platform. In one embodiment, the low power computing platform 900 comprises user equipment (UE). In some embodiments, a UE relates to a device that can be used for communication, such as a voice-enabled device. Examples of UEs are a phone, a smartphone, a tablet, an ultraportable laptop, and a low-power laptop. However, a low-power computing platform may also refer to any other platform to provide a low-power operating point, such as a tablet, low-power laptop, ultra-portable or ultra-thin laptop, microserver server, low-power desktop computer, transmitting device, receiving device, or any other known or an affordable computing platform. The platform shown depicts many different interconnects to interconnect numerous different devices. An exemplary discussion of these interconnects is provided below to provide opportunities for implementing and introducing the devices and methods disclosed herein. However, a low power platform 900 is not required to contain or implement the illustrated interconnects or devices. In addition, other devices and interconnect structures may be included that are not specifically shown.

Starting at the center of the drawing, platform 900 comprises an application processor 905. Often it comprises a low power processor, which may be a version of the processor configuration described herein or known in the industry. As an example, processor 900 is implemented as a single-chip system (SoC). In a specific illustrative example, the processor 900 comprises an Intel® Architecture Core ™ processor-based processor such as i3, i5, TI, or another such processor available from Intel Corporation, Santa Clara, California. However, it should be understood that other low-power processors, such as those available from Advanced Micro Devices, Inc., can also be integrated on the SoC. (AMD), Sunnyvale, California, MIPS-based project from MIPS Technologies, Inc. Sunnyvale, CA, an ARM-based project, licensed from ARM Holdings, Ltd. or its customer, or their licensees or copyright holders, which may instead be present in other embodiments, such as an Apple A5 / A6 processor, Qualcomm Snapdragon processor, or OMAR TI processor. Note that as the processor and SoC technologies from these companies improve, more components can be integrated into the SoC, shown as separate from the main processor 900. As a result, such interconnects (and related inventions) can be used on-chip.

In one embodiment, the application processor 905 runs an operating system, a user interface, and applications. Here, the application processor 905 often recognizes or communicates with the instruction set architecture of the instruction system, Instruction Set Architecture (ISA), so that the operating system, user interface, and applications directly use the operations / execution of operations by the processor 905. It also typically interacts through an interface with sensors, cameras , displays, microphones and mass storage. Some implementations allow the transfer of time-critical telecommunication processing to other components.

  As you can see, the main processor 905 communicates with a wireless interface 930, such as WLAN, WiGig, WirelessHD, or another wireless interface. It uses a compatible LLI, SSIC, or UniPort interconnect to link the main processor 905 and the wireless interface 930.

LLI supports a low latency interface. LLI usually allows memory sharing between two devices. A bi-directional interface transports memory transactions between two devices and allows the device to access the local memory of another device; often this is done without software intervention, as if it were the only device. LLI, in one embodiment, three classes of traffic are allowed carrying signals over a communication channel, reducing the GPIO count. As an example, the LLI defines a layered protocol stack for transmission or physical layer (PHY), such as MPHY, which is described in more detail below.

SSIC refers to the SuperSpeed Inter-Chip. SSIC can enable the design of high-speed USB devices that use the physical layer of low power. As an example, the MPHY level is used, while compatible USB 3.0 protocols and software are used in addition to MPHY for better energy performance.

UniPro describes a multi-level protocol stack with an abstraction of the physical layer, which provides a universal, error-handling, high-speed solution for interconnecting a wide range of devices and components: application processors, coprocessors, modems and peripherals, as well as supporting various types of data traffic, including messages management, mass data transfer and packet streaming. UniPro can support the use of MPHY or DPHY.

Other interfaces may also communicate directly with the host processor 905, debug module 990, network 985, display 970, camera 975, and memory 980 via other interfaces that may use the devices and methods described herein.

The debug interface 990 and the network 985 communicate with the application processor 905 through a debug interface 991, for example, a PTI, or a network connection, for example, a debug interface that operates via a functional network connection 985.

A display 970 comprises one or more displays. In one embodiment, the display 970 comprises a display with one or more touch sensors capable of receiving / detecting touch input. Here, the display 970 communicates with the application processor 905 through a display interface (DSI) 971. The DSI 971 defines protocols between the host processor and peripheral devices that can use the physical D-PHY interface. Typically, it accepts pixel formats and a specific set of commands for video formats and signaling, such as Display Pixel Interface 2 (DPI-2) and parameters for the control display module, such as Display Command Set (DCS). As an example, the DSI 971 operates at a frequency of approximately 1.5 Gb / s per route and up to 6 Gb / s.

Camera 975, in one embodiment, comprises an image sensor used to take photographs, video, or both. Front and rear cameras are common on mobile devices. Dual cameras can be used to provide support for stereoscopy. As can be seen in the drawing, the camera 975 communicates with the application processor 905 through a peripheral interconnect, such as CSI 976. The CSI 976 defines the interface between the peripheral device (eg, camera, image signal processor) and the main processor (eg, 905, broadband application mechanism). In one embodiment, data transfers are performed via DPHY, a unidirectional differential serial interface with data and clocks. The peripheral control in the embodiment takes place on a separate return channel, such as camera control. As an example, the CSI speed can range from 50 Mbit / s to 2 Gbit / s or in any range / s with any value of them.

The storage device 980 in one example contains non-volatile memory used by the application processor 905 to store a large amount of information. It may be based on flash technology or on a magnetic storage type such as a hard disk. Here, the storage device 980 communicates with the processor 905 through the interconnect 981 Universal Flash Storage (UFS). UFS 981 in one embodiment includes an interconnect that adapts to low power computer power platforms, such as mobile systems. As an example, it provides a transfer rate between 200 and 500 MV / s (for example, 300 MV / s), using queuing features to increase random read-write speeds. In one implementation, UFS 981 uses the MPHY physical layer and protocol layer, such as UniPro.

A 910 modem is often recommended for a modulator / demodulator. Modem 910 typically provides an interface for cellular communications. It uses its ability to transmit with different types of networks and different frequencies, depending on what communication standard is used. In one embodiment, both voice and data connections are supported. The modem 910 communicates with the host processor 905 using any known interconnect, such as one or more of the LLI, SSIC, UniPro, Mobile Express, etc.

In one embodiment, a control bus is used to communicate control or data interfaces, such as a wireless interface 935, speaker 940, microphone 945. An example of such a bus is SLIMbus, a flexible low-power multi-point interface capable of supporting a wide range of audio and control solutions. Other examples include PCM, I2S, I2C, SPI, and UART. Wireless communication interface 935 contains an interface such as an interface according to the short-range communication standard between two devices (e.g., Bluetooth or NFC), a navigation system capable of triangulating by position and / or time (e.g., GPS), a receiver for analog or radio broadcasts ( e.g. FM Radio) or another well-known wireless interface or standard. Loudspeaker (s) 940 comprise any device for creating sound, such as an electromechanical device, to form music for telephone calls or music. Numerous speakers can be used for stereo or multi-channel sound. Microphone 945 is often used for voice input, such as talking during a call.

The radio frequency integrated circuit (RFIC) 915 must perform analog processing, such as processing radio signals, for example, amplification, frequency conversion, filtering, and digital conversion. As shown in the drawing, RFIC 915 communicates with modem 910 via interface 912. In one embodiment, interface 912 comprises a bi-directional, high-speed interface (eg. DigRF) that supports communication standards such as LTE, 3GPP, EGPRS, UMTS, HSPA + , and TD-SCDMA. As a specific example, DigRF uses a frame-oriented protocol based on the M-PHY physical layer. DigRF is commonly referred to as RF-friendly, low-latency, low-power, with an optimized amount of output, which currently operates at speeds between 1.5 and 3 Gbps per route and can be performed with many routes, such as 4 routes.

The 961 interface (e.g., the RF control interface) contains a flexible bus to support simple and complex devices. As a specific example, the 961 interface contains a flexible two-wire serial bus for controlling RF Front-End components. One bus control device can write and read data to many devices, such as a power amplifier 950 for amplifying the power of the RF signal, sensors for receiving signals from the sensors, switch module (s) 960 for switching the path of the RF signal depending on the mode networks, and antenna tuner 965 to compensate for poor propagation conditions or improve bandwidth. Interface 961 in one embodiment has a batch trigger function for time critical events and low EMI.

Power management 920 is used to provide all of the various components in the mobile device 900 with a controlled voltage supply, such as decreasing voltage or increasing voltage, to increase the efficiency of the components in the mobile device. In one embodiment, it also controls and monitors the battery charge and remaining energy. A battery interface can be used between power management 920 and the battery. As an example, the battery interface contains a single-wire connection between the mobile terminal and smart / low-cost batteries.

In FIG. 10 is a block diagram of components existing in a computer system in accordance with an embodiment of the present invention. As shown in FIG. 10, system 1000 comprises any combination of components. These components may be implemented as integrated circuits (ICs), parts thereof, discrete electronic devices or other modules, logic, hardware, software, firmware or combinations thereof adapted in a computer system, or as components otherwise inserted inside chassis computer system. Note also that the block diagram shown in FIG. 10 is intended to show a top-level view of many components of a computer system. However, it should be understood that some of the components shown may be absent, additional components may be present, and in other implementations there may be a different arrangement of the components shown. As a result, the invention described above can be implemented on any site of one or more interconnects shown or described below.

As seen in FIG. 10, a processor 1010 in one embodiment comprises a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an integrated processor, or other known processing element. In the shown implementation, the processor 1010 acts as a main processing unit and a central hub for communication with many different components of the system 1000. As an example, the processor 1000 is implemented as a system on a chip (SoC). As a specific illustrative example, the processor 1010 comprises an Intel® Architecture Core ™ processor, such as i3, i5, i7, or another such processor, available from Intel Corporation, Santa Clara, California. However, it should be understood that in other embodiments, instead of processors such as the Apple A5 / A6 processor, Qualcomm Snapdragon processor, or TI OMAR processor, other low-voltage processors may be present, such as those available from Advanced Micro Devices, Inc. (AMD), Sunnyvale, Calif., MIPS-based project from MIPS Technologies, Inc. Sunnyvale, CA, an ARM-based project licensed from ARM Holdings, Ltd or its consumer. Note that many of the custom versions of such processors are modified and differentiated; however, they can support or recognize a set of specific commands that execute certain algorithms, as indicated by the processor licensor. Here, the microarchitectural implementation may vary, but the architectural function of the processor is usually compatible. Certain details regarding the architecture and operation of the processor 1010 in one implementation will be discussed further below to provide an illustrative example.

A processor 1010 in one embodiment communicates with system memory 1015. This is an illustrative example that, in an embodiment, may be implemented through multiple memory devices to provide a predetermined amount of system memory. By way of example, the memory may correspond to the Joint Electron Devices Engineering Council (JEDEC) Low Voltage, Dual Data Rate Design (LPDDR) Joint Design Council, current LPDDR2 standard according to JEDEC JESD 209-2E (published April 2009). ) or the next generation LPDDR standard, which will be referred to as LPDDR3 or LPDDR4 with LPDDR2 extensions to increase bandwidth. In various implementations, individual memory devices may have different types of packets, such as a single matrix packet (SDP), a dual matrix packet (DDP), or a quad matrix packet (Q17P). These devices, in some embodiments, are directly soldered to the system board to provide a lower profile solution, while in other embodiments, devices are configured as one or more memory modules that alternately communicate with the system board with this connector. And of course, other memory implementations are possible, such as other types of memory modules, for example, dual-row memory modules (DIMMs) of various options, including, in particular, microDIMM, MiniDIMM. In a specific illustrative embodiment, the memory size is from 2 GB to 16 GB, and can be performed as a DDR3LM or LPDDR2 package or LPDDR3 memory, which is soldered to the system board through a spherical grid matrix (BGA).

To ensure the permanent storage of information, such as data, applications, one or more operating systems, etc., the mass storage device 1020 may also be coupled to the processor 1010. In various embodiments, to provide a thinner and lighter system design, and Also increase the sensitivity of the system, this mass storage device can be realized through SSD. However, in other embodiments, the mass storage device can be implemented primarily by using a small SSD hard drive (HDD) to act as an SSD cache allowing long-term storage of context status and other such information during a shutdown event power supply, so that when you turn it back on, the system can quickly turn on. Also, as shown in FIG. 10, the flash memory device 1022 may be coupled to the processor 1010, for example, via a serial peripheral interface (SPI). This flash device can provide long-term storage of system software, including basic input / output software (BIOS), as well as other system firmware.

In various embodiments, large capacity system storage is implemented with only one SSD, or as a disk, optical, or other disk with an SSD cache. In some embodiments, the mass storage device is implemented as an SSD or as an HDD along with a recovery cache module (RST). In various implementations, the HDD provides storage storage capacity of 320 GV - 4 TB and higher, while the RST cache is implemented with an SSD having a capacity of 24 GB - 256 GB. Note that such an SSD cache may be implemented as a single-level cache (SLC) or a multi-level cache (MLC) option to provide an appropriate level of sensitivity. In the option with SSD only, the module can be placed in various places, such as in mSATA or the NGFF slot. As an example, an SSD has a capacity ranging from 120 GB - 1 TB.

Within the system 1000, various input / output (I / O) devices may be present. In the embodiment of FIG. 10, a display 1024 is specifically shown, which may be a high-definition liquid crystal display or an LED panel (LED) formed within a portion of the chassis cover. This display panel may also provide a touch screen 1025, for example, made over the display panel so that through user interaction with this touch screen, user input for the system can be provided to allow desired operations, for example, in relation to displaying information, accessing information etc. In one embodiment, the display 1024 may be coupled to the processor 1010 via a display interconnect, which may be implemented as a high-performance graphical interconnect. The touch screen 1025 may be connected to the processor 1010 through another interconnect, which in an embodiment may be an I2C interconnect. As further shown in FIG. 10, in addition to the touch screen 1025, user input can also be made by touching the touch panel 1030, which can be made inside the chassis and can also be connected to the same I2C interconnect as the touch screen 1025.

In various embodiments, the display may have different screen sizes, for example, 11.6 inches or 13.3 inches, and may have a 16: 9 format and at least 300 nits of brightness. Also, the display can have a resolution of full high definition (HD) (at least 1920 × 1080 pixels), be compatible with the built-in display port (eDP), and be a low energy panel with a self-updating panel.

Regarding the capabilities of the touch screen, the system can provide a multi-touch display panel with multi-touch ability and designed for at least 5 fingers. And in some embodiments, the display may be suitable for 10 fingers. In one embodiment, the touch screen is located inside a glass protected from damage and scratches and has a coating (for example, Gorilla GlassTM or Gorilla Glass 2TM) for low friction to reduce finger burning and avoid finger skipping. To provide improved touch feeling and sensitivity, the touch panel, in some implementations, has multi-touch functionality, such as less than 2 frames (30 Hz) for static viewing during zooming, and one-touch functionality with less than 1 cm per frame (30 Hz) for 200 ms (delay on the finger to the pointer). The display in some implementations supports glass at the edges with minimal skew of the screen, which is also flush with the surface of the panel, and limited I / O interference when using multi-touch.

For the purposes of perceptual computing and other purposes, various sensors may be present in the system, which may be coupled to the processor 1010 in various ways. Certain inertial sensors and medium sensors can communicate with the processor 1010 through a sensor concentrator 1040, for example, through an I2C interconnect. In the embodiment shown in FIG. 10, these sensors may comprise an accelerometer 1041, an ambient light sensor (ALS) 1042, a compass 1043, and a gyroscope 1044. Other environmental sensors may include one or more temperature sensors 1046, which in some embodiments are coupled to a processor 1010 via a system control bus ( SMBus).

For example, with regard to power management / life expectancy problems, based on at least a portion of the information from the ambient light sensor, the ambient light conditions at the platform location are determined and, accordingly, the display luminance intensity is controlled. Thus, the energy consumed by the display, in certain lighting conditions is reduced.

In an embodiment, the operating system (OS) may be a Microsoft® Windows® 8 operating system that implements the Connected Standby function (also referred to as Win8 CS here). Connected Standby Windows 8 or another operating system with a similar state can provide, in the platform, as described here, very low power inactive to allow applications to remain connected, for example, to a cloud-based location, at very low power consumption. The platform can support 3 power states, namely, the screen is on (normal); Connected Standby (as the default value is “off”); and shutdown (zero power consumption). Thus, in the Connected Standby state, the platform is logically turned on (with a minimum level of power consumption) even though the screen is off. In such a platform, power management can be made transparent to applications and maintain constant communication, in particular thanks to unloading technology, to allow the component with the lowest energy consumption to work.

Also in FIG. 10, it can be seen that various peripheral devices can communicate with the processor 1010 via a low pin count (LPC) interconnect. In the embodiment shown, various components may communicate via an integrated controller 1035. Such components may include a keyboard 1036 (eg, connected via a PS2 interface), a fan 1037, and a temperature sensor 1039. In some embodiments, the touch panel 1030 may also communicate with the EU 1035 through an interface PS2. In addition, a security processor such as the Proven Platform Module (TPM) 1038 in accordance with version 1.2 of the TPM specification Trusted Computing Group (TCG), dated October 2, 2003, can also communicate with processor 1010 through this LPC interconnect. However, it should be understood that the scope of the present invention is not limited in this regard, and safe processing and storage of secure information can be carried out in another secure place, such as static random access memory (SRAM) in the security coprocessor, or as encrypted data blobs that are decrypted, only when protected by safe power on (SE) of the processor.

In a particular implementation, the peripheral ports may comprise a high definition media interface (HDMI) connector (which may have other form factors such as full size, mini or micro); one or more USB ports, such as full-size external ports in accordance with the Universal Serial Bus Revision 3.0 Specification version 3.0 specification, (November 2008, of which at least one supplies power to charge USB devices (such as smartphones) when the system is in a Connected Standby state and is plugged into an AC wall outlet, and one or more ThunderboltTM ports may be provided. Other ports may contain an externally accessible card reader such as full-face SDXC punch card reader and / or WW AN SIM card reader (for example, an 8-pin punch card reader). For audio, there may be a 3.5 mm jack with stereo speaker and microphone (for example, combinational functionality) , with support for connector detection (for example, headphones only support a microphone embedded in the cover, or headphones with a microphone in the cable). In some embodiments, the implementation of this connector may be with switching tasks between stereo headphones and input from a stereo microphone. In addition, a power connector may be provided for communication with an AC adapter.

System 1000 can communicate with external devices in a variety of ways, including wireless. In the embodiment shown in FIG. 10, various wireless modules are present, each of which may correspond to a radio module configured to communicate over a particular wireless communication protocol. One short-range radio communication method, such as near field communication, may be via a near field communication unit (NFC) 1045, which may, in one embodiment, communicate with processor 1010 via SMBus. Note that through this NFC unit 1045, devices located in close proximity to each other can communicate. For example, a user may allow the system 1000 to communicate with another (e.g.) mobile device, such as a user's smartphone, adapting the two devices together in close connection and allowing information such as identification information, payment information, data such as image data, and so on to be transmitted. farther. Wireless power transmission can also be performed using an NFC system.

Using the NFC box described here, users can push devices together and place devices next to each other for near field communication functions (such as near field communication and wireless power transmission (WPT)), enhancing the connection between the windings of one or more such devices . More specifically, the embodiments provide devices strategically shaped and positioned having ferrite materials to provide better coil coils. Each coil has an inductance associated with it, which can be selected in combination with resistive, capacitive, and other features of the system to select the total resonant frequency for the system.

As further seen in FIG. 10, additional wireless units may comprise other short-range wireless communication mechanisms, including a WLAN unit 1050 and a Bluetooth unit 1052. Using the 1050 WLAN 1050 unit, Wi-Fi ™ communications can be implemented in accordance with the IEEE 802.11 Institute of Electronics and Radio Engineering (IEEE) standard, while short-range communications can be made via the Bluetooth module 1052 via Bluetooth. These units can communicate with the processor 1010, for example, via a USB communication channel or a universal asynchronous transceiver (UART) communication channel. Or, these units can communicate with the 1010 processor through an interconnect according to the Peripheral Component Interconnect Express ™ (PCIe ™) protocol, for example according to PCI ExpressTM Specification Base Specification version 3.0 (published January 17, 2007), or another such protocol, such as serial input / output standard (SDIO). Of course, the actual physical connection between these peripheral devices, which can be made using one or more expansion cards, can adapt to the system board using NGFF connectors.

In addition, messaging in the area of a broadband wireless zone, for example, in accordance with a cellular communication protocol or other wireless broadband area, can be done through a WWAN unit 1506, which in turn can communicate with a Subscriber Identity Module (SIM) 1057. In addition, to enable the reception and use of location information, a GPS module 1955 may also be present. Note that in the embodiment shown in FIG. 10, WWAN unit 1056 and an integrated receiving device, such as a camera module 1054, can transmit via this USB protocol, such as USB 2.0 or 3.0, a communication channel, or an I2C or UART protocol. And again, the actual physical connection of these blocks can be done by adapting the NGFF expansion board to the NGFF connector made on the system board.

In a particular embodiment, wireless functionality may provide modality, for example, with a WiFiTM 80211ac solution (for example, an expansion board that is backward compatible with IEEE 802.11labgn) with support for Windows CS8. This card can be configured in the internal slot (for example, through the NGFF adapter). The add-on module can provide Bluetooth capabilities (such as Bluetooth 4.0 backward compatible) as well as Intel® Wireless Display functionality. In addition, NFC support can be provided through a separate device or multifunction device and can be located, for example, on the front right side of the chassis for ease of access. Another optional module may be a WWAN device, which can provide support for 3G / 4G / LTE and GPS. This module can be implemented in the internal slot (for example, NGFF). Integrated antenna support can be provided by WiFi ™, Bluetooth, WWAN, NFC and GPS, enabling seamless transition from WiFi ™ to WWAN for the radio channel, transfer of wireless gigabytes (WiGig) in accordance with the Wireless Gigabit Specification (July 2010) and vice versa .

To provide audio inputs and outputs, the audio processor may be implemented by a digital signal processor (DSP) 1060, which may be coupled to the processor 1010 via a high resolution audio channel (HDA). Similarly, the DSP 1060 can communicate with an integrated encoder / decoder (CODEC) and amplifier 1062, which, in turn, can communicate with output speakers 1063, which can be implemented within the chassis. Similarly, an amplifier and CODEC 1062 can be coupled to receive audio input from a microphone 1065, which in an embodiment can be implemented through a dual array of microphones (such as a matrix of digital microphones) to provide high-quality audio inputs that allow voice activation control of various operations within the system. Note also that audio outputs can be provided from an amplifier / CODEC 1062 to a headphone jack 1064. Although in FIG. 10 shows an embodiment with these specific components, it should be understood that the scope of the present invention is not limited in this regard.

In some embodiments, the processor 1010 may receive power from an external voltage stabilizer (VR) and numerous internal voltage stabilizers that integrate within the processor matrix are referred to as fully integrated voltage stabilizers (FIVRs). The use of multiple FIVRs in a processor comprises grouping components on separate power planes, so that power is regulated and FIVR is applied only to these components in the group. During power management for a given plane, the power of one FIVR can turn off or off when the processor is placed in a certain low-voltage power state, while the other power plane of the other FIVR remains active or is receiving full power.

In one embodiment, holding the power plane can be used during some deep sleep states to turn on the I / O pins for several I / O signals, such as the interface between the processor and the PCH, an interface with external VR, and an interface with the EU 1035. holding the power plane, power is also supplied to the matrix voltage stabilizer, which supports the built-in SRAM or other cache memory, which stores the processor context during sleep. Power plane holding is also used to power the processor wake-up logic, which monitors and processes the various wake-up source signals.

During power management, although other power planes are turned off or off when the processor enters certain sleep states, holding the power planes remains on to support the components mentioned above. However, this can lead to unnecessary energy consumption or dissipation when these components are not required. To this end, embodiments may provide a connected sleep state in order to maintain a processor context using a dedicated power plane. In one embodiment, the connected sleep state facilitates waking up the processor using PCN resources, which in themselves may be present in a packet with the processor. In one embodiment, the connected sleep state makes it easier for the processor to maintain architectural functions in the PCN until the processor wakes up, this allows you to disable all unnecessary processor components that previously remained on during deep sleep states, including turning off all hours. In one embodiment, the PCN comprises a time stamp counter (TSC) and attached standby logic to control the system during an attached standby state. An integrated voltage regulator to hold the power plane can also be located on the PCH.

In an embodiment, during the connected standby state, the integrated voltage regulator can function as a dedicated power plane that remains on to maintain a dedicated cache in which the processor context is stored, such as critical state variables when the processor enters a deep sleep state, and connected standby state. This critical state may contain state variables associated with the architectural, microarchitectural, debug state and / or similar state variables associated with the processor.

Initial wake-up signals from the EU 1035 can be sent to the PCN instead of the processor during the connected standby state so that the PCN can control the wake-up processing instead of the processor. In addition, the TSC is stored in the PCN to facilitate the maintenance of the processor's architectural features. Although the embodiment of FIG. 10 is shown with these specific components, it should be understood that the scope of the present invention is not limited in this regard.

Power management in the processor can lead to increased energy savings. For example, energy can be dynamically distributed between cores, individual cores can change frequency / voltage, and numerous deep low-power states can be provided to allow the lowest energy consumption. In addition, the dynamic control of cores or independent parts of the core can provide reduced energy consumption by turning off components when not in use.

Some implementations may provide microchips (ICs) for specific power management (PMICs) to control the platform power. Using this solution, the system can see a very low (for example, less than 5%) battery deterioration with an extended duration (for example, 16 hours) when it is in a given standby state, such as when it is in the Win8 Connected Standby state. In the Win8 standby state, battery life can be realized, exceeding, for example, 9 hours (for example, at 150 nits). As for video playback, a long battery life can be realized, for example, video playback at full HD can take at least 6 hours. A platform with one implementation can have an energy reserve of, for example, 35 Watt-hours (Wh) for CS Win8 using an SSD and (for example) 40-44 Wh for CS Win8 using an HDD with an RST cache configuration.

In various implementations, a security module, such as TPM, may be integrated into the processor or may be a discrete device, such as a TPM 2.0 device. With an integrated security module, also referred to as Platform Trust Technology (PTT), BIOS / firmware (PTT), BIOS / firmware, you can enable certain hardware features of certain security features, including safety instructions, secure boot, technology Intel® Anti-Theft Technology, Intel® Identity Protection Technology, Intel® Trusted Execution Technology (TXT), and Intel® Intel® Manageability Engine Technology along with secure user interfaces such as a secure keyboard and display.

The components, features, and details described for any of FIG. 4 and 5 may also be additionally used in any of FIGS. 1, 2 or 3. In addition, the components, features and details described herein for any device can also, if desired, be used in any of the methods described here that, in embodiments, can be implemented with such a device / or with it.

The following examples relate to further embodiments. Specific features in the examples may be used anywhere in one or more embodiments.

Example 1 is a device with an interconnect architecture that contains a processor for generating a transaction incompatible with LLI (or alternatively refers to a different interconnect protocol other than LLI. The device also contains conversion logic associated with the processor, conversion logic for transforming the transaction, not compatible with LLI (or alternatively has a different interconnect protocol than LLI) in the LLI packet.The device also contains an LLI controller associated with the conversion logic, an LLI controller for communication trinity with the architecture of the interconnects with the LLI communication channel, the LLI controller for transmitting a symbol corresponding to the LLI packet on the LLI communication channel.

Example 2 contains the subject matter of the invention, as corresponding to Example 1, in which the conversion logic contains logic for transforming a transaction selected from a Peripheral Component Interconnect (PCI) transaction, a Peripheral Component Interconnect Express (PCIE) transaction and a Peripheral Component Interconnect extended (PCI- X), in LLL package

Example 3 contains an object of the invention, as an option corresponding to example 1, in which a transaction should be used to at least enumerate or configure a device with an interconnect architecture that should be associated with the LLI communication channel.

Example 4 contains the subject matter of the invention, as an option corresponding to example 1, in which a transaction is selected from a PCI configuration transaction and a PCIE configuration transaction, and in which the conversion logic is to convert the configuration transaction into an LLI service package.

Example 5 contains the subject of the invention, as an option corresponding to example 1, in which a transaction is selected from a transaction with mapped PCI memory and a transaction with mapped PCIE memory, and in which the conversion logic should convert the mapped transaction into an LLI transaction packet.

Example 6 contains the subject of the invention, as an option, corresponding to example 1, in which the conversion logic should provide the conversion of the LLI packet to the transaction level of the LLI stack of the LLI controller.

Example 7 contains the subject of the invention according to any one of examples 1-6, as an embodiment, comprising a memory associated with a processor, a module stored in memory. The module is selected from among the enumeration module and the configuration module. The module is compatible with a transaction (or, alternatively, a non-LLI interconnect protocol). The processor must form a transaction in response to the execution of one or more instructions of the module.

Example 8 contains the subject of the invention according to any one of examples 1-6, in which, as an option, the device with the interconnect architecture does not have an interconnect corresponding to the interconnect protocol that corresponds to the transaction (or, alternatively, has a different interconnect protocol other than the LLI).

Example 9 is an interconnect architecture device comprising an LLI controller, an LLI controller for communicating a device with an interconnect architecture with an LLI communication channel, an LLI controller for receiving a symbol over an LLI communication channel. The device also contains conversion logic associated with the LLI controller, conversion logic for converting the LLI packet corresponding to the received symbol to a transaction not compatible with the LLI (or, alternatively, which has a different interconnection protocol than the LLI). The device also contains interconnect protocol logic that is compatible with the transaction (or, alternatively, that has a different interconnect protocol other than LLI), along with translation logic to service the transaction.

Example 10 contains the subject of the invention corresponding to example 9, in which, alternatively, the conversion logic contains logic for converting the LLI packet into a transaction selected from among a PCI transaction, a PCIE transaction, and a PCI-X transaction.

Example 11 contains an object of the invention corresponding to example 9, in which, as an option, the logic that is compatible with the transaction (or, alternatively, which has a non-LLI interconnect protocol) contains PCI endpoint logic or PCIE endpoint logic.

Example 12 contains an object of the invention corresponding to example 9, in which, as an option, the logic that is compatible with the transaction (or, alternatively, which has an interconnect protocol other than LLI) contains the integrated endpoint logic of the root complex.

Example 13 contains an object of the invention corresponding to example 9, in which, alternatively, the transaction should be used to at least configure a device with an interconnect architecture and rank the device with an interconnect architecture as a device with an interconnect architecture that should be connected to the LLI communication channel.

Example 14 contains an object of the invention corresponding to example 9, in which, as an option, the LLI packet contains the LLI service packet, and in which the conversion logic must convert the LLI service packet into a PCI configuration transaction or a PCIE configuration transaction.

Example 15 contains an inventive subject to Example 9, in which, as an option, the LLI packet contains an LLI transaction packet, and in which the conversion logic must convert the LLI transaction packet to a memory-mapped PCI transaction or a memory-mapped PCIE transaction.

Example 16 contains a subject matter according to any one of examples 9-15, in which, alternatively, the transformation logic must receive the LLI packet from the transaction level of the LLI stack of the LLI controller, and in which the transaction-compatible logic (or, alternatively, which has a protocol non-LLI) is not associated with an interconnect that uses the interconnect protocol,

Example 17 is a method in a device with an interconnect architecture, which comprises generating a transaction having a different interconnect protocol other than LLI within the device with an interconnect architecture. The method also includes converting a transaction that has a different interconnect protocol than the LLI to an LLI packet. The method further comprises transmitting a symbol corresponding to the LLI packet over the LLI communication channel.

Example 18 contains an inventive subject to example 17, wherein, alternatively, the conversion comprises converting one of such transactions, as a PCI transaction, a PCIE transaction, or a PCI-X transaction, to an LLI packet.

Example 19 contains the subject of the invention according to any one of examples 17-18, wherein, as an option, the formation comprises the formation of a transaction as part of at least an enumeration or configuration of a device with the architecture of interconnects associated with the LLI communication channel.

Example 20 is a method in a device with an interconnect architecture that comprises receiving a symbol over an LLI link of a device with an interconnect architecture. The method also comprises converting the LLI packet obtained from the received symbol into a transaction having a different interconnect protocol other than the LLI. The method also includes a transaction service that has a different interconnect protocol than the LLI.

Example 21 contains an object of the invention corresponding to example 20, in which, as an option, the conversion comprises converting an LLI packet into a PCI-based transaction, and in which the service comprises servicing a transaction with protocol-based PCI endpoint logic.

Example 22 contains the subject of the invention according to any one of examples 20-21, as an option comprising at least configuring a device with an interconnect architecture and listing the device with an interconnect architecture into a device with an interconnect architecture based on transaction service.

In Example 23, the system comprises a battery, a dipole antenna, a memory to store a PCI-based protocol module, an LLI communication channel, and an interconnect architecture device together with an LLI communication channel. The interconnect architecture device contains translation logic to convert LLI packets that must be received from the LLI stack, which must communicate with the LLI transmission channel, into PCI-based transactions.

Example 24 contains an object of the invention corresponding to example 23, in which, alternatively, PCI-based transactions must contain at least one of the transactions in order to list a device with interconnect architecture and transactions for configuring a transaction architecture device.

Example 25 contains the subject of the invention according to any one of examples 23-24, as an embodiment containing PCI-based logic associated with the conversion logic in order to receive transactions from the conversion logic. PCI-based logic is not connected to any other PCI-based logic.

Example 26 includes a device for executing memory-mapped transactions containing an integrated circuit. The integrated circuit contains a processor element for forming a memory-mapped transaction, which must be compatible with the standard protocol Peripheral Interconnect Component Express (PCIe). The integrated circuit contains conversion logic for converting a PCIe transaction displayed in memory into a converted packet compatible with another protocol standard. The integrated circuit contains a mobile physical layer (MPHY) compatible with the MIPI standard to transmit the converted packet over the communication channel.

Example 27 is an interconnect architecture device comprising a transaction generator that has a different interconnect protocol than the LLI. The device also comprises conversion means associated with the generation means, conversion means for converting a transaction that has a different interconnection protocol than the LLI into an LLI packet. The device also comprises transmission means associated with the conversion means, transmission means for transmitting a symbol corresponding to the LLI packet over the LLI communication channel.

Example 28 is an interconnect architecture device comprising LLI communication channel communication means for associating an interconnect architecture device with an LLI communication channel and receiving a symbol over an LLI communication channel. The device also comprises conversion means associated with the LLI communication channel, conversion means for converting the LLI packet received from the symbol into a transaction that has a different interconnection protocol than the LLI. The device also includes a service tool that has an interconnect protocol other than LLI and that communicates with a communication tool to service the transaction.

Example 29 contains a device for performing the method according to any one of paragraphs. 17-19.

Example 30 contains a device containing means for performing the method according to any one of paragraphs. 17-19.

Example 31 contains a system comprising a memory, a battery and a wireless modem, that is, a system for performing the method according to any one of claims. 17-19.

Example 32 contains a device for performing the method according to any one of paragraphs. 20-22.

Example 33 contains a device containing means for performing the method according to any one of paragraphs. 20-22.

Example 34 comprises a system comprising a memory, a battery and a wireless modem, a system for performing the method according to any one of claims. 20-22.

Example 35 comprises an apparatus for performing a method essentially as described herein.

Example 36 comprises an apparatus, comprises means for performing a method essentially as described herein.

The terms “coupled” and “connected”, together with their derivatives, could be used in the description and claims. It should be understood that these terms are not intended to be synonymous with each other. Rather, in specific embodiments, “connected” can be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Connected” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but are still collaborating or interacting with each other. For example, a processor may be coupled to a PCIE-LLI conversion module through an intermediate interconnect and / or one or more other components. In the drawings, arrows are used to show connections and connections.

The term “logic” could be used in the description and claims. As used here, the logic may include hardware, firmware, software, or a combination thereof. Examples of logic are integrated circuits, specialized integrated circuits, analog circuits, digital circuits, programmable logic devices, memory devices containing commands, etc. In some embodiments, the hardware logic may comprise transistors and / or logic elements potentially together with other components of the circuitry.

The term "and / or" may be used. As used here, the term "and / or" means one or the other or and (for example, A and B means A or B or both A and B).

In the above description, for purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of embodiments of the invention. It will be apparent to those skilled in the art that one or more other embodiments may be practiced without some of these specific details. The specific embodiments described are not intended to limit the invention, but to explain it through the embodiments presented as an example. The scope of the invention should not be determined by specific examples, but only by the claims. In other cases, well-known circuits, structures, devices and operations are shown in the form of a block diagram or without details, in order to avoid details that impede the understanding of the description.

If deemed appropriate, the reference position or terminal portion of the position of the reference position is repeated in the drawings to indicate corresponding or similar elements that may further have similar or the same characteristics, unless specifically or clearly defined otherwise. In some cases, when numerous components have been described, they can be incorporated into a single component. In other cases where a single component is described, it can be divided into multiple components.

Various operations and methods have been described. Some of the methods have been described in a relatively basic form in the form of flowcharts, but, as an option, operations can be added to or removed from the methods. In addition, although the flowcharts illustrate, by way of example, a specific order of operations corresponding to the embodiments, such a specific order remains exemplary. Alternative embodiments may additionally perform operations in a different order, combine certain operations, overlap certain operations, etc.

Some embodiments comprise manufacturing products (eg, a computer program product) that comprises a computer-readable medium. The medium may contain a mechanism that provides, for example, the storage of information in a form readable by a machine. A computer-readable medium can provide or store on it one or more or a sequence of instructions that, if and / or when executed by a machine, causes the machine to execute and / or result in the machine performing the operations, methods or technologies disclosed herein. In some embodiments, a computer-readable medium may comprise tangible and / or non-transferable computer-readable media. For example, tangible non-transferable machine-readable media may include a floppy disk, optical media, optical disk, CD-ROM, magnetic disk, magneto-optical disk, read-only memory (ROM), programmable ROM (PROM), erasable and programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), flash memory, phase-change memory, etc. A material medium may contain one or more solid-state or material physical materials for storing data, such as, for example, a semiconductor material, a material, a material with easy transition from one phase to another, etc. A storage medium does not consist of a transient propagating signal, such as carrier waves, infrared signals, digital signals, etc. In some embodiments, the carrier is non-volatile

Examples of suitable machines are, in particular, desktop computers, portable personal computers, laptops, netbooks, tablets, smartphones, cell phones, Mobile Internet Devices (MID), mobile wireless devices, mobile terminals, battery powered electronic devices, media players, and other computing or electronic devices having one or more processors. Such electronic devices typically comprise one or more processors associated with one or more other components, such as one or more non-transferable computer-readable media, user input / output devices (e.g., keyboard, touch screen, and / or display). Communication between processors and other components is typically done through one or more buses and bridges (also called controller buses).

It should also be understood that throughout this description, reference to “one embodiment”, “embodiment”, or “one or more embodiments”, for example, means that a particular function may be put into practice using the invention. In the same way, it should be understood that in the description various features are sometimes grouped into a single embodiment, a drawing or its description in order to optimize the disclosure and help in understanding the various variants of the invention. This disclosure method, however, should not be interpreted as a reflection of the intention that the invention requires more features than are explicitly indicated in each claim. Rather, as reflected in the following claims, embodiments of the invention may belong to less than all the features of the only disclosed embodiment. Thus, the claims corresponding to the detailed description herein are explicitly contained in this detailed description, with each claim standing independently as a separate embodiment of the invention.

Claims (44)

1. An LLI master with an interconnect architecture, comprising: a processor for generating a transaction that is not compatible with LLI; conversion logic associated with the processor for converting an incompatible LLI transaction into an LLI packet; and an LLI controller associated with the conversion logic, wherein the LLI controller is for connecting the device with the interconnect architecture to the LLI communication channel, and the LLI controller is for transmitting the symbol corresponding to the LLI packet over the LLI channel in which the transaction is selected from the PCI configuration transaction and the transaction PCIE configuration, and in which the conversion logic must convert the configuration transaction into an LLI service package. 2. The device according to claim 1, in which the conversion logic contains logic for converting a transaction selected from a Peripheral Component Interconnect (PCI) transaction, a Peripheral Component Interconnect Express (PCIE) transaction and a Peripheral Component Interconnect extended (PCI-X) transaction into a package LLI 3. The device according to claim 1, in which the transaction should be used at least to list or configure the device that should communicate with the LLI communication channel. 4. The device according to claim 1, wherein the transaction is selected from a PCI transaction displayed in memory and a PCIE displayed in memory, and in which the conversion logic must convert the memory displayed transaction into an LLI transaction packet. 5. The device according to claim 1, in which the conversion logic must provide the conversion of the LLI packet to the transaction level of the LLI stack of the LLI controller. 6. The device of claim 1, further comprising: memory associated with the processor; and a module stored in memory, the module being selected from an enumeration module or a configuration module, an interconnect protocol module other than LLI, and in which the processor is configured to generate a transaction in response to the execution of one or more instructions of the module. 7. The device according to claim 1, wherein the device with the interconnect architecture does not have an interconnect confirming the interconnect protocol that the transaction is compatible with the LLI. 8. An LLI slave with interconnect architecture, comprising: LLI controller, while the LLI controller is designed to communicate the device with the interconnect architecture with the LLI communication channel, and the LLI controller is designed to receive a character on the LLI communication channel; conversion logic associated with the LLI controller, wherein the conversion logic is intended to convert the LLI packet corresponding to the received symbol into a transaction not compatible with the LLI; and transaction compatible interconnect protocol logic associated with the transformation logic for servicing a transaction in which the transaction logic of the transaction interconnect protocol is not connected to an interconnect that uses the interconnect protocol. 9. The device of claim 8, wherein the conversion logic comprises logic for converting the LLI packet to a transaction selected from among a PCI transaction, a PCIE transaction, and a PCI-X transaction. 10. The device according to claim 8, in which the logic, which is the logic of the interconnect protocol that is compatible with the transaction, contains the logic of the PCI endpoint or the logic of the PCIE endpoint. 11. The device according to claim 10, in which the logic, which is the logic of the interconnect protocol compatible with the transaction, contains the integrated endpoint logic of the root complex. 12. The device according to claim 8, in which the transaction should be used at least to configure a device with an interconnect architecture or transfer a device with an interconnect architecture to a device with an interconnect architecture that should be connected to the LLI communication channel. 13. The device according to claim 8, in which the LLI packet contains the LLI service packet, and in which the conversion logic must convert the LLI service packet into a PCI configuration transaction or PCIE configuration transaction. 14. The device of claim 8, wherein the LLI packet contains an LLI transaction packet, and in which the conversion logic is to convert the LLI transaction packet into a memory-mapped PCI transaction or a memory-mapped PCIE transaction. 15. An LLI slave with interconnect architecture, comprising: LLI controller, LLI controller to associate the device with the interconnect architecture over the LLI communication channel, LLI controller to receive a symbol on the LLI communication channel; conversion logic associated with the LLI controller, conversion logic to convert the LLI packet corresponding to the received symbol into a transaction not compatible with LLI; and transaction-compatible interconnection protocol logic associated with the transformation logic for servicing a transaction in which the transformation logic must receive an LLI packet from the transaction level of the LLI LLI controller stack, and in which the logic, which is transaction-compatible interconnection protocol logic, is not associated with interconnect that uses the interconnect protocol. 16. A method of implementing a transaction in a device with an interconnect architecture, comprising the steps of: form a transaction according to a different interconnect protocol other than LLI, inside a device with an interconnect architecture; converting a transaction corresponding to a different interconnect protocol other than LLI into an LLI packet; and the symbol corresponding to the LLI packet is transmitted over the LLI communication channel in which the transaction is selected from the PCI configuration transaction and the PCIE configuration transaction, and in which the conversion logic converts the configuration transaction into the LLI service packet. 17. The method of claim 16, wherein the conversion comprises converting one of such transactions as: a PCI transaction, a PCIE transaction, or a PCI-X transaction, to an LLI packet. 18. The method of claim 16, wherein the generation comprises the step of forming a transaction as part of at least the enumeration or configuration of the interconnect architecture device associated with the LLI communication channel. 19. A system for carrying out a transaction, comprising: a battery; dipole antenna; memory to store a PCI-based protocol module; LLI communication channel; an interconnect architecture device comprising an LLI controller for communicating a device with an interconnect architecture with an LLI communication channel, and an LLI controller for receiving a symbol over an LLI communication channel; conversion logic associated with the LLI controller, wherein the conversion logic is intended to convert the LLI packet corresponding to the received symbol into a transaction not compatible with the LLI; and transaction compatible interconnect protocol logic associated with the transformation logic for servicing a transaction in which the transaction logic of the transaction interconnect protocol is not connected to an interconnect that uses the interconnect protocol. 20. The system of claim 19, wherein the PCI-based transaction must contain at least a transaction for transferring a device from an interconnect architecture or a transaction for configuring a device with an interconnect architecture. 21. The system of claim 19, wherein the PCI-based protocol comprises PCI. 22. The system of claim 19, wherein the PCI-based protocol comprises a PCIE.

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