RU2625527C1 - Exciter for radio transmitters - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: exciter for radio transmitters includes a control unit, a signal conditioning unit, an amplifier and a selector. The control unit is implemented in the form of a computational module (CM) comprising a central processing unit (CPU) and a programmable logic integrated circuit (PLIC CM), the signal conditioning unit is implemented as a radio frequency (RF) module containing a PLIC RFM, a clock generator, a reference oscillator (RO), an analog-to-digital converter (ADC), a digital boost converter (DBC), three low-pass filters (LPF), a selector contains input and output switches, four bandpass filters and a control status signal sensor of the radio transmitting device units, wherein the interface module comprises a microcontroller, a codec and two level converters.

EFFECT: expanding the functionality by providing remote control from external devices and local control by the parameters of the signals generated by the blocks entering the exciter for radio transmitters, providing radio communication, providing the nominal signal level at the output while reducing the level of distortion and interference.

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Description

The invention relates to radio communications technology and can be used in transmitting equipment for telegraph and telephone communication lines for various purposes, in particular in HF-VHF radio communication lines.

Known dual-ring digital frequency synthesizer (DSC) with frequency modulation (FM) with the sequential inclusion of rings, built on the basis of a pulse-phase-locked loop (IFAP) with a frequency divider with a variable division ratio (DPC) in the feedback circuit of each ring (see certificate Utility Model No. 30043 of 08/26/2002).

In this DSC, the first IFAPC ring is narrow-band, operates at the same frequency as the FM output signal, which is the reference for the second ring. The second IFAPCH ring (output) is connected in series with the first and is wide-range, high-speed (due to the use of fractional DPKD), and can operate at ultra-high frequencies. The modulating signal for the second ring is contained in its reference signal from the output of a controlled generator (UG) of the first ring.

In this DSS with FM, the functions of frequency formation and modulation are divided between the first and second IFAPH rings, which reduces the known contradictions. Two-point frequency modulation is carried out in the first ring operating at one fixed frequency, and wide-range frequency tuning and speed when switching frequencies in the second IFAPC ring.

A disadvantage of the known device is that it is currently impossible to implement point-to-point modulation by introducing an FM in the UG and at the modulating input of a phase modulator connected between the frequency divider and the input of the frequency-phase detector (ChFD), since there is no separate accessible input to the ChFD in the produced DSC chips (everything is inside the “crystal” of the DSC chip). In addition, this synthesizer lacks the purity of the spectrum of the output signal.

Closest to the proposed device is a pathogen for radio transmitters [2], containing a series-connected shaper of parcels, a digital modulator and an amplifier-conversion unit, to the corresponding inputs of which are connected the outputs of the synthesizer, to the input of which is connected the first output of the control unit and the series-connected modulator unit and block filters. A linear input amplifier with automatic control of gain along the envelope, a discrete limitation block of the emitted spectrum, a synchronization block, a program block, a selector, two peak detectors, a comparison block and a cascade of automatically blocking the path when the input signal is lost, a cascade with peak voltage adjustment is introduced into the exciter and an output amplifier, the output of which is connected to the first additional input of the amplifier-conversion unit and the input of the first peak detector, in the output of which is connected to the first input of the comparison unit, the second input and output of which are connected respectively to the output of the second peak detector and the second additional input of the amplifier-converter unit, the output of which is connected to the first input of the selector, the second input and output of which are connected respectively to the output of the program unit and the input of the second peak detector, while the additional outputs of the synthesizer are connected to the first input of the modulator unit, the second input of the output amplifier and to the inputs of the sync block radonization, the outputs of which are connected to the synchronization inputs of the digital modulator and the discrete limitation block of the emitted spectrum, the input and output of which are connected respectively to the second output of the package former and the second input of the digital modulator, and the input of the software block is connected to the second output of the control unit and the third additional input of the amplifier converter unit, and the outputs of the input linear amplifier with automatic gain control over the envelope and the filter unit are connected respectively -retarded modulator to the second input unit and the automatic locking stage entry path when the input signal failure.

The disadvantage of the prototype device is the low functionality for providing automated radio communications.

The objective of the invention is the expansion of functionality by providing automated radio communications.

The problem is achieved in that in the exciter for radio transmitters containing a control unit, a signal conditioning unit, an amplifier and a selector, according to the invention, the control unit is made in the form of a computing module (VM) containing a central processing unit (CPU) and a programmable logic integrated circuit (FPGA VM ), the signal conditioning unit is made in the form of a radio frequency (RF) module containing an FPGA RFM, a clock driver, a reference generator (OG), an analog-to-digital converter (ADC), a digital boost the first converter (DPC), three low-pass filters (LPFs), the selector contains input and output switches, four band-pass filters and an RMS sensor, an interface module containing a microcontroller (MK), a codec and two level converters are additionally introduced into the excitation device the Ethernet 100 joint, through which control commands are received, is connected to the CPU, to which the USB port is also connected, the inputs and outputs of the CPU are connected to the FPGA VM, which is connected to the MK interface module, and also through the codec to the inputs of the TLF, through level converters (ПУ) - with the input “TLG Input” and the RS-422 output, while the MK of the interface module is connected to the local control interface (MU) (CAN) and to the “RPDU Control” input, as well as the MK output is connected to the FPGA FPM input, and the MK output is connected to the selector RMS sensor and, by control, to an amplifier, the output of which is connected to the input selector switch, the outputs of which are connected to four bandpass filters that are connected to the output switch, the output of which with the RMS sensor connected is the RF exciter output, while two inputs-outputs of FPGA VM control and data are connected to two FPGA RFM inputs / outputs, the input of which is connected to the ADC output, and the output - to the CPU input, the output of which is connected to the amplifier, and the three ADC inputs are connected to three low-pass filter outputs, the first of which is fed signals from the OK OK input, to the input of the second of which signals from the OK OK input are supplied, and to the input of the third of which the intermediate frequency (IF) signals are supplied, while the input of the RF signal generator of the clock is connected to the output of the reference generator, which for synchronization withexternal devices additional output to an external connector and external input.

The drawing shows a diagram of the proposed device containing a computing module 1 with a central processor 2 and a programmable logic integrated circuit 3. The signal conditioning unit is made in the form of a radio frequency module 4 containing FPGA RFM 5, a clock signal generator 6, a reference oscillator 7, an analog-to-digital converter 8, a digital boost converter 9, three low-pass filters 10, a selector 11 is made comprising input 12, output 13 switches, four band-pass filters 14 and a RMS sensor 15. V is exciting The second device, comprising an amplifier 16, is additionally introduced an interface module 17 containing a microcontroller 18, a codec 19, and two level converters 20.

The proposed device operates as follows.

The central processor 2 of the computing module 1 software implements:

- processing of the remote control protocol from external devices at the joints of Ethernet 100 and RS-422;

- processing of the control protocol from the local control panel (PMU) at the CAN interface;

- management of the components of the VU 1 and the blocks of the radio transmitting device (RPDU);

- collection of data on the condition and accidents of the components of VU 1 and RPDU;

- Signal generation algorithms in telephone and telegraph classes of radiation, in the mode of digital input and IF input 128 kHz.

Management and control subsystem

Remote control is carried out at the Ethernet 100 and RS-422 interfaces. The Ethernet interface 100 commands enter the CPU 2. The RS-422 interface commands through the level 20 converter in the interface module 18 to the FPGA 3 of the computing module 1, then to the CPU 2. In the opposite direction, the CPU 2 replies and the status messages of the VU 1 and RPDU.

Commands at the MU interface (CAN) are sent to the microcontroller 18 of the interface module 17, then they are transmitted to the FPGA VM 3 and then to the CPU 2. In the opposite direction, the responses are received from the CPU 2 and status messages from the VU 1 and RPDU.

The control commands for the VU 1 nodes and RPDU blocks from the CPU 2 are received in the FPGA VM 3. The FPGA VM 3 implements an interface converter that translates the CPU 2 commands:

- in MK 18 of the interface module 17;

- in FPGA RFM 5.

MK 18 interface module 17 on the instructions of the CPU 2 generates commands for controlling the RPDU blocks and issues to the joint MU (CAN). In the opposite direction are the responses of RPDU blocks and messages about their status.

MK 18 on the instructions of the CPU 2 generates control commands for the selector 11 and the amplifier 16. Turning on / off the amplifier 16 is performed on the line "Locking". The selection of the range of the selector 11 is performed on the control lines by switching the input 12 and output 13 of the switches.

FPGA FPM 7 generates ADC 10, DPC 11 and clock driver 8 tuning commands, and also collects information about the state of the devices of RF module 6. The state of RF module 6 is transmitted to CPU 2 through the return channel of the SPORT interface.

Indication of the main conditions of the VU 1 on the front panel is carried out by the indication module 17 along the control lines from the CPU 2.

The USB joint is used to replace the software CPU 2, FPGA VM 3, FPGA RFM 5 and MK 18, as well as for in-depth monitoring of the status of VU 1 and RPDU.

Subsystem for generating a radio frequency signal.

The formation of the radio frequency signal, the processing of input information signals and digital signal processing algorithms is synchronized by the clock signals generated in the RF module 4 on the basis of a highly stable reference oscillator 7. The clock signals from the shaper are fed 6 to the ADC 8, CPU 9 and FPGA RFM 5. FPGA RFM 5 broadcasts clock signals in the FPGA VM 3 and further to the CPU 2. For synchronization with external devices, the output of OG 7 to an external connector is provided. It also provides a mode of operation from the external input of exhaust gas 7.

The choice of the information input for the formation of the radio frequency signal depends on the installed operating mode of VU 1.

In the telephone mode, the information signal from the input through the codec 19 enters the FPGA VM 3 and is transmitted to the CPU 2. In the CPU 2, filtering, normalization of the telephone signal level and modulation in the established class of radiation are performed. The modulated signal is issued in the FPGA VM 3.

In the telegraph mode, the information signal from the TLG input through the PU 20 enters the FPGA VM 3, it converts the serial stream of samples and translates it to the CPU 2. In the CPU 2, the telegraph signal is regenerated and modulated in the specified radiation class. The modulated signal is issued in the FPGA VM 3.

In the digital input mode, the digital signal samples are sent to CPU 2 at the Ethernet 100 interface. CPU 2 without processing translates the digital signal into the FPGA VM 3.

In the input IF mode, an information signal at a frequency of 128 kHz through a low-pass filter 10, which reduces interference at the “mirrors” of the sampling frequency, is fed to the 3rd input of the multi-channel ADC 8. From the output of the ADC 8, the samples of the discrete signal are transmitted to the FPGA 5, where spectrum transfer to zero frequency and filtering with lower sampling frequency. The samples of the IF signal from the FPGA RFM 5 are transmitted to the FPGA VM 3, then transmitted to the CPU 2. In CPU 2, filtering and normalization of the IF signal level are performed.

In the mode of broadband or high-speed radio links, information from the Ethernet 1000 interface goes directly to the FPGA VM 3, where a modulated signal is generated.

In FPGA VM 3, the modulated signal from CPU 2 passes through a predistortion algorithm (to compensate for the nonlinearity of the RPDU amplifier). The signal from FPGA VM 3 is issued in FPGA RFM 5. In FPGA RFM 5 is performed:

- increasing the sampling frequency of the signal with a large signal-to-noise ratio;

- calculation of the average and peak level of the modulating signal for the ARN subsystem;

- correction of the signal level by the ARN algorithm.

Next, the signal is output to a digital boost converter 9.

In CPU 9, an increase in the sampling frequency, signal transfer to a reference radio frequency (1.5-80 MHz), and digital-to-analog conversion (DAC) are performed. The reference radio frequency of the CPU 9 corresponds to the set operating frequency of the VU 1 and is configured by commands from the CPU 2. The output level of the DAC is controlled by commands from the FPGA RF module 5 according to the algorithm of the AVR subsystem.

The radio frequency signal from the output of the DSP 9 is transmitted to an amplifier 16, which provides a nominal signal level at the output of the VU 1 taking into account the attenuation in the selector 11. By the commands of the control system, the amplifier 16 can be locked to ensure a low noise level in the absence of a signal.

From the output of the amplifier 16, the signal is fed to the input of the selector 11. The selector 11 consists of four subbands of tunable bandpass filters 14 (in the short-wavelength design of 1.5-30 MHz, the fourth subband is absent). The subband is switched on by input 12 and output 13 switches according to commands from MK 18, depending on the installed operating frequency of VU 1. Inside the subband, the middle of the filter passband is tuned to the operating frequency of VU 1 according to commands from MK 18. From the output switch 13, the signal is fed to the output connector of the VU one.

Subsystem ARN and compensation distortion path RPDU.

The ARN subsystem regulates the voltage at the output of the CPP by:

- a control signal from the level sensor at the output of the VU;

- signals of the directional couplers of the incident (PV) and reflected wave (S) at the output of the RPDU;

- a control signal of the state of the RPDU blocks;

- the level of the modulating signal from the CPU 2.

The ARN subsystem also provides protection against voltage surges when switching the operating modes of VU 1 and RPDU. The ARN algorithm is implemented in software in FPGA RFM 5.

The samples of the average and peak level of the modulating signal, calculated in FPGA RFM 5, pass through the delay line, compensating for the delay in the signal of the return channel. The values of the level of the modulating signal are used when controlling the voltage at the output of the DSP 9.

A control signal proportional to the operating voltage at the RF output of VU 1 is generated by the SKZ 15 sensor and fed to MK 18 of the interface module 17. MK 18 performs analog-to-digital conversion and translates the signal samples to the FPGA of RFM 5. The signal level values at the output of VU 1 are used for voltage control of the central heating circuit 9 in the internal AVR mode (excluding the output power of the RPDU) and for monitoring faults.

The signals from the directional couplers PV and OV are fed to the inputs of the return channels OK1 and OK2, respectively. Further, the PV and OV signals through low-pass filters 10, which reduce interference at the “mirrors” of the sampling frequency, are fed to the 1st and 2nd inputs of the four-channel ADC 8. From the output of the ADC 8, the samples of the discrete signals are transmitted to the FPGA 5, where transfer is performed spectrum at zero frequency, filtering with decreasing sampling frequency, calculating the average and peak level of signals. The values of the average and peak level of the PV and OV signals are used to control the voltage of the CPC 9 in the external AVR mode and to control faults.

The PV signal is also transmitted to the FPGA VM 3 and then to CPU 2. The PV signal is used to calculate the parameters of the predistortion algorithm implemented in the FPGA VM 3.

The control signal of the state of the RPDU blocks is fed to the MK 18 of the interface module 17. The MK 18 transmits the samples of the control signal to the FPGA of the RFM 5. When the control signal is increased (which indicates a malfunction or overheating of the RPDU blocks), the AVR algorithm reduces the voltage at the output of CPU 9.

Information sources

1. Utility Model Certificate No. 30043, Н03С 3/10, publ. 08/26/2002

2. Patent No. 1840279, Н04В 1/02, published on August 17, 2006.

Claims (1)

An exciter for radio transmitters comprising a control unit, a signal conditioning unit, an amplifier and a selector, characterized in that the control unit is made in the form of a computing module (VM) comprising a central processing unit (CPU) and a programmable logic integrated circuit (FPGA VM), a signal conditioning unit made in the form of a radio frequency (RF) module containing FPGA RFM, a clock driver, a reference generator (OG), an analog-to-digital converter (ADC), a digital boost converter (DPC), three lower filters frequency (low-pass filter), the selector contains input and output switches, four band-pass filters and a control signal sensor for the state of the blocks of the CKZ radio transmitting device, an interface module containing a microcontroller (MK), a codec and two level converters, with an Ethernet 100 interface, through which control commands are received, it is connected to the CPU, with which the USB port is also connected, the inputs and outputs of the CPU are connected to the FPGA VM, which is connected to the MK interface module, and also through the codec to the inputs of the TLF, through whether the level (PU) is with the input “TLG Input” and the output of RS-422, while the MK of the interface module is connected to the interface of the MU (CAN) and the input “RPDU Control”, as well as the MK output is connected to the FPGA FPM input, and the output MK is connected to the selector CKZ sensor and, by control, to an amplifier, the output of which is connected to the input selector switch, the outputs of which are connected to four bandpass filters that are connected to the output switch, the output of which with the CKZ sensor is connected, is the output of the RF exciter, with two inputs -output FPGA VM management and d They are connected to the two inputs-outputs of the FPGA RFM, the input of which is connected to the ADC output, and the output to the input of the CPU, the output of which is connected to an amplifier, and the three ADC inputs are connected to three outputs of low-pass filters, the first of which receives signals from the input of the return channel of the incident wave of OK PV, the input of the second of which receives signals from the input of the return channel of the reflected wave of OK OB, and the input of the third of which signals of the intermediate frequency (IF), while the input of the driver of the clock signal of the RF module is connected to the output ohm of the reference generator, having for synchronization with external devices an additional output to an external connector and an external input.

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