RU2691731C1 - Wideband signal receiving device - Google Patents

Abstract

FIELD: radio equipment.SUBSTANCE: invention relates to radio engineering, particularly to information processing systems using complex broadband signals, and can be used in broadband interference-protected radio communication devices. Device comprises a receiving unit (RU), a digital receiving device (DRD), an analogue-to-digital converter (ADC), a clock frequency synthesizer (CFS), a control unit (CU), a reference generator (RG), a correlation receiving device (CRD) comprising a correlation processing control unit (CPCU), a signal accumulation unit (SAU), a reference signal generator (RSG), a correlation function calculating unit (CFCU), a synchronization sequence detection unit (SSDU), a signal delay estimation unit (SDEU), a first extrapolator filter (EF1), a correlators unit (CsU), a detection unit (DU), a signal phase estimation unit (SPEU), a second extrapolation filter (EF2), an information reception circuit (IRC).EFFECT: invention is intended to reduce signal detection time and increase accuracy of synchronization of receiving device of broadband signals.1 cl, 5 dwg

Description

The proposed device relates to the field of radio communications using broadband phase-shift keyed signals based on pseudo-random sequences (PSP). The device can be used in broadband jam-proof radio communication systems.

At present, the requirements for the performance of military and special-purpose radio transceiver devices based on spreading methods have increased. At the same time, the capabilities of the specialized element base for high-speed digital signal processing (DSP) have significantly increased. This led to the transfer of information transmission and processing systems on a digital basis, because it ensures the stability and efficiency of communication systems, together with improved performance in the presence of significant levels of a priori uncertainty of signal-information influences.

A device for searching for a pseudo-random sequence described in [1] is known, which contains a low-pass filter, a clock generator, an analog-to-digital converter, a frequency divider, switches, an address counter, OR elements, a loop counter, driver control signals, registers, a generator of memory bandwidth , elements “AND”, accumulation trigger, ALU, detection trigger, RAM, threshold block, keys, shift register with feedback, allowing to reduce the signal search time. Device [1] in terms of functionality and algorithm of operation is similar to the claimed device. The disadvantage of the device [1] is the ability to work only with M-sequences.

The closest in technical essence to the claimed is the device described in [2], adopted for the prototype.

The functional diagram of the prototype device is shown in FIG. 1, where the following notation:

1 - receiving unit (PB);

4 - analog-to-digital converter (ADC);

6 - control unit (CU);

9 - signal accumulation unit (BNS);

10 - shaper reference signals (FOS) - PSP;

15 is a block of correlators (BC);

20 - block information selection (BVI);

21 - digital-to-analog converter (DAC);

22 is a comparison unit (BS);

23 - block select the maximum code (BWMK);

24 is a voltage code conversion unit (BPNK);

25 - block filling correlation convolutions (BNK);

26 is a permanent storage device (ROM).

The prototype device contains serially connected receiving unit (PB) 1, analog-to-digital converter (ADC) 4, signal accumulation unit (BNS) 9, digital-to-analog converter (DAC) 21, correlator unit (BC) 15, voltage-code conversion unit ( BPNK) 24, the block for filling the correlation convolutions (BNK) 25, the block for selecting the maximum code (BVMK) 23, the comparator (BS) 22, the output of which is connected to the input of the control unit (CU) 6; in addition, the device prototype contains the shaper reference signals (FOS) 10, the block information selection (BVI) 20, a persistent storage device (ROM) 26.

The second output of the BNS 9 is connected to the second input of the ADC 4, the output of the FOS 10 is connected to the second input of the BC 15, the second output of the BC 15 is connected to the input of the BVI 20, the output of the ROM 26 is connected to the second input of the BS 22.

The first input-output of the control unit 6 is connected to the input-output of the BNS 9, the second input-output is connected to the input-output of the BVI 20, and the third input-output is connected to the input-output of the BVMK 23; the first output of the control unit 6 is connected to the second input of the BNK 25, the second output is connected to the input of the ROM 26, the third output is connected to the third input of the BC 15 and the second input of the BPSK 24, the fourth output is connected to the input of the FOS 10.

The operation of the device prototype is as follows.

The input mixture of the useful signal, noise and interference enters PB 1, in which preselection occurs, transfer to an intermediate frequency, rejection of spectral regions affected by narrowband interference, blanking of impulse noise and amplification to a fixed average level.

From the output of PB 1, the mixture of the useful signal, fluctuation noise, and wideband interference enters the ADC 4.

In ADC 4, the incoming signal is sampled at a frequency of 4Ft, where Ft is the clock frequency of the modulating pseudo-random sequences, and is quantized in levels, and the samples are converted into a 4-bit binary code. The resulting stream of digital data is continuously recorded in BNS 9.

Compressed data streams from the output of the BNS 9 arrive at the inputs of the DAC 21. Next, from the output of the DAC 21, the analog signal arrives at the BC 15, where in each correlator the input signal is multiplied with the reference video sequence, pre-filtered, transferred to the second intermediate frequency, then detected.

Next, the output signals from the BC 15 are sent to the BPNK 24, where the voltages of digital bundles are normalized by noise and converted into digital form, then sent to the BNK 25, where post-detector accumulation and memorization of the bundles takes place.

Then the values of convolutions are sent to BVMK 23, where the selection of the maximum of the N values of the correlation sums and the determination of its number is made. The value of the maximum code goes to BS 22, where it is compared with the threshold value, which is issued by the ROM 26.

At the end of each accumulation cycle, the CU 6 selects from the ROM 26 two threshold values and in turn outputs them to BS 22.

If the value of the maximum code does not exceed the smaller of the thresholds, the search is terminated. If it exceeds the larger of the thresholds, the signal is considered to be detected.

Next, the CU 6 generates a phasing signal, which arrives at the BNS 9 and synchronizes the instant of the beginning of the recording of the receiving information, and the receiver, accordingly, goes into the tracking mode and the selection of information.

BVI 20 provides information allocation. The FOS 10 generates pseudo-random reference sequences and phases them with the start of reading information from the BNS 9 according to the control command received from the control unit 6.

Based on the description of the operation of the prototype device, it can be concluded that it is made on the circuits and elements of hard logic, which leads to an excessive amount of hardware resources. In the prototype device, blocks were introduced that implement signal conversion from analog to digital and vice versa; there is a block of analog correlators. This greatly limits the functionality, not allowing for the implementation of adaptive algorithms for DSP.

Also, a disadvantage of the prototype device is the inability to receive signals with a variable clock frequency, which limits the ability of the device [2] to adapt to changes in the frequency of the received signal.

The claimed invention solves the problem of developing a receiving device for broadband signals based on high-speed digital signal processing devices while simultaneously improving the characteristics of the device. In addition, all units included in the receiving device must be centrally controlled and dynamically change the search and detection parameters at various signal-to-noise ratios, which allows for the implementation of adaptive signal processing algorithms.

Achieved with the use of the invention, the technical result is to reduce the time of signal detection and increase the accuracy of synchronization of receiving devices of broadband signals that detect complex signals with a known carrier frequency and a random initial phase, while simplifying the hardware implementation and reducing overall characteristics, and the characteristics are improved by adding blocks, performing digital processing, which allows to optimize synchronization algorithms in the process of reception.

To solve the task in the device containing the receiving unit (PB 1), the input of which is the input of the device, the analog-digital converter (ADC 4), the control unit (BU 6), the output of which is the output of the device, and the PB is connected in series with the ADC, According to the invention, a digital receiver (CPU 2), a clock frequency synthesizer (DFC 5), a reference oscillator (OG 7) and a correlation receiver (CPU 3) are introduced,

containing the control unit correlation processing (BUKO 8), the first output of which is the output of the CPU 3, the signal accumulation unit (BNS 9), the first input of which is the first input of the CPU 3, the driver of the reference signals (FOS 10), the first input of which is the second input of the CPU 3, a sequentially connected block for calculating the correlation function (BVKF 11) and a block for detecting a synchro sequence (BFB 12), a series of connected block for estimating a signal delay (BOSC 13) and a first filter extrapolator (FE1 14), a block of correlators (BK 15), the connected detection unit (BO 16), the signal phase evaluation unit (BOPS 17) and the second filter extrapolator (FE2 18), the information receiving circuit (PSI 19), with the groups of inputs-outputs BUKO 8, FOS 10, PSI 19 are inputs-outputs of the CPU 3;

while the first input of the CPU 2 is connected to the output of the ADC 4, and the output is connected to the first input of the CPU 3, the group of inputs-outputs of which is connected to the group of inputs-outputs BU 6; the output of SCh 5 is connected respectively to the second inputs of CPU 2, CPU 3, ADC 4; the first output of the CU 6 is connected to the first input of PB 1, the second output is connected to the first input of the MTS 5, and the third output is connected to the third input of the CPU 2; the first output of exhaust gas 7 is connected to the second input of the MTS 5, and the second output is connected to the second input of PB 1; the output of the CPU 3 is connected to the fourth input of the CPU 2;

Besides,

the first input BVKF 11 is connected to the first output of the FOS 10, the output of the BOS 12 is connected to the first input of BUKO 8; the first output FE1 14 is connected to the second input BNS 9; the first input of the BC 15 is connected to the second output of the FOS 10, and the first output is connected respectively to the input of the BOZS 13 and the first input of the IPA 19; the second output of the BO 16 is connected to the second input of BUKO 8, and the first input is connected to the second output of the BC 15; output BNS 9 is connected respectively to the second inputs BVKF 11 and BK 15, the second output FE1 14 is connected respectively to the second inputs of BO 16, BOFS 17 and SPI 19, output FE2 18 is connected to the third input of PSI 19, the second output of BUKO 8 is connected respectively to the third entrances BNS 9, BC 15 and with the second entrance FOS 10.

The functional diagram of the inventive device is shown in FIG. 2, where the following notation:

1 - receiving unit (PB);

2 - digital receiving device (CPU);

3 - correlation receiver (KPU);

4 - analog-to-digital converter (ADC);

5 - clock frequency synthesizer;

6 - control unit (CU);

7 - reference generator (exhaust).

The inventive device contains a serially connected receiving unit (PB) 1, analog-to-digital converter (ADC) 4 and digital receiving device (CPU) 2, correlation receiving device (CPU) 3, connected by two groups of inputs-outputs with CPU 2; the clock frequency synthesizer (TSC) 5, the output of which is connected respectively to the second inputs of the CPU 2 and the A / D converter 4.

Additionally, the device contains a control unit (CU) 6, the first output of which is connected to the first input of PB 1, the second output is connected to the first input of SCh 5, and the third output is the output of the device; reference generator (OG) 7, the first output of which is connected to the second input of MTS 5, and the second output is connected to the second input of PB 1.

In addition, the CU 6 is connected by a group of inputs-outputs with the CPU 3.

The functional diagram of the CPU 3 is shown in FIG. 3, where the following notation is used:

8 — correlation processing control unit (BUKO);

9 - signal accumulation unit (BNS);

10 - shaper reference signals (FOS);

11 is a block for calculating the correlation function (BVKF);

12 — sync sequence detection unit (BFR);

13 —the signal delay estimation unit;

14 - the first filter extrapolator (FE1);

15 is a block of correlators (BC);

16 - detection unit (BO);

17 - signal phase evaluation unit (BOPS);

18 - the second filter-extrapolator (FE2);

19 - information reception scheme (STI).

CPU 3 contains a signal accumulation unit (BNS) 9, the group of inputs and outputs of which is the first group of inputs and outputs of CPU 3, the control unit of correlation processing (BUCO) 8, the first group of inputs and outputs of which is the second group of inputs and outputs of CPU 3, and the second group of inputs-outputs is the third group of inputs-outputs of the CPU 3.

In addition, the CPU 3 further comprises a shaper reference signals (FOS) 10, the first input of which is the first output of the BNS 9, serially connected unit for calculating the correlation function (BVKF) 11, the first input of which is connected to the first output of the FOS 10, and the sync sequence detection unit ( BOS) 12, the first output of which is connected to the first input of BUKO 8, and the second output is connected to the first input of BNS 9; series-connected unit for estimating the delay of the signal (PSU) 13 and the first filter extrapolator (FE1) 14, the first output of which is connected to the second input of the BNS 9; block correlators (BC) 15, the first input of which is connected to the second output of the OPC 10, and the first output is connected respectively to the input of the gateway 13 and the first input of the information reception circuit (SPI) 19; series-connected detection unit (BO) 16, signal phase evaluation unit (BOPS) 17 and second filter extrapolator (FE2) 18, with the second output BO 16 connected to the second input of BUKO 8, and the first input connected to the second output of BC 15; (SPI) 19 ,.

In addition, the output of BNS 9 is connected respectively to the second inputs of BVKF 11 and BK 15, the second output of BUKO 8 is connected respectively to the third inputs of BNS 9, BK 15 and the second input of FOS 10, the second output of FE1 14 is connected respectively to the second inputs of BO 16, BOFS 17 and SPI 19, the output of FE2 18 is connected to the third input of SPI 19.

The device works as follows.

Before starting the search cycle signal BU 6 sets the search parameters by transmitting control information to the BUK 8 and FOS 10.

Exhaust 7 generates a signal of a stable frequency F _{Exhaust gas} , which is fed to the inputs PB 1 and IS, 5. The signal from the output SW 5 goes to the inputs of ADC 4, CPU 3 and FOC 10.

PB 1 and A / D converters 4 are functionally similar to the units of the prototype device. The input mix of the useful signal, noise and wideband interference enters PB 1, in which preliminary selection takes place, multiplied by a stable frequency signal synthesized from the exhaust signal 7, rejection of spectral regions affected by narrowband interference, blanking of impulse noise and amplification to a fixed average level.

The received signal from the output of PB 1 is fed to the ADC 4. In ADC 4, the signal is sampled at the clock frequency synthesizer frequency, and converted into a parallel binary code.

The converted signal is fed to the input of CPU 2, where the complex envelopes of the corresponding reception channels are extracted, then pre-decimation, subsequent decimation to the minimum required sampling frequency equal to twice the clock frequency of the modulating sequences, amplitude-frequency distortion correction and channel filtering are performed. The CPU 2 also controls the phase of the output signal based on the control codes issued by BUKO 8.

Next, the digitized signal from the output of the CPU 2 is fed to the input of BNS 9, where the accumulation and addition of several periods of repetition of the clock signal occurs. Then the stream of digital data is fed to the inputs BVKF 11 and BK 15, where the signal is multiplied with the reference signal. The reference signal is generated in FOS 10 under control of BUK 8 and clocked by a signal from the ESC 5.

In BVKF 11, the input and reference clock cross-correlation function is calculated using the double Fourier transform (DFT), the maximum squared modulus of the cross-correlation function R _max (k) is determined, the mean square modulus of the cross-correlation function R _cf (k) is calculated, the signal ratio is calculated / noise q ² (k) = R ² _max (k) / R ² _cf (k). The operation is repeated for each value of the detuning in frequency k * Δf, where Δf is the search step of the signal at the carrier frequency, k = 0, ± 1, ± 2 ... ± m.

Then from the output BVKF 11 the values of q ² (k) are sent to the biofeedback 12, where a comparison with the threshold occurs and the decision is made about the detection or absence of a signal in the radio channel.

In the absence of a signal, BFB 12 issues a report to BUK 8. BUK 8 sends a report about the absence of a signal to BU 6, and BU 6 sets new search parameters by transmitting control information to BUK 8 and FOC 10.

When a signal is detected, BFB 12 issues a report to BUK 8. BUKO 8 issues a report to BNS 9 and BK 15.

In BC 15, the cross-correlation function of the input and reference signals is calculated for a detuning by frequency k _О * Δf, the maximum value of the modulus of the cross-correlation function is determined. The calculations are repeated for each period of the signal in the vicinity of the maximum value found with a step equal to half the elementary signal. The found value determines the maximum value of the cross-correlation function and its location.

The obtained value of the time shift relative to the moments of discretization of the signal, the BC 15 transmits to the BOZS 13, which forms an estimate of the time shift. BOZS 13 outputs the obtained values on FE1 14, which performs automatic clock frequency adjustment for LBP 9, BO 16, BOFS 17 and SPI 19.

After detecting the information signal, the CP 16 verifies the detection accuracy by calculating at each signal period the ratio of the modules of the cross-correlation functions of the input signal and the reference synchronization and information signals, averaging these estimates over a certain number of periods and comparing the results with the threshold values.

After receiving confirmation of detection of the signal, the BO 16 issues a report in BUK 8, which issues a report in IPN 19.

Based on the values obtained from FE1 14 and BO 16, BOPS 17 determines the phase angle of the signal, then transfers the calculated values to FE2 18.

FE2 18 performs auto-tuning of the carrier frequency and transmits the obtained values to SPI 19.

SPI 19 on the basis of data received from BC 15, makes a decision about accepting bit “1” if the difference in phase angles is from 0 to 180 degrees, otherwise it is decided to accept bit “0”. Then SPI 19 transmits data to I / O bus 6 via the I / O bus.

The termination of the issuance of information and the transition to the search mode is performed by a command from the BU 6.

REALIZATION.

The ADC 4 unit can be implemented on the basis of the 1273PV5U microcircuit (SKTB ES OJSC, Voronezh) or similar in functionality [3].

The SCh 5 can be implemented as a device described in [4, 5].

The control unit 6 can be implemented as a control device for a noise-free radio system [6], including a microprocessor of the 51x family, for example, based on microprocessors [7, 8].

The control unit 3 can be implemented, for example, on the basis of signal processors from a series of single-chip programmable multiprocessor-on-chip systems based on the IP-nuclear (IP intellectual property) MULTICORE platform, which contain MIPS32 processor cores functions of the central processing unit CPU (Central Processing Unit) and high-performance cores of accelerator cores for floating-point / fixed-point DSP [9] or similar functionality.

The CPU 2 unit can be implemented, for example, on the basis of the 1288HK1 chip [10] or similar in functionality.

ALGORITHMS.

The enlarged algorithm of functioning of the CU 6 is shown in FIG. four.

When switched on in block 6.1, the control parameter values are initialized.

Further, in block 6.2, the initial settings of BUKO 8 and FOS 10 are issued, SPI 19 is activated with a message about waiting for receiving information.

Further, in blocks 6.3 and 6.8, BU 6 goes into standby mode for messages from BUKO 8 or from SPI 19. If a message came from BUKO 8 that the signal in the radio channel was not found, then proceed to block 6.4, where the parameters for BUU 8 are recalculated FOS 10.

Further, in block 6.5, the issuance of new parameters BUKO 8 and FOS 10 and the return to block 6.3.

If a message is received from BUKO 8 that a signal has been detected on the radio channel, then proceed to block 6.6, where data is initialized for the information receiving mode.

Further, in block 6.7, a request is issued for IPN 19 about readiness to receive the next data packet, and transition to block 6.8 to wait for messages from IPA 19.

Next, in block 6.9, the next data packet is received from SPI 19, the next data packet is processed (data packet is checked for correctness), the data is decoded and output, after which it returns to block 6.8.

The enlarged algorithm for the functioning of BUKO 8 is shown in FIG. five.

When enabled in block 8.1, the initial control settings from the CU 6 are received and the values of the control parameters of the CPU 2, BNS 9, FOS 10 and BK 15 are initialized.

Further, in block 8.2, the current values are calculated and the control parameters are issued to the CPU 2, BNS 9, FOS 10 and BC 15 blocks.

BUKO 8 goes into standby mode messages from the BIOS.

If in block 8.3 a message is received from the biofeedback 12 about the absence of a signal, then proceed to block 8.4.

In block 8.4, BUK 8 sends a message to the CU 6 about the need to proceed to the next radio search cycle and set new search parameters.

Further, in block 8.5, BUK 8 goes into standby mode for messages from the CU 6.

Further, in block 8.6, BUKO 8 receives from the CU 6 the next control parameters values and issues them to the CPU 2 and FOS 10 blocks, as a result the mode parameters for the next search of the radio signal are determined. Then comes back to block 8.3.

If in block 8.3 a message is received from the BSB 12, which reports the detection of a signal, then proceed to block 8.7, where a report is received about the detection of a signal on BNS 9 and BK 15.

Further, in block 8.8, BUKO 8 enters the mode of waiting for messages about the detection of an information signal from the CP 16.

In the event that a message has arrived from the BO 16, a transition occurs to block 8.9, where a report is issued to PSI 19 about the start of receiving information.

 Further, in block 8.10, BUKO 8 issues a message about the detection of the information signal on the BC 15, as a result of which the frequency and phase adjustment blocks begin to operate in the radio signal tracking mode.

Further, in block 8.11, BUKO 8 goes into standby mode for messages about termination of information output and transition to search mode from the CU 6.

After receiving the message, it returns to block 8.1.

Thus, the set of new units introduced in the proposed device and their connections allows reducing the time of signal detection and increasing the synchronization accuracy of the receiving device of the broadband signals, which ultimately allows for adaptive digital processing of the received signal and optimizing the synchronization algorithms. In addition, the use of modern hardware can significantly reduce the overall dimensions while simplifying the hardware implementation.

Information sources:

1. RF patent №1788592. Device for searching for a pseudo-random sequence: IPC H04L 7/02, H04L 7/04 / N.I. Kozlenko, Yu.V. Levchenko, V.I. Saprykin, IG Pavlov; applicant and patent holder Voronezh Research Institute of Communications (RU). - №4921630 / 09, announced 3/26/1991, publ. 01/15/1993, Byul. №2.

2. RF patent №1840292. Receiver of broadband signals: IPC H04B 7/00 / А.П. Bilenko, N.I. Kozlenko, R.N. Ryzhkova, N.I. Popolitov, Yu.V. Levchenko; applicant and patent holder Voronezh Research Institute of Communications (RU). - №3060708 / 09, announced 02.28.1983, publ. 27.08.2006, Byul. №24.

3.http: //www.analog.com/ru/analog-to-digital-converters/ad-converters/products/index.html - radio electronic components of the company "Analog Device".

4. RF patent №2419201. Adaptive frequency synthesizer with commutation of the elements of a phase-locked loop: MPK H03L 7/16 / N.М. Tikhomirov, A.V. Lenshin; applicant and patent holder Open Joint-Stock Company Concern Sozvezdie (RU). - №2010106933/09, declared February 24, 2010, publ .: 20.05.2011, Bulletin No. 14.

5. RF patent №2416158. Digital frequency synthesizer: IPC H03L 7/18 / I.P. Usachev, E.I. Stetsura, V.V. Stetzura; applicant and patent holder Open Joint-Stock Company Concern Sozvezdie (RU) - No. 2009134759/2009, announced September 16, 2009, publ .: April 10, 2011, Bulletin No. 10.

6. RF patent №127957. Control device for a noise-free radio system: IPC G05B 19/05 / A.N. Asoskov, Yu.V. Levchenko, I.N. Malysheva, Yu.A. Plakhotnyuk (RU); Applicant and patent holder of JSC Concern Sozvezdie. No. 2012149703/08; declare 11/21/2012, published on 10.05.2013, Byul. № 13. 3 p.

7. http://www.atmel.com/products/ - ATMEL electronic components.

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Claims (2)

A receiver of broadband signals containing a receiver unit (PB), whose input is the device input, an analog-to-digital converter (ADC), a control unit (CU) whose output is the output of the device, with the PB being serially connected to the ADC, characterized in that digital receiver (CPU), clock synthesizer (DFC), reference oscillator (OG) and correlation receiver (CPU), containing a correlation processing control unit (BUKO), the first output of which is the CPU output, signal updates (BNS), the first input of which is the first input of the CPU, the driver of the reference signals (FOS), the first input of which is the second input of the CPU, serially connected correlation function calculator (BVKF) and sync sequence detection unit (BS), serially connected evaluation unit signal delays (BOZS) and the first filter extrapolator (FE1), a block of correlators (BK), a series-connected detection unit (BO), a signal phase evaluation unit (BOFS) and a second filter extrapolator (FE2), an infor ation (IPN), wherein the group buco-O inputs, FOS, are a group of IPN CPU input-output; the first input of the CPU is connected to the output of the ADC, and the output is connected to the first input of the CPU, the group of inputs-outputs of which is connected to the group of inputs-outputs of the CU; the output of the SCh is connected respectively to the second inputs of the CPU, CPU, ADC; the first output of the control unit is connected to the first input of the safety alarm, the second output is connected to the first input of the EPS, and the third output is connected to the third input of the CPU; the first output of the exhaust gas is connected to the second input of the ESC, and the second output is connected to the second input of the PB; the output of the CPU is connected to the fourth input of the CPU; in addition, the first input BVKF connected to the first output of the FOS, the output of the BOS is connected to the first input of the BUCO; the first output FE1 is connected to the second input of the BNS; the first input of the BC is connected to the second output of the FOS, and the first output is connected respectively to the input of the PSU and the first input of the IPN; the second output BO is connected to the second input of the BUKO, and the first input is connected to the second output of the BC; the output of BNS is connected respectively to the second inputs of BVKF and BK, the second output of FE1 is connected respectively to the second inputs of BO, BOFS and SPI, the output of FE2 is connected to the third input of SPI, the second output of BUKO is connected to the third input of FNS.

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