RU2652529C1 - Method and device for phasing and equal-signal differential automatic tracking of non-uniform digital antenna array for reception of wide-band signals - Google Patents

Abstract

FIELD: radio engineering and communications.

SUBSTANCE: invention relates to radio engineering and can be used to receive broadband signals. Device comprises a receiver, a beamforming processor, a memory, a data bus, a control computer, an address decoder, a clock generator, a local oscillator, and a set of signal reception paths from antennas that are part of the antenna array. Moreover, each of the signal reception paths is connected to a data bus, and the control computer, the address signal decoder and the clock generator are common for each of the signal reception paths. Said signal reception path includes two antenna signal sampling units associated with the address decoder, the control computer, receiver and antenna control grids in the azimuth and elevation angle, with the address decoder, the control computer, the receiver is associated with delay blocks of the pulse train, one for each sampling channel.

EFFECT: technical result consists in increased speed of a antenna phasing unit when receiving broadband signals from the antenna field.

10 cl, 9 dwg

Description

The invention relates to radio engineering and can be used to receive broadband signals in a system for collecting telemetric information from onboard equipment of spacecraft.

There is a method of forming the antenna array radiation pattern by introducing a phase shift in the numerical sequence of samples of signals from the array antennas [see Problems of antenna technology / Ed. L.D. Bahraha D.I. Voskresensky. - M .: Radio and communications, 1989 .-- 368 p.: Ill. - ISBN5-256-00335-6]. For a relatively small number of antennas, this method is implemented by the serial circuit shown in FIG. 1, where: 1 - receiving antenna; 2 - input low-noise amplifier (LNA) and feeder to the mixer; 3 - mixer; 4 - the first local oscillator; 5 - intermediate frequency amplifier with a bandpass filter (UPCH-PF); 6 - divider; 7 - synchronous phase detectors (SFD); 8 - second local oscillator; 9 - constant phase shifter 90 °; 10 - analog-to-digital converters (ADC); 11 - clock generator (GTI); 12 - decoder address signal; 13 - data bus; 14 - processor beamforming (PFDN); 15 - storage device (memory); 16 - control device (UE); 17 - receiver; 18 - control computer, 21 - key.

The output of each receiving antenna 1 is connected to the input of the corresponding LNA 2, the output of each LNA 2 is connected to the signal input of the corresponding mixer 3, the local oscillator input of which is connected to the output of the first local oscillator 4, the output of each mixer 3 is connected to the input of the corresponding IF-PF 5, the output of which is connected with the input of the corresponding divider 6, the first output of each divider 6 is connected to the signal input of the first, and the second output of the divider is connected to the signal input of the second of the corresponding pair of synchronous phase detectors 7, the heterodyne input of each first in the corresponding pair of SFD 7 is connected to the output of the second local oscillator 8, and the heterodyne input of every second in the corresponding pair of SFD 7 is connected to the output of the constant phase shifter by 90 ° 9, the input of which is connected to the output of the second local oscillator 8, the output of each SFD 7 connected to the signal input of the corresponding ADC 10, the input of the start pulses of which is connected to the output of the GTI 11, the data output of each ADC 10 is connected to the input of the corresponding key 21, the control input of which is connected to the corresponding output of an address signal 12 emitter, whose input is connected to the first address bus of the УУ 16, the synchronization input of the УУ 16 is connected to the output of the GTI 11, the output of the key 21 is connected to the corresponding input of the data bus 13, the output of which is connected to the first data input of the PFDN 14, and the second data input PFDN 14 is connected to the data output of the memory device 15, and the control input PFDN 14 is connected to the control output of the memory device 16, the address bus of the memory device 15 is connected to the second address bus of the memory device 16, the data output of the PFDN 14 is connected to the data input of the receiver 17, data bus and address of the memory device 15 connected to data bus and address and the host computer 18.

The wavefront of the radio signal with a shift for antenna No. i falls on the antenna 1 of the grating for the time of the difference in the path of the rays Дt _io relative to the reference antenna No. 0. The signal received by the antenna is amplified in the corresponding low-noise amplifier 2, reduced in frequency using the first local oscillator 4 and mixer 3, amplified and limited in frequency band using an intermediate-frequency amplifier and a band-pass filter 5, branched into two signals by a divider 6, and quadrature signals are generated using the corresponding synchronous phase detector 7, the second local oscillator 8 and a constant phase shifter 90 ° 9, after which on the analog-to-digital Converter 10 under the influence of pulses with a frequency of sampling f _d from the clock generator 11 form digital readings of the values of quadrature signals S _iс = A _i · cos (2рf _s t) and S _is = A _i · sin (2рf _s t) with an average frequency of the spectrum f _s , and under the influence of address the signals from the decoder 12 coming from the control device 16 upon the arrival of the synchronization pulse from the GTI, the signals of different lattice antennas through the corresponding keys 21 are sequentially inserted into the data bus 13 and then introduced into the beamforming processor 14, on which the individual phase shift is generated signal of each antenna on the basis of data on the relative delays of the signal phase front at different antennas dt _io, which are stored in the memory 15 and calculated in advance for target indications in the control computer 18. The processor 14 beamforming based on the relative delay dt _io wavefront calculates the difference phase of the signals at the average frequency f _s of the signal spectrum after the ADC according to the formula Дс _io = 2рf _s Дt _io , determines the resulting phased signals according to the formula S _iД = A _i · cos (2рf _s t + Дц _io ) = A _i · [cos (2рf _s t) cos (Дц _io ) - sin (2 pf _s t) · sin (Дц _io )] = S _iс · cos (Дц _io ) - S _is · sin (Дц _io ) and calculates the total signal from all the antennas of the array, and then outputs it to the receiver 17.

The main disadvantages of the known solution for forming the antenna array radiation pattern by introducing a phase shift in the numerical sequence of samples of signals from the array antennas are its relative complexity and unsuitability for transmitting broadband signals. Indeed, when phasing signals from N antennas, 2N relatively labor-intensive multiplication operations and an N-1 addition operation are required. In addition, with a fairly wide spectrum of phase incursions in symmetrical harmonics of different antennas that are far enough far in frequency, they lead to unacceptable distortion of the transmitted signal. For example, harmonics at the edges of the spectrum when transmitting telemetric information (TMI) at a speed of 3 Mbit / s, spaced by about Df = 6 MHz, with a difference in the path of the rays between the antennas at DL = 30 m, will give an incursion of phases Dts = 2p · Df 2р · Дf · (ДL / c) = 2р · 6 · 10 ⁶ · 30 / (3 · 10 ⁸ ) = 1,2р. Harmonics from the middle part of the spectrum of the TMI signal, spaced about Df = 3 MHz, will give a phase advance of 0.6 p. Since, during detection, the symmetric frequencies of the spectrum of the radio signal are added up, the indicated phase incursions will lead to strong distortions of the transmitted broadband signals. In addition, in the known technical solution, the relative delays of the signal of one phase front on different antennas Дt _io throughout the entire radio visibility zone must be calculated based on target designations in advance, which required the storage of significant amounts of information in the storage device 15.

In turn, the above disadvantages are eliminated in the proposed method and device for phasing and auto tracking non-equidistant digital antenna array for receiving broadband signals. Using the proposed method and device will ensure the reception and processing of broadband signals without distortion while providing auto tracking of the spacecraft (SC) and ensuring the speed of the phasing device of the antenna of the antenna field when receiving broadband signals from the antenna field that carry, for example, telemetry information about the state of onboard systems of spacecraft for example low orbit.

A method is proposed for processing broadband signals and auto-tracking of a spacecraft, which provides for signal reception by antennas that are part of the antenna array, and the formation of digital (discrete) samples of the received signal of each antenna in the corresponding two quadrature information channels, followed by the summation of digital (discrete) samples of each quadrature channel from several antennas when monitoring the signal travel time from the reference and slave antennas of the antenna array to its analog-to-digital device transformation, as well as providing for the formation of digital (discrete) samples of the received signal of each antenna in four auto-tracking channels with a certain lead and the same lag from the samples of the corresponding quadrature information channel, followed by the formation on their basis of auto-tracking signals of the antennas in azimuth and elevation, as well the calculation of their values of the new values of the relative delays of the signal of one phase front on different antennas with the subsequent input of the corresponding signals There are delays in the corresponding registers of the proposed device for the formation of subsequent samples of the received signals of one edge. In contrast to the analog, the broadband signals received by the indicated antennas and arriving at the proposed phasing and auto tracking (UVA) device are not phase shifted, but are sampled with a sampling period Dt _d with delays relative to the time of arrival at the corresponding feeders at the corresponding UVA for the duration of the stand Dt _p as shown in the diagram of FIG. 2 for information channels. That is, it is not the received signals that are delayed, but the corresponding sequence of sampling pulses so that the sampling time of the signal of each antenna corresponds to the same edge of the incoming signal. For this, the next k-th sampling pulse of the generator for the information signal of antenna No. i, formed at time t _Гk , is delayed for a while

_Zik = dt dt dt + _{si0k .phi.i} - dt dt + _{p ^ 0.} (one)

Here Дt _сi0k is the shift time of the arrival time of the wavefront of the received signal at antenna No. i relative to the reference antenna No. 0, can be negative if the signal arrives at antenna No. i earlier than antenna No. 0, and positive if the signal arrives at antenna No. i later than to antenna No. 0 and changes during the spacecraft radio-visibility zone. The remaining terms of the delay time are constants. So, Dt _fi is the propagation time of the signal wave front in the feeder from the phase center of antenna No. i to the phasing and auto-tracking device for UVA. Further, Dt _p is the stand time, which is chosen so that the time instant of the k-th sampling pulse on all antennas comes later than the k-th sampling pulse of the generator, that is, from the condition Дt _zik > 0. This condition is always satisfied if the stand time Дt _п is chosen from the condition

_N dt> dt _fmax - _fmin + dt dt dt _Pmax + _none + dt _ADC (2)

where dt _fmax and dt _fmin - the minimum and maximum signal wavefront propagation in the feeder of the antenna array, respectively, dt _Pmax - maximum possible propagation time of the signal wave front into free space on diameters of antenna array dt _none - the deviating points in time taking reference to negative and in the positive direction for the formation of auto-tracking signals relative to the time of taking a sample in the information channel, Дt _ADC - the time of formation of a reference for the ADC.

In one automatic tracking each channel quadrature antenna i-th sampling pulse sequence is delayed by a time dt _none less than the delay of the sampling pulses corresponding to an information channel dt _zik, that is delayed by the time

Dt = dt _{zikAS1 zik} - _none dt = dt + dt _{si0k .phi.i} - _{^ 0} dt dt + _n - _none dt, (3)

and the second channel of the same quadrature autotracking the same i-th antenna sampling pulse sequence is delayed by a time dt _none greater than the sampling pulses delayed in a corresponding data channel dt _zi, that is delayed by the time

Dt = dt _{zikAS2 zik} + _none dt = dt + dt _{si0k .phi.i} - _{^ 0} + dt dt dt _n + _none. (four)

Since in accordance with FIG. 2 readout in the information channel of each antenna take after one the same for all antennas stand time Dt_P after the phasing and auto tracking (UVA) device arrives at the same wavefront of the received signal at different times for different antennas t_UVAi, then the samples taken for different antennas at time t_k + Dt_zi, also refer to the same wavefront of the received signal arriving at the phase centers of the antennas and at the UVA later on for the time Дt_P . That is, if the value of the signal arriving at time t_wik on the phase centers of the antennas is equal to S (t), then the value of this signal (let's call it the sine quadrature signal) arriving at time t_UFAik on UVA, equal

S _i (t) = K _i · S (t), (5)

where K _i is the transmission coefficient of the path of the i-th antenna from the phase center to UVA.

If the value of the signal S (t) passed through the phase shifter by 90 ° at time t _tik is equal to S ₉₀ (t), then the value of this cosine quadrature signal arriving at time t t _UFAik at UFA will be equal to

S _90i (t) = K _i · S ₉₀ (t). (6)

Thus, from the signal of the ith antenna S _i (t), i = 0, ..., N, at discrete time instants t _ik = t _Гk + Дt _zik = t _UVAik + Dt _p , the samples of two quadrature information channels are formed:

S _ik = S _i (t + Dt _p ) = K _i · S (t + Dt _p ) (7)

S _90ik = S _90i (t + Dt _p ) = K _i S ₉₀ (t + Dt _p ) (8)

From (7) and (8) we see that, ideally, for the same transmission coefficients K _i in the receiving paths of different antennas and in the absence of noise, the corresponding quadrature readings of signals in the information channels of different antennas for the same wave front will be the same.

The discrete times t = t _{ikAS1 gk} + dt _{zikAS1 gk} = t + dt _zik - _none dt = t + dt _{UFAik n} - _none dt for each quadrature channel are formed readings autotracking ahead of the corresponding information channel:

S _ik- = S _i (t + dt _n - _{none dt) = K i · S (t} + dt _n - dt _none) (9)

S _90ik- = S _90i (t + dt _n - _none dt) = K _i · S ₉₀ (t + dt _n - dt _none) (10)

Finally, at discrete times t = t _{ikAS2 gk} + _zikAS2 dt = t _gk + _zik + dt dt _{none UFAik} = t + dt _n + dt _none for each quadrature channel are formed autotracking readings with a time lag from the respective information channel:

_{S ik + = S i (t} + dt _n + _{none dt) = K i · S (t} + dt _n + dt _none) (11)

_{S 90ik + = S 90i (t} + dt _n + _none dt) = K _i · S ₉₀ (t + dt _n + dt _none) (12)

From (9) ÷ (12) we see that, ideally, for the same transmission coefficients K _i in the receiving paths of different antennas and in the absence of noise, the signal counts in the corresponding auto tracking channels (with lagging or ahead) of different antennas for one wave front will also be the same .

The generated digital (discrete) samples of the received signals from each antenna for each of the six channels (two information (sine and cosine) and four auto-tracking channels (two sine ahead and backward and two cosine ahead and backward) write each in its corresponding indexed array memory in the cell with the corresponding current index k related to the current wave front of the signal.

With a delay from the kth sampling pulse at the master oscillator, sufficient for the signal from the antenna with the greatest delay to arrive, in the sine and cosine information channels, they are selected from the corresponding arrays and digital (discrete), respectively, sine and cosine samples, one from each antenna, are summed with the same index k related to the same wavefront of the signal. Then, the amplitude and reference phase of the received information signal are determined. For the sine and cosine information channels, the process of summing the antenna information samples is carried out in each sampling interval Дt _д .

In accordance with (1), the delay time guaranteeing the start time of the summation of the samples from the antennas of one edge after this edge arrives from the antenna with the greatest delay is selected from the condition:

Дt _z∑ > Дt _рmax + Дt _фmax - Дt _фmin + Дt _п (13)

In accordance with (2), this condition is equivalent to the following condition:

Dt _zΣ> 2 _n · dt - dt _none - dt _ADC (14)

By analogy with condition (13), to start processing samples in four auto tracking channels in accordance with (4), a delay in the formation of a sample relative to the k-th sampling pulse on the master oscillator must be provided based on the condition:

_ZAS dt> dt dt _Pmax + _fmax - _fmin + dt dt dt _n + _none, (15)

which, taking into account (2), is equivalent to the condition:

Dt _zAC > 2 · Dt _p - Dt _ADC . (16)

As the time deviation dt _none and dt _ADC of the signal time ADC small compared with the maximum possible time signal wavefront propagation in free space on diameters of antenna array dt _Pmax, then in accordance with (13) and (15) the value of the delay time starts processing counts of one wave front in the information channels Dt _zobrI and in the channels of auto tracking Dt _zobrAS can be established on the basis of the same condition:

Dt _zobr >2; Dt _p (17)

Dt _zobrAS > 2 · Dt _p

At the same time, it should be noted that processing in the information circuit is reduced to a simple addition of discrete samples related to one wavefront of the received signal, which requires a time Dt _arrI significantly less than the sampling period of the signal Dt _d , while at each step of auto tracking it is necessary to perform rather complex calculations that may require processing time Дt _obrAC significantly longer than the sampling period Дt _д , however, the dynamics of the angular displacement of the spacecraft is several orders of magnitude slower than the dynamo Changes in transmitted information signals.

The processing of the values of the samples in the channels of auto tracking is carried out with a period of time T _AC , which is selected from the conditions:

T _AC > Dt _obrAS (18)

and makes up

M _dAS = (T _AC / Dt _d ) (19)

sampling periods. Since the process of angular motion of the spacecraft is much slower than the process of changing the radio signal, the conditions T _AC >> Dt _d and M _dAC >> 1 are always satisfied in order to manage to calculate the corrected digital signals of antenna auto-tracking.

At the jth step of auto tracking, samples of auto tracking channels with the number k = (Dt _zobrI / Dt _d ) + j · (T _AC / Dt _d ) are processed.

The processing is as follows:

1) Determine the sum of the values of the information signals, respectively, the sine and cosine quadratures of all the antennas of the array:

(20)

(twenty)

(21)

(21)

2) Determine the phase of the lattice information signal:

(22)

(22)

3) For each i-th antenna, the difference in the values of the samples for the sine and cosine quadratures in the auto tracking channels taken with a deviation in the negative and in the positive direction relative to the k-th sample of the information channel is found, and the values of the difference signal for the sine and cosine quadratures i- th antenna:

Du _ACik = S _ik– - S _{ik +} (23)

Du _AC90ik = S _90ik– - S _{90ik +} (24)

4) Determine the sum of the values of the difference signals of the sine and cosine quadratures of the antennas near the spacecraft part of the antenna field relative to the phase center of the array:

(25)

(25)

(26)

(26)

5) The sum of the values of the difference signals of the sine and cosine quadratures of the antennas distant to the spacecraft part of the antenna field relative to the phase center of the array is determined:

(27)

(27)

(28)

(28)

6) Determine the value of the difference of the total values of the difference signals of the sine and cosine quadratures of the antennas near and far to the spacecraft parts of the antenna field relative to the phase center of the array:

(29)

(29)

(30)

(thirty)

5) Determine the module of the control signal for guiding the array antennas by elevation angle Φ:

(31)

(31)

6) Determine the phase of the control signal for pointing the array antennas in elevation Φ:

(32)

(32)

7) Determine the sign of the control signal of pointing the antennas of the array in elevation Φ:

(33)

(33)

8) The control signal for pointing the array antennas in elevation angle Φ with the value

(34)

(34)

they are converted into analog form, filtered on a low-pass filter, amplified on electric machine amplifiers and fed to the antenna pointing drives of the array in elevation.

9) Determine the elevation angle of the antenna array pattern at the j-th step of auto tracking:

(35)

(35)

Here K _Φ is the transmission coefficient of the digital control loop in elevation.

The elevation angle at the beginning of the radio visibility zone is determined by the adopted technology for conducting communication sessions with the spacecraft. As a rule, the spacecraft work from the horizon in the zero radio visibility zone when Φ _ДН0 = 0, however, the initial direction can be any direction on the spacecraft within the radio visibility zone and, therefore, any value of the initial elevation angle from zero to the highest elevation angle target designation on the spacecraft.

10) Determine the sum of the values of the difference signals of the sine and cosine quadrature antennas of the left part of the antenna field relative to the direction of the spacecraft from the phase center of the array:

(36)

(36)

(37)

(37)

11) Determine the sum of the values of the difference signals of the sine and cosine quadrature antennas of the right side of the antenna field relative to the direction of the spacecraft from the phase center of the array:

(38)

(38)

(39)

(39)

12) Determine the difference value of the total values of the difference signals of the sine and cosine quadratures of the antennas left and right relative to the spacecraft and the phase center of the array of parts of the antenna field:

(40)

(40)

(41)

(41)

13) Determine the control signal module of the antenna guidance of the array in azimuth W:

(42)

(42)

14) Determine the phase of the control signal of the guidance of the antennas of the array in azimuth W:

(43)

(43)

15) Determine the sign of the control signal of the guidance of the antennas of the array in azimuth W:

(44)

(44)

16) The control signal for guiding the array antennas in azimuth Ш with the value

(45)

(45)

they are converted into analog form, filtered on a low-pass filter, amplified on electric machine amplifiers and fed to the antenna pointing drives of the array in azimuth.

17) Determine the azimuth of the antenna array pattern at the j-th step of auto tracking:

(46)

(46)

Here K _Ψ is the transmission coefficient of the digital control loop in azimuth. The initial azimuth value is determined by the target designation on the spacecraft.

18) The direction cosines of the antenna array antenna radiation patterns are determined at the jth step of auto tracking in the local coordinate system shown in FIG. 3, by the formulas

cos (α _ДНj ) = cos (Ц _ДНj ) · sin (Ш _ДНj ); (47)

cos (β _ДНj ) = cos (Ц _ДНj ) · cos (Ш _ДНj ); (48)

cos (γ _ДНj ) = sin (Ц _ДНj ) (49)

19) Determine the difference in the path of the rays from the direction of the antenna pattern at the j-th step of auto tracking between antennas No. _i (A _i ) and the reference antenna No. 0 (A ₀ ) according to the formula:

ΔR _i0j = L _i0 · cos (∠А _i -0-ДНj) =

= L _i0 · [cos (α _i0 ) · cos (α _ДНj ) + cos (β _i0 ) · cos (β _ДНj ) + cos (γ _i0 ) · cos (γ _ДНj )] (50)

Here L _i0 is the distance between the phase centers of the antennas A _i and A ₀ , cos (α _i0 ), cos (β _i0 ), cos (γ _ДНj ) are the direction cosines of the vectors from the reference antenna A ₀ to the antenna A _i , are calculated by the formulas:

(51)

(51)

cos (α _i0 ) = (x _i - x ₀ ) / L _i0 ; (52)

cos (β _i0 ) = (y _i - y ₀ ) / L _i0 ; (53)

cos (γ _i0 ) = (z _i - z ₀ ) / L _i0 ; (54)

where (x _i, y _i, z _i ) and (x _0, y _0, z ₀ ) are the coordinates of the phase centers of the antennas A _i and A ₀ in the local coordinate system (see figure 3).

20) Determine Дt _сi0j - estimate of the shift in time of arrival of the radio signal between antennas A _i and A ₀ according to the formula:

Дt _сi0j = ΔR _i0j / c, (55)

where c is the speed of light in free space.

21) Replace on the registers of the proposed CAR phasing and auto tracking device digital signals of the time shift of the arrival of the radio signal between antennas A _i and A ₀ with values Dt _ci0j-1 to digital signals formed at the jth step of auto tracking with Dt _{ci0j values} for UVA operation at ( j + 1) -th step of auto tracking.

Since the values of the mismatch signals due to inaccurate but in-phase guidance on the antennas located on opposite sides relative to the phase center of the array will have the opposite sign, when subtracting the absolute values of these signals will add up, increasing the value of the resulting mismatch signal.

 The essence of the proposed equal-difference difference method of auto tracking in a digital antenna array is illustrated by vector diagrams in FIG. 4-14 for harmonics of received signals.

Suppose that a harmonic signal S is received by an array of two antennas A1 and A2. In the information path, antenna A1 receives signal S ₁ , and antenna A2 receives signal S ₂ . The automatic tracking signal path from the power take proactively and with a delay relative path information for an interval of time dt deviation _none.

At exact hover both antennas to the source signal phase shift relative to the phase center of the lattice received by antennas A1 and A2, the signals S ₁ and S ₂ is zero and the time deviation dt _none taking readout in automatic tracking channels regarding traffic channel such that the shift signal phase in the auto-tracking channels | c ₁ | <90 °, the vector diagram of the signals on antennas A1 and A2 will have the form shown in FIG. 4. Here, d1 - difference signal vector S _1- received by the antenna A1 on channel autotracking proactively in time dt _none S ₁ relative to the signal received by the antenna A1 in the data path, and S ₁₊ signal received by the antenna A1 on channel autotracking lagging _none dt at time relative to the signal S ₁ received by the antenna A1 in the data path. The vector d2 of the difference of the corresponding signals S _2- and S ₂₊ received in the channel ahead of and with a lag in the auto-tracking path of antenna A2 has a similar value. Obviously, the zero deviation of the antenna patterns from the direction to the signal source for difference signals of deviation in the time of sampling is equal to the signal, the difference signals d1 and d2 are equal to each other, and their difference d12 = d1 - d2, which is the antenna pointing signal, is zero.

At the same time deviations taking readout signal dt _none in tracts autotracking A1 antennas and A2 at a certain deviation of the lattice of the radiation pattern of the direction of the source signal towards the antenna A2, resulting in a received signal phase shift in the information channel of the antennas A1 through an angle of + ξ ₂ , and in antenna A2, at an angle of ξ ₂ relative to the phase center of the grating, where ξ ₂ <90 °, we have a vector diagram of the signals in FIG. 5, and with the same deviation of the array pattern towards the antenna A1, we have a vector signal diagram in FIG. 6. In these cases, the subtraction of the difference signals d1 and d2 forms an already non-zero antenna pointing signal d12, the sign of which depends on the direction of the deviation of the array pattern.

Size antenna pointing signal d12 with the same deviation pattern lattice ξ ₂ from the signal source chart is determined by the taking of readout signals deflection dt _none in tracts autotracking A1 antennas A2 and reaches a maximum at a value of time deviations dt _off when the shift signal phase in the channels of auto tracking | q ₂ | = 90 °, as shown in FIG. 7, 8 and 9.

The maximum maximum of the antenna pointing signal d12 reaches the quadruple of the received signal value by one antenna S (without taking into account the attenuation of the partial antenna pattern), when this deviation of the array pattern leads to a phase shift of the received signal in the information channel of antennas A1 and A2 relative to the phase center of the array by an angle ξ ₃ = 90 °, as shown in FIG. 10 and 11. This hypothetical case, which is of purely theoretical interest, determines the dynamic range of the antenna pointing signal in the proposed equal-difference method, namely | d12 | _maxmax = 4 | S |.

In FIG. 12, 13 and 14 are vector signals of antenna patterns in a case where time deviations taking readout dt _none signals in paths autotracking has a value such that the shift of the signal phase automatic tracking channels regarding traffic channel 90 ° <| n ₃ | <180 °. We see that when the phase shift relative to the phase center of the grating in the auto tracking channels exceeds 90 °, the value of the antenna pointing signal d12 begins to decrease, turning to zero at a shift of 180 °. This allows us to give the following recommendation on the choice of the value of time changes taking counts dt signals _off the path automatic tracking.

The capture sampling signal deviation dt _none in tracts autotracking should be selected so that the harmonic of the signal in the middle of the spectrum f _s for automatic tracking channels have a phase shift relative to corresponding harmonics in the middle part of the information channel of the spectrum by about ± 90 °, i.e. starting from condition 2 · p · f _s · _none dt = p / 2. Then the vector diagrams for harmonics in the middle part of the spectrum of the received broadband signal will have the form shown in FIG. 7-9, the vector diagrams for harmonics in the lower part of the spectrum of the received broadband signal will be as shown in FIG. 4-6, finally, the vector diagrams for harmonics in the upper part of the spectrum of the received broadband signal will have the form shown in FIG. 12-14.

It is important that such a timing deviation dt _none resulting difference signals from all the spectrum of the received RF signal harmonics have the same polarity and are summed absolute values resulting in the formation of the antennas on the proposed guidance signal equisignal-difference method.

The affiliation of the antenna to the near or far, left or right side of the antenna field relative to the phase center of the array, used in the calculations according to formulas (25) ÷ (32), (36) ÷ (43), is determined as follows.

1) The coordinates of the phase center of the digital antenna array are determined by the formulas

(56)

(56)

Here N is the number of antennas in the antenna field array; (x _i, y _i, z _i ) - the coordinates of the phase center of the antenna A _i in the local coordinate system (see figure 3).

2) Determine the distance from the phase center (FC) of the CAR to each antenna A _i :

(57)

(57)

3) Determine the directional cosines of the vectors from the CAR phase center to each antenna A _i in the local coordinate system (Fig. 15):

cos (α _iс ) = (x _i - x _фц ) / L _iц ; (58)

cos (β _iс ) = (y _i - y _фц ) / L _iц ; (59)

cos (γ _iс ) = (z _i - z _фц ) / L _iц ; (60)

4) Determine the directional cosines of the projections onto the horizontal plane of the vectors from the phase center of the CAR on each antenna A _i :

cos (α _iCG ) = (x _i - x _FC ) / L _iCG = (x _i - x _FC ) / (L _iC sin (γ _iC )) = cos (α _iC ) / sin (γ _iC ); (61)

cos (β _yc ) = (y _i - y _fc ) / L _iCG = (y _i - y _fc ) / (L _iC cos (γ _iC )) = cos (β _iC ) / sin (γ _iC ); (62)

5) Determine the directional cosines of the projection onto the horizontal plane of the vector of the radiation pattern of an individual antenna at the current time:

cos (α _DNGj ) = sin (W _DNJj ); (63)

cos (β _DNGj ) = cos (W _DNJj ); (64)

6) In the horizontal plane for each antenna, determine the cosine of the difference in azimuths of the direction to the antenna and the current direction of the antenna pattern:

cos [∠ (azimuth DNj - azimuthA _i )] = cos (α _iGG ) cos (α _DNGj ) + cos (β _iGG ) · cos (β _{DNG j} ) =

= cos (α _ijc ) / sin (γ _ijc ) · sin (W _DNj ) + cos (β _ijc ) / sin (γ _ijc ) · cos (W _DNj ); (65)

7) Determine the condition "closer" - "further" for each antenna at the current time:

if cos (∠ (azimuth ДНj - azimuth А _i ))> 0, then А _{i is} closer to the spacecraft than the FC; (66)

if cos (∠ (azimuth ДНj - azimuth А _i )) <0, then А _{i is} further from the spacecraft than the FC. (67)

8) In the horizontal plane for each antenna, determine the sine of the difference in azimuths of the direction to the antenna and the current direction of the antenna pattern:

sin [∠ (azimuth ДНj - azimuth А _i )] = - cos {∠ [(azimuth ДН j + р / 2) - azimuth А _i ]} =

= - {cos (α _iq ) / sin (γ _iq ) · sin (W _DNj + p / 2) + cos (β _ij ) / sin (γ _ij ) · cos (W _DNj + p / 2)} =

= –Cos (α _iц ) / sin (γ _i ·) · cos (W _DN ) + cos (β _i )) / sin (γ _i )) · sin (W _DN ) (68)

9) Determine the condition "right" - "left" for each antenna at the current time:

If sin (∠ (azimuth ДНj – azimuth А _i ))> 0, then А _{i is to the} left of the FC; (69)

If sin (∠ (azimuth ДНj - azimuth А _i )) <0, then А _{i is} more to the right than the FC. (70)

A phasing and auto-tracking device for a nonequidistant digital antenna array for receiving broadband signals is proposed, which contains a set of signal reception paths from antennas and auto-tracking antennas that are part of the antenna array.

A diagram of the proposed phasing device and equal-difference differential auto tracking of a non-equidistant digital antenna array for receiving broadband signals is shown in FIG. 16, where: 1 - receiving antenna; 2 - input low-noise amplifier (LNA) and feeder to the mixer; 3-1 - mixer of the first intermediate frequency (ПЧ-1); 3-2 - mixer of the second intermediate frequency (FC-2); 4 - the first local oscillator; 5-1 - amplifier ПЧ-1 with a bandpass filter (UPCH-PF-1); 5-2 - amplifier ПЧ-2 with a band-pass filter (UPCH-PF-2); 6 - divider; 8 - second local oscillator; 9 - constant phase shifter 90 °; 11 - clock generator (GTI); 12 - decoder address signal; 13 - data bus; 14 - processor beamforming (PFDN); 15 - storage device (memory); 16 - control computer (UEM); 17 - the receiver. In this proposed phasing and auto tracking device, synchronous phase detectors - 7 are eliminated (see Fig. 1), the functions of the control device are assigned to the control computer (UEVM) - 16 and the following are introduced: mixers ПЧ-2 - 3-2, amplifiers with filters UPCh- PF-2 - 5-2, counter-divider - 19; block delay pulse sequence (BZPI) - 20; index signal key - 21; antenna signal sampling units (BDSA) - 23; azimuth antenna pointing signal register - 24; the antenna pointing signal register in elevation - 25; digital-to-analog transducer of the guidance signal in azimuth - 26; digital-to-analog converter of a signal of guidance by elevation - 27; low-pass filter of the azimuth guidance signal - 28; low-pass filter of the guidance signal by elevation - 29; azimuth electric guidance amplifiers - 30; electric machine amplifiers for elevation guidance - 31; azimuth guidance drives - 32; elevation guidance drives - 33; auto tracking period counter - 34; scheme for comparing the auto tracking period - 35; auto tracking period signal register 36, OR circuit 37.

The output of each antenna 1 is connected to the input of the corresponding LNA 2, the output of each LNA 2 is connected via a feeder to the signal input of the corresponding mixer 3-1, the local oscillator input of which is connected to the output of the first local oscillator 4, the output of each mixer 3-1 is connected to the input of the corresponding IF-PF -1 5-1, the output of which is connected to the input of the corresponding divider 6, the first output of each divider 6 is connected to the signal input of the first, and the second output of the divider is connected to the signal input of the second of the corresponding pair of mixers 3-2, and the heterody the input of each first in the corresponding pair of mixer 3-2 is connected to the output of the second local oscillator 8, and the heterodyne input of each second in the corresponding pair of mixer 3-2 is connected to the output of the constant phase shifter 90 ° 9, the input of which is connected to the output of the second local oscillator 8, output each mixer 3-2 with a signal input 1 of the corresponding block of sampling of the antenna signal (BDSA) 23.

The output of the GTI 11 is connected to the counting input of the counter-divider 19, with the input of the phasing pulses 10 of the delay block of the pulse sequence BZPI 20 and with the input of the phasing pulses 2 of each antenna signal sampling unit (BDSA) 23; the output of the counter-divider 19 is connected to the synchronization input of the control computer 16, with the input of 11 sampling pulses of the delay block of the pulse sequence BZPI 20 and with the input of sampling pulses 3 of each sampling block of the signal signal of the BDSA 23. The output of the key 21 and output 4 of each BDSA is connected to the input input data bus data 13.

The first address bus of the UEVM 16 is connected to the input of the decoder 12. The address, data and control bus of the UEVM 16 is connected to the address, data and control bus of the memory device 15. The control output of the UEVM 16 is connected to the control input of the beamforming processor PFDN 14. The PFDN data input 14 is connected to the first data output of the memory 15, the data output PFDN 14 is connected to the data input of the receiver 17. The second data output of the memory 15 is connected to the data output input of the bus 13, the data input of which is connected to the data input of the memory 15. Data output output the data bus 13 is connected to the input 8 of the data input bus BZPI 20, with the data input 5 of each BDSA 23, with the data input of the signal register of the auto tracking period 36, with the input of the register signal of the antenna guidance signal in azimuth 24 and with the input of the antenna signal signal register register angle places 25.

The first output of the address decoder (DSA) 12 is connected to the control input of the signal register of the auto tracking period 36; the second output of the DCA 12 is connected to the control input of the key 21; the third output of the DCA 12 is connected to the input 12 of the start signal of the session BZPI 20, with the second input of the OR circuit 37 and with the input 6 of the start signal of the session of each BDSA 23; The 4th output of the DCA 12 is connected to the input 9 of the signal of the end of the session BZPI 20 and to the input 7 of the signal of the end of the session of each BDSA 23; The 5th output of the DCA 12 is connected to the input 7 of the signal for entering the code of the sampling period of the BZPI 20 and to the input 8 of the signal for entering the code of the code of the sampling period of each BDSA 23; The 6th output of the DCA 12 is connected to the input 6 of the input signal for the delay code of the ADC BZPI 20 and to the input 9 of the input signal for the input of the delay code for the ADC of each BDSA 23; The 7th output of the DCA 12 is connected to the input 2 of the signal input of the time code for the prohibition of the pulse BZPI 20 and to the input 10 of the signal input of the code for the time of the pulse inhibit each BDSA 23; The 8th output of the DCA 12 is connected to the input 1 of the input signal delay code BZPI 20; The 9th output of the DCA 12 is connected to the control input of the antenna guidance signal register in azimuth 24; The 10th output of the DCA 12 is connected to the control input of the antenna guidance signal register at elevation 25; output [10 + 18 · i + 9 · (j – 1) +1] DSA 12 is connected to input 11 of the output signal of the digital signal of the reference number of the information channel of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +2] DSA 12 is connected to input 12 of the output signal of the digital signal of the reference signal of the information channel of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +3] DSA 12 is connected to input 13 of the input signal of the delay code of the information channel of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; the output [10 + 18 · i + 9 · (j – 1) +4] DSA 12 is connected to the input 14 of the signal output of the digital signal of the reference number of the auto tracking channel ahead of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +5] DSA 12 is connected to the input 15 of the output signal of the digital signal of the reference signal of the auto tracking channel ahead of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +6] DSA 12 is connected to input 16 of the input signal of the delay code of the auto-tracking channel ahead of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +7] DSA 12 is connected to the input 17 of the signal output of the digital signal of the reference number of the auto tracking channel with the lag of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +8] DSA 12 is connected to input 18 of the output signal of the digital signal of the reference signal of the auto tracking channel with the lag of the jth BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1; output [10 + 18 · i + 9 · (j – 1) +9] DSA 12 is connected to the input 19 of the signal for entering the delay code of the auto tracking channel with the lag of the jth BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1.

 The output of 3 delayed sampling pulses in the BZPI 20 is connected to the counting input of the counter of the auto tracking period 34, the output 4 of the signal of the reference number of the BZPI 20 is connected to the data input of the key 21, the output 5 of the signal of the interruption of the counting signal of the BZPI 20 is connected to the 2nd interrupt input of the UEVM 16.

The output of the auto-tracking period counter 34 is connected to the first input of the auto-tracking period comparison circuit 35, the second input of which is connected to the output of the auto-tracking period signal register 36, and the output is connected to the first input of the OR 37 circuit and to the first interrupt input of the WUEM 16. The output of the OR 37 circuit is connected to the input of resetting the counter of the auto tracking period 34.

The output 20 of the signal of the interruption of the reading of the information channel of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, connected to the input [2 + 6 · i + 3 · (j – 1) +1] of interruption of the computer 16; output 21 of the signal for interrupting the reference of the auto tracking channel ahead of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, connected to the input [2 + 6 · i + 3 · (j – 1) +2] of the interruption of the computer 16; output 22 of the signal of the interruption of the reference of the auto tracking channel with the lag of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, connected to the input [2 + 6 · i + 3 · (j – 1) +3] of the interruption of the computer 16.

The output of the antenna guidance signal register in azimuth 24 is connected to the input of the digital-to-analog converter (DAC) 26, the output of which is connected to the low-pass filter of the low-pass filter 28. The antenna guidance signal output register at elevation angle 25 is connected to the input of the DAC 27, the output of which is connected to LPF 29. The output of the LPF 28 is connected to the input of each electric machine amplifier of the EMU azimuth channel 30. The output of the LPF 29 is connected to the input of each electric machine amplifier of the elevation channel of the EMU 31. The output of each electric machine amplifier of the azimuth channel of the EMU 30 is connected to the input m azimuth drive 32 corresponding to the antenna 1. The output of each amplifier channel dynamoelectric elevation angle ECU 31 is connected to the drive input in elevation corresponding antenna 33 1.

The circuit of the signal sampling unit of the antenna 23 is shown in FIG. 17, where three sampling channels (information channel and two auto-tracking channels with sampling ahead and backward) contain three analog-to-digital converters 10-1, 10-2, and 10-3, one for each sampling channel, three pulse sequence delay units (BZPI) - 20-1, 20-2, 20-3, one for each sampling channel, three index signal keys 21-1, 21-2, 21-3, one in each sampling channel and three counting signal keys 22- 1, 22-2, 22-3, one in each sampling channel, and the signal input 1 of the BDSA 23 is connected to the signal th input of each ADC 10-1, 10-2, 10-3. The input of the phasing pulses 2 in BDSA 23 is connected to the input of the phasing pulses 10 of each BZPI 20-1, 20-2, 20-3. The input of sampling pulses 3 in BDSA 23 is connected to the input of 11 sampling pulses of each BZPI 20-1, 20-2, 20-3.

The output of 3 delayed sampling pulses of each BZPI 20-1, 20-2, 20-3 is connected to the input of the sampling pulses of the ADC 10-1, 10-2, 10-3 of the corresponding BDSA sampling channel. In each sampling channel, the output of the corresponding ADC 10-1, 10-2, 10-3 is connected to the data input of the corresponding key of the reference signal 22-1, 22-2, 22-3, and the output of each of these keys is connected to the data output 4 BDSA .

In each BZPI 20-1, 20-2, 20-3, the output 4 of the signal of the reference number is connected to the data input of the corresponding signal key of the index 21-1, 21-2, 21-3, and the output of each of these keys is connected to the data output 4 BDSA.

The output 5 of the signal of the interruption of the counting of the information channel BZPI 20-1 is connected to the output 20 of the signal of the interruption of the counting of the information channel BDSA 23.

The output 5 of the signal of the interruption of the countdown of the auto-tracking channel ahead of the BZPI 20-2 is connected to the output 21 of the signal of the interruption of the countdown of the auto-tracking channel ahead of the BDSA 23.

The output 5 of the signal of the interruption of the countdown channel of the auto-tracking with a lag BZPI 20-3 is connected to the output 22 of the signal of the interruption of the countdown of the channel of the auto-tracking with a lag BDSA 23.

Data input 5 BDSA 23 is connected to the input 8 of the data input bus of each BZPI 20-1, 20-2, 20-3. The input 6 of the signal to start the session BDSA 23 is connected to the input 12 of the signal to start the session BZPI 20-1, 20-2 and 20-3. The input 7 of the signal of the end of the session BDSA 23 is connected to the input 9 of the signal of the end of the session BZPI 20-1, 20-2 and 20-3. The input 8 of the input signal of the code of the sampling period code BDSA 23 is connected to the input 7 of the signal input of the code of the sampling period BZPI 20-1, 20-2, 20-3. The input 9 of the input signal of the ADC delay code in the BDSA 23 is connected to the input 6 of the input signal of the ADC delay code in the BZPI 20-1, 20-2, 20-3. Input 10 of the input signal of the time code for inhibiting the pulse of the BDSA 23 is connected to the input 2 of the signal for entering the code of the time of the pulse inhibit BZPI 20-1, 20-2, 20-3.

The input 11 of the output signal of the digital signal of the reference number of the information channel BDSA 23 is connected to the control input of the key 21-1. The input 12 of the output signal of the digital reference signal of the information channel BDSA 23 is connected to the control input of the key 22-1. The input 13 of the input signal delay code information channel BDSA 23 is connected to the input 1 of the input signal delay code BZPI 20-1.

The input 14 of the output signal of the digital signal of the reference number of the auto tracking channel ahead of the BDSA 23 is connected to the control input of the key 21-2. The input 15 of the output signal of the digital reference signal of the auto tracking channel ahead of the BDSA 23 is connected to the control input of the key 22-2. The input 16 of the input signal delay code channel auto tracking ahead of BDSA 23 is connected to the input 1 of the input signal delay code BZPI 20-2.

The input 17 of the output signal of the digital signal of the reference number of the auto tracking channel with a lag of the BDSA 23 is connected to the control input of the key 21-3. The input 18 of the output signal of the digital signal of the reference channel of the auto tracking with a lag BDSA 23 is connected to the control input of the key 22-3. The input 19 of the input signal delay code channel auto-tracking with a lag BDSA 23 is connected to the input 1 of the input signal delay code BZPI 20-3.

The circuit of the pulse sequence delay unit (BZPI) is shown in FIG. 18, where 38-1, 38-2, 38-3, 38-4, 38-5 are the OR circuits, 39 are the trigger, 41-1, 41-2 are the I circuits, 40-1, 40-2, 40 -3, 40-4 - pulse delay blocks, 42 - counter. Input 1 of the input signal delay code BZPI is connected to input 5 of the signal input of the new delay block delay pulses (BZI) 40-1. Input 2 of the input signal of the time code for the prohibition of the impulse delay of the BZPI is connected to the input 5 of the signal for inputting the new delay of the BZI 40-2. The input 6 of the input signal of the ADC delay code in the BZPI is connected to the input 5 of the input signal of the new delay of the BZI 40-4. The input 7 of the input signal of the code of the sampling period of the BZPI is connected to the input 5 of the input signal of the new delay of the BZI 40-3. The input 8 of the data input bus BZPI is connected to the input 6 of the signal code of the new delay blocks BZI 40-1, 40-2, 40-3, 40-4. The input 9 of the signal of the end of the session BZPI connected to the input 8 of the prohibition of counting block BZI 40-3, used to delay the sampling pulses, and with the first input of the circuit OR 38-2. The input 10 of the phasing pulses BZPI is connected to the input 1 of the phasing pulses of the blocks BZI 40-1, 40-2, 40-3, 40-4. The input 11 of the sampling pulses BZPI connected to the first input of the circuit And 41-1. The input 12 of the start signal of the BZPI session is connected to the input of zeroing of the counter 42, with the first inputs of the OR 38-4, 38-5 circuits and with the first input of the OR 38-1 circuit, the output of which is connected to the input of the zeroing pulse 2 of the BZI 40-1, with the input 4 input signals of the current delay code BZI 40-1, BZI 40-2, BZI 40-3, BZI 40-4 and with a single trigger input 39, a single output of which is connected to the second input of the And 41-1 circuit, the output of which, in its the queue is connected to input 9 of the input pulse BZI 40-1. The output 3 of the delayed pulse BZI 40-1 is connected to the second input of the OR 38-1 circuit, with the second input of the OR 38-2 circuit, with the first input of the OR 38-3 circuit and with the input 9 of the input pulse BZI 40-3.

The output 10 of the state for enabling the counting of the BZI 40-1 is connected to the zero input of the trigger 39. The output of the OR 38-2 circuit is connected to the input 8 of the prohibition of counting the BZI 40-1. The output 3 of the delayed pulse of the BSI 40-3 is connected to the second input of the OR 38-3 circuit, the output of which is connected to the input 2 of the zero pulse of the BSI 40-3 and the first input of the AND 41-2 circuit. The output 3 of the delayed pulse BZI 40-2 is connected to the second input of the circuit OR 38-4. The output of the OR 38-4 circuit is connected to the input 2 of the zeroing pulse of the BZI 40-2 and to the input 8 of the prohibition of calculating the BZI 40-2. The output 7 of the state of the prohibition of counting the BZI 40-2 is connected to the second input of the AND 41-2 circuit, the output of which is connected to the counting input of the counter 42, with the input 9 of the input pulse of the BZI 40-2, with the input 9 of the input pulse of the BZI 40-4 and with the output 3 delayed sampling pulses block BZPI. The output 3 of the delayed pulse BZI 40-4 is connected to the second input of the OR 38-5 circuit, with the input 8 of the prohibition of counting the BZI 40-4 and with the output 5 of the interrupt signal of the BZPI index. The output of the OR 38-5 circuit is connected to the input 2 of the pulse zeroing BZI 40-4. The output of the counter 42 is connected to the output 4 of the signal index BZPI.

The circuit of the pulse delay block (BZI) is shown in FIG. 19, where 43 is the I circuit, 44 is the counter, 45 is the comparison circuit, 46 is the register of the delay period, 47 is the buffer register of the delay period, 48 is the trigger, and the input 1 of the phasing pulse of the BZI is connected to the first input of the circuit And 43, input 2 the zero reset pulse of the BZI is connected to the input of the zeroing of the counter 44, the input 4 of the signal input of the current delay code code The BZI is connected to the control input of the delay period register 46, the input 5 of the new delay code input signal is connected to the control input of the buffer register of the delay period 47, input 6 of the new code signal delayed BZI connected to the input of the buffer register data of the delay period 47, the input 8 of the prohibition of counting is connected to the zero input of the trigger 48, the input 9 of the input pulse of the BZI is connected to the single input of the trigger 48, the single output of the trigger 48 is connected to the second input of the circuit And 43 and with the output 10 of the state of the resolution of counting the BZI , the zero output of flip-flop 48 is connected to the output 7 of the state for inhibiting the counting of BZI, the output of circuit I 43 is connected to the counting input of the counter 44, the output of which is connected to the first input of the comparison circuit 45, the output of the delay period register 46 is connected to the second input a comparison circuit 45, the output of which is connected to the output 3 of the delayed pulse BZI.

When implementing the proposed method and the operation of the proposed device, before the start of the communication session with the spacecraft, the antenna 1 of the lattice (see Fig. 16) is guided by target designation to a point in the celestial sphere with a given elevation and azimuth corresponding to the beginning of the radio visibility zone of the spacecraft.

Further, UEVM 16 introduces into the blocks of the proposed device digital signals corresponding to the values of the source data for conducting a communication session with the spacecraft in the following, for example, order: generates a digital signal on its bus address, data and control with the value of the cell address where the digital signal is stored with the value of the sampling period Dt _d . Under the influence of this address signal, the memory device 15 generates on its second data output a digital signal with a value of the sampling period Dt _d , which is fed to the input of the data output bus 13, from the output of the data output of which a digital signal with a value of the sampling period Dt _d is input 8 the data input bus of the delay block of the pulse sequence BZPI 20, to the data input 5 of the j-th block of the signal sampling unit BDSA 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to the input 8 of the BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the signal code of the new delay of the block of delay of the pulse of the BZI 40-3 (see Fig. 18), from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Next, the UEWM 16 generates on its first address bus a digital signal with a value of 5, which is fed to the input of the decoder 12, from the 5th output of which a single control signal is fed to the input 7 of the delay block of the pulse sequence BZPI 20 (see Fig. 16), input 8 of the j-th block of signal sampling of the BDSA antenna 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to the input 7 of the BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 5 of the input signal of the new delay of the delay block of the pulse of the BZI 40-3 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and remembers a digital signal with a value of the sampling period Dt _d .

Next, the UEM 16 generates a digital signal with a cell address value on its bus of the address, data, and control, where the digital signal with the ADC delay value Dt _{ADC is} stored. Under the influence of this address signal, the storage device ZU 15 generates on its second data output a digital signal with an ADC delay value Dt _ADC , which is fed to the data output terminal of bus 13, from the data output output of which a digital signal with an ADC delay value Dt _ADC is input 8 the data input bus of the delay block of the pulse sequence BZPI 20, to the data input 5 of the j-th block of the signal sampling unit BDSA 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to input 8 of the data input bus BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the new delay code signal block delay pulses BZI 40-4 (see Fig. 18), from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Next, UEVM 16 generates on its first address bus a digital signal with a value of 6, which is input to the decoder 12, from the 6th output of which a single control signal is input to input 6 of the delay block of the pulse sequence BZPI 20 (see Fig. 16), input 9 of the j-th BDSA 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to the input 6 of the BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 5 of the pulse delay block of the BZI 40-4 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and stores a digital signal with the value of the delay of the ADC Dt _ADC .

Next, the computer 16 generates on its bus address, data and control a digital signal with the value of the address of the cell where the digital signal with the value of the pulse inhibit time Dt _{prohibition is} stored. Under the influence of this address signal, the memory device 15 generates at its second data output a digital signal with a pulse inhibit time value Dt of a _ban , which is fed to the data output input of bus 13, from the data output output of which a digital signal with a pulse inhibit time Dt of a _{ban is} supplied to input 8 of the data input bus of the delay block of the pulse sequence BZPI 20, to the data input 5 of the j-th BDSA 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to input 8 of the БЗПИ 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the pulse delay block БЗИ 40-2 (see Fig. 18), from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Next, the UEWM 16 generates on its first address bus a digital signal with a value of 7, which is fed to the input of the decoder 12, from the 7th output of which a single control signal is fed to the input 2 of the delay block of the pulse sequence BZPI 20 (see Fig. 16), input 10 of the j-th BDSA 23 of the i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to input 2 of the BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 5 of the pulse delay block of the BZI 40-2 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and stores a digital signal with the value of the time of the prohibition of the pulse Dt _prohibition .

Further, the UEWM 16 generates a digital signal with a cell address value on its address, data and control bus, where a digital signal with a delay time of the processing of the readings of one wavefront in the information channels Дt _{zобрИ is stored} . Under the influence of this address signal, the storage device ZU 15 generates a digital signal on its second data output with a delay time for processing the readings of one wavefront in the information channels Дt _zобрИ , which is fed to the data output input of bus 13, from the data output output of which a digital signal value Dt _{zobrI is} fed to input 8 of the delay block of the pulse sequence of the BZPI 20 and then to input 6 of the block of the delay of the pulse of the BZI 40-1 (see Fig. 18), from which it passes to the input of the buffer register data ode delay 47 (see FIG. 19).

Next, the UEWM 16 generates on its first address bus a digital signal with a value of 8, which is fed to the input of the decoder 12, from the 8th output of which a single control signal is fed to the input 1 of the delay block of the pulse sequence BZPI 20 (see Fig. 16) and further to input 5 of the pulse delay block БЗИ 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters from his entrance data and stores a digital signal with a delay value of the start time of processing the samples of one wave front in the information channels Дt _zобрИ .

Further, the UUVM 16 generates a digital signal with a cell address value on its address, data and control bus where the digital signal with the value M _{dAC of the} number of sampling periods Dt _d in the time period of processing the samples from the auto tracking channels T _{AC is} stored. Under the influence of this address signal, the memory device 15 generates at its second data output a digital signal with a value of M _dAS , which is fed to the data output input of the bus 13, from the output of the data output of which a digital signal with a value of M _{dAS is} fed to the data input of the auto tracking period signal register 36 (see FIG. 16).

Next, the UEWM 16 generates on its first address bus a digital signal with a value of 1, which is input to the decoder 12, from the first output of which a single control signal is fed to the control input of the signal register of the auto tracking period 36 (see Fig. 16). Under the influence of a single control signal at its control input, the buffer register of the signal of the auto tracking period 36 enters data from its input and stores a digital signal with the value of the time period for processing the samples from the auto tracking channels in the sampling periods M _dAS .

In addition to the above signals, before the start of the communication session with the spacecraft, the UFA also introduces digital signals of the sampling pulse delay time in the digital information channel and both auto-tracking channels of each BDSA, the values of which are calculated in the control computer 16 according to formulas (1), (3), (4), (45) ÷ (53) at the beginning of the spacecraft radio visibility zone for the corresponding elevation and azimuth angles. Digital signals with the values of the calculated initial delays Dt _zi0 , Dt _zi0AC1 and Dt _zi0AC2 are placed in the corresponding cells of the memory 15.

After that, for each j-th BDSA 23 of each i-th antenna, j = 1, 2; i = 0, 1, ..., N - 1, sequentially perform a series of the following steps.

Step 1: WUEM 16 generates a digital signal with a cell address value on its bus of the address, data and control, where the digital signal with the value of the sampling pulse delay time Дt _{zi0 is stored} in the information channel of the ith antenna. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the initial value of the sampling pulse delay time Дt _zi0 in the digital information channel of the ith antenna, which is fed to the data output input of the bus 13, from the data output output of which is digital the signal with the value of the sampling pulse delay time in the information channel of the i-th antenna is fed to the data input 5 of the j-th BDSA 23 of the i-th antenna, in the BDSA block to the input 8 of the data input bus BZPI 20-1, 20-2, 20- 3 (see Fig. 17) and further to the input 6 of the signal code of the new delay of the delay block of the pulse BZI 40-1 (see Fig. 18), from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Step 2: WUEM 16 generates a digital signal on its first address bus with the value [10 + 18 · i + 9 · (j – 1) +3], which is input to the decoder 12, with [10 + 18 · i + 9 · of the (j – 1) +3] -th output of which a single control signal is input to the input 13 of the j-th BDSA 23 of the i-th antenna, in the BDSA block to the input 1 of the BZPI 20-1, (see Fig. 17) and further on input 5 of the pulse delay block BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and stores a digital signal with the initial value of the sampling pulse delay time Дt _zi0 in the information channel of the ith antenna.

Step 3: WUEM 16 generates a digital signal with a cell address value on its bus address, data and control, where a digital signal with a sampling delay time value Dt _{zi0AC1 is stored} in the auto tracking channel ahead of the ith antenna. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the initial value of the sampling pulse delay time Дt _zi0AC1 in the auto tracking channel ahead of the ith antenna, which is fed to the data output input of bus 13, from the data output output of which a digital signal with a sampling pulse delay time value in the auto tracking channel ahead of the i-th antenna, is fed to the data input of the 5th j-th block of signal sampling of the BDSA antenna 23 of the i-th antenna, in the block e BDSA to the input 8 of the data input bus BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the signal code of the new delay of the delay block pulse delay BZI 40-1 (see Fig. 18) , from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Step 4: WUEM 16 generates a digital signal on its first address bus with the value [10 + 18 · i + 9 · (j – 1) +6], which is input to the decoder 12, with [10 + 18 · i + 9 · of the (j – 1) +6] -th output of which a single control signal is input to the input 16 of the j-th BDSA 23 of the i-th antenna, in the BDSA block to the input 1 of the BZPI 20-2, (see Fig. 17) and further on input 5 of the pulse delay block BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and stores a digital signal with the initial value of the sampling pulse delay time Дt _zi0AC1 in the auto tracking channel ahead of the ith antenna.

Step 5: WUEM 16 generates a digital signal with a cell address value on its address, data and control bus, where a digital signal with a sampling delay time value Dt _{zi0AC2 is stored} in the auto tracking channel with the ith antenna lagging. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the initial value of the sampling pulse delay time Дt _zi0AC2 in the auto tracking channel with the lag of the i-th antenna, which is fed to the data output input of bus 13, from the data output output of which a digital signal with a sampling delay time value in the auto tracking channel with the lag of the ith antenna is fed to the data input 5 of the jth BDSA of the 23rd antenna, in the BDSA block it is fed to input 8 of the input bus d data BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the signal code of the new delay of the delay block of the pulse BZI 40-1 (see Fig. 18), from which it is fed to the data input buffer register delay period 47 (see Fig. 19).

Step 6: UEM 16 generates a digital signal on its first address bus with the value [10 + 18 · i + 9 · (j – 1) +9], which is input to the decoder 12, with [10 + 18 · i + 9 · of the (j – 1) +9] -th output of which a single control signal is input to the 19th junction BDSA 23 of the i-th antenna, in the BDSA block to input 1 BZPI 20-3, (see Fig. 17) and further on input 5 of the pulse delay block BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the delay period 47 enters data from its input and stores a digital signal with the initial value of the sampling pulse delay time Дt _zi0AC2 in the auto tracking channel with the ith antenna lagging.

Upon completion of the input of digital signals with the values of the source data, immediately before the start of the communication session at the beginning of the radio visibility zone of the spacecraft, a signal for the beginning of the session is issued to all BZPI blocks. To this end, the UEMU 16 generates a digital signal with a value of 3 on its first address bus, which is fed to the input of the decoder 12, from the 3rd output of which a single control signal of the beginning of the session is fed to the second input of the OR circuit 37, through it to the input of the counter zero 34 and sets a digital signal in it with a zero value, in addition, this single control signal of the beginning of the session is fed to input 12 of the delay block of the pulse sequence BZPI 20 (see Fig. 16), to input 6 of each j-th BDSA 23 in the path of each i-th antennas, j = 1, 2; i = 0, 1, ..., N - 1, in each BDSA block to the input 12 of the BZPI 20-1, 20-2, 20-3 (see Fig. 17) and in each BZPI to the first input of the OR 38-1 circuits , 38-4, 38-5 and to the input of zeroing of the counter 42, setting the zero value of the signal of index k in it (see Fig. 18). A single control signal from the output of the OR 38-1 circuit is supplied to the single input of the trigger 39 and translates it into a single state. From the outputs of the OR 38-1, 38-4, 38-5 circuits, a single control signal is fed to the zeroing input 2 of the BSI 40-1, 40-3, 40-2, 40-4 and in each BSI it is fed to the counter zeroing input 44 ( see Fig. 19) and sets in it a digital signal with a zero value. In addition, from the output of the OR 38-1 circuit, a single control signal is fed to input 4 of the input signal of the current delay code of the BZI 40-1, 40-2, 40-3, 40-4 (see Fig. 18) and in each BZI to the control input of the register of the delay period 46 (see Fig. 19) and enters into it a digital signal with the current value of the delay period from the output of the buffer register of the delay period 47, into which this signal was previously entered from the WEM 16. In addition, from the output of the circuit OR 38-4, a single control signal is fed to input 8 of the prohibition of counting BZI 40-2 (see Fig. 18) and then to the zero input trigger 48 (see. FIG. 19), setting it to zero state, then the single signal from the zero output of the trigger 48 is output 7 prohibition condition calculation Bzi 40-2 and further the second input of the AND circuit 41-2.

Thus, under the influence of the signal of the beginning of the session in the UVA, the preparatory operations are completed and the operations of phasing signals from different antennas and auto-tracking of the spacecraft begin.

As in the prototype, the wavefront of the radio signal with a shift for antenna No. i, i = 0, 1, ..., N – 1, falls on the antenna 1 of the grating for the time of the difference in the path of the rays Дt _io relative to the reference antenna No. 0. The received signal is amplified in the corresponding LNA 2, the frequency is reduced to the first intermediate frequency using the first local oscillator 4 and the mixer 3-1, amplified and limited in frequency band using the IF-PF 5-1, forked into two signals by a divider 6 and further, unlike prototype, form quadrature signals on the second intermediate the moose with the help of mixers 3-2, the second local oscillator 8 and a constant phase shifter at 90 ° 9.

At the 1st block of signal sampling, the BDSA antenna 23 of the i-th antenna, i = 0, 1, ..., N – 1, under the influence of phasing pulses with a repetition rate f _f from the GTI 11, arriving at the 2nd input of the BDSA, and pulses discretization from the output of the counter-divider 19 with a repetition rate f _d arriving at the 3rd input of the BDSA, in accordance with expression (7) form digital samples of the sine quadrature of the received signal in the information channel S _ik at times t _ik = t _Гk + Dt _zik = t _UVAik + Dt _p ; in accordance with the expression (9) is formed readings S _ik- sine quadrature received signal in a channel in autotracking ahead _ikAS1 instants t = t + dt _{gk zikAS1 gk} = t + dt _zik - _none dt = t + dt _{UFAik n} - dt _none ; in accordance with the expression (11) is formed readings S _{ik +} sine quadrature received signal in the channel auto-tracking with a lag in time points t _ikAS2 = t _gk + dt _zikAS2 = t _gk + dt _zik + dt _none = t _UFAik + dt _n + dt _none.

On the 2nd block of sampling the signal of the BDSA antenna 23 of the i-th antenna, i = 0, 1, ..., N – 1, under the influence of phasing pulses with a repetition rate f _f from the GTI 11, arriving at the 2nd input of the BDSA, and pulses discretization from the output of the counter-divider 19 with a repetition rate f _d arriving at the 3rd input of the BDSA, in accordance with expression (8) form digital samples of the cosine quadrature of the received signal in the information channel S _90ik at times t _ik = t _Гk + Dt _zik = t _UVAik + Dt _p ; in accordance with the expression (10) is formed readings S _90ik- cosine quadrature received signal in a channel in autotracking ahead _ikAS1 instants t = t + dt _{gk zikAS1 gk} = t + dt _zik - _none dt = t + dt _{UFAik n} - dt _none ; in accordance with the expression (12) is formed readings S _{90ik +} cosine quadrature received signal in the channel auto-tracking with a lag in time points t _ikAS2 = t _gk + dt _zikAS2 = t _gk + dt _zik + dt _none = t _UFAik + dt _n + dt _none.

To do this, in one of the three delay units of the pulse sequence of the BZPI pulses that are part of the BDSA, for example 20-1 (see Fig. 17), under the influence of phasing pulses arriving at input 10 of the block 20-1 from the input 2 of the BDSA and sampling pulses, arriving at input 11 of block 20-1 from input 3 of BDSA, form a sequence of sampling pulses delayed by the time interval Дt _zik , and apply sampling pulses of this delayed sequence to the input of sampling pulses of the ADC 10-1, to the signal input of which the received ith antenna a sine quadrature signal for the 1st BDSA and a cosine square signal for the 2nd BDSA from the signal input 1 BDSA. The discrete reference signal from the output of the ADC 10-1 is fed to the data input of the key of the reference signal 22-1.

In parallel with the output 4 of the BZPI 20-1, a reference index signal with a value of k is supplied to the input of the key data 21-1, and from the output 5 of the BZPI 20-1, an interrupt signal is sent to the output of the BDSA 20, which is then fed to [2 + 6 · i + 3 · (j – 1) +1] -th input of the interrupt signal about the readiness of the countdown of the information channel of the computer 16 for the j-th BDSA, j = 1, 2; i = 0, 1, ..., N – 1.

Under the influence of the interrupt signal about readiness of counting at its [2 + 6 · i + 3 · (j – 1) +1] -m input of the interrupt signal about readiness of counting, the UEUM 16 generates a signal with the value [10 + 18 · i + 9 · (j – 1) +1], which is input to the decoder 12, with the [10 + 18 · i + 9 · (j – 1) +1] output of which a single control signal is supplied to the 11th the input of the j-th BDSA23 of the i-th antenna (see Fig. 16) and then to the control input of the key 21-1 (see Fig. 17). Under the influence of a single control signal, the key 21-1 passes the reference index signal with value k to the data output 4 of the jth BDSA of the i-th antenna and then to the data input of the data bus 13 (see Fig. 16), from the data input of which the reference index signal with a value of k from the j-th BDSA of the i-th antenna is fed to the data input of the memory 15, where under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, this discrete signal is recorded in the cell the current reference index of the information channel of the i-th antenna.

Further, the UEM 16 generates on its first address bus a signal with the value [10 + 18 · i + 9 · (j – 1) +2], which is input to the decoder 12, with [10 + 18 · i + 9 · (j –1) of the +2] -th output of which a single control signal is supplied to the 12th input of the j-th BDSA 23 of the i-th antenna (see Fig. 16) and then to the control input of the key 22-1 (see Fig. 17 ) Under the influence of a single control signal, the key 22-1 passes a discrete signal of counting of the information channel to the data output 4 of the jth BDSA of the i-th antenna and then to the data input of the data bus 13, from the output of the data input of which a discrete signal of reading of the information channel of the j-th BDSA of the i-th antenna is fed to the data input of the memory 15 (see Fig. 16), where under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, this discrete signal is recorded in the cell of the indexed array i antenna with current m index k counting information channel.

Similarly, S _ik– samples of the sine quadrature of the received signal, S _90ik– cosine samples of the signal and their indices in the auto-tracking channel are formed and recorded in the memory 15 _{ahead of the curve} .

For this, in one of the remaining two delay units of the pulse sequence of the BZPI, which are part of the j-th BDSA of the i-th antenna, j = 1, 2; i = 0, 1, ..., N – 1, for example, 20-2 (see Fig. 17), under the influence of phasing pulses arriving at input 10 of block 20-2 from input 2 of the jth BDSA of the ith antenna and pulses sample arriving at the input of block 11 with input 20-2 3 j-th BDSA i-th antenna, the sampling pulse sequence is formed, delayed by the time interval (dt _zik - _none dt), and the sampling pulses supplied to this sequence delayed by the sampling pulse input ADC 10-2, the signal input of which receives the signal received by the i-th antenna from the signal input 1 of the j-th BDSA of the i-th antenna s. A discrete reference signal from the output of the ADC 10-2 is fed to the input of the key data of the reference signal of the auto-tracking channel ahead of 22-2.

In parallel with the output 4 of the BZPI 20-2, the signal of the reference index of the auto-tracking channel ahead of the value k is sent to the input of the key data 21-2, and from the output 5 of the BZPI 20-2, an interrupt signal is sent to the output of the 21st ADS of the ith antenna, which is then fed to the [2 + 6 · i + 3 · (j – 1) +2] th input of the interrupt signal about the readiness of the countdown of the auto tracking channel ahead of UEM 16 (see Fig. 16).

Under the influence of the interrupt signal about the readiness of the auto-tracking channel counting ahead of time on its [2 + 6 · i + 3 · (j – 1) +2] -m input of the interruption signal about the readiness of the auto-tracking channel counting ahead of the UEVM 16 generates on its first address bus a signal with the value of [10 + 18 · i + 9 · (j – 1) +4], which is input to the decoder 12, with the [10 + 18 · i + 9 · (j – 1) +4] -th output of which a single control signal is supplied to the 14th input of the j-th BDSA 23 of the i-th antenna and then to the control input of the key 21-2 (see Fig. 17). Under the influence of a single control signal, the key 21-2 passes the signal of the reference index of the auto tracking channel ahead of the value k to the data output 4 of the j-th BDSA of the i-th antenna and then to the data input of the data bus 13, from the output of the data input of which the reference index signal with a value of k from the j-th BDSA of the i-th antenna is fed to the data input of the memory 15, where under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, that discrete signal is recorded in the cell of the current reference index auto-channel roving ahead of the i-th antenna.

Further, UEVM 16 forms on its first address bus a signal with the value [10 + 18 · i + 9 · (j – 1) +5], which is input to the decoder 12, with [10 + 18 · i + 9 · (j –1) of the +5] -th output of which a single control signal is supplied to the 15th input of the j-th BDSA 23 of the i-th antenna (see Fig. 16) and then to the control input of the key 22-2 (see Fig. 17 ) Under the influence of a single control signal, the key 22-2 passes a discrete counting signal of the auto tracking channel ahead of the data output 4 of the jth BDSA of the i-th antenna and then to the data input input of the data bus 13, from the data input output of which a discrete counting signal of the auto tracking channel with ahead of the j-th BDSA of the i-th antenna it enters the data input of the memory 15, where under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, this discrete signal is recorded in the indexed mass cell wa i-th antenna with the current index k reference channel automatic tracking ahead.

Similarly, samples S _{ik + of the} sine square of the received signal, samples S _{90ik + of the} cosine square of the received signal and their indices in the auto-tracking channel with a lag are formed and recorded in the memory 15.

To do this, in the remaining delay block of the pulse sequence of the BZPI, which is part of the j-th BDSA of the i-th antenna, for example 20-3 (see Fig. 17), under the influence of phasing pulses arriving at input 10 of block 20-3 from input 2 j-th BDSA i-th antenna and a sampling pulse input at the input unit 11 to input 20-3 3 j-th BDSA i-th antenna, the sampling pulse sequence is formed, delayed by the time interval (dt _{none zik} + dt), and apply sampling pulses of this delayed sequence to the input of ADC 10-3 sampling pulses, to a signal ny input of which is fed the received i-th antenna signal from the signal input 1 j-th BDSA i-th antenna. A discrete reference signal from the output of the ADC 10-3 is fed to the input of the key data of the reference signal of the auto-tracking channel with a lag of 22-3.

In parallel with the output 4 of the BZPI 20-3, the signal of the reference index of the auto-tracking channel with a lag with a value of k is sent to the input of the key data 21-3, and from the output 5 of the BZPI 20-3, an interrupt signal is sent to the output of the j-th BDSA of the ith antenna which is then fed to the [2 + 6 · i + 3 · (j – 1) +3] th input of the interrupt signal about the readiness of the countdown of the auto tracking channel with the UEM 16 behind (see Fig. 16).

Under the influence of the interrupt signal about the readiness of the countdown of the auto-tracking channel with a lag at its [2 + 6 · i + 3 · (j – 1) +3] -th input of the interrupt signal about the readiness of the countdown of the auto-tracking channel, the UEUVM 16 forms on its first address bus a signal with the value of [10 + 18 · i + 9 · (j – 1) +7], which is input to the decoder 12, with the [10 + 18 · i + 9 · (j – 1) +7] -th output of which a single control signal is supplied to the 17th input of the j-th BDSA 23 of the i-th antenna and then to the control input of the key 21-3 (see Fig. 17). Under the influence of a single control signal, the key 21-3 passes the signal of the reference index of the auto-tracking channel with a lag with a value of k to the data output 4 from the j-th BDSA of the i-th antenna and then to the data input input of the data bus 13, from the data input output of which the index signal of the sample with the value k of the j-th BDSA of the i-th antenna is fed to the data input of the memory 15, where, under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, this discrete signal is recorded in the cell of the current reference index auto channel Activity with a lag i-th antenna (see. Fig. 16).

Further, the UEM 16 generates on its first address bus a signal with the value [10 + 18 · i + 9 · (j – 1) +8], which is input to the decoder 12, with [10 + 18 · i + 9 · (j –1) of the +8] -th output of which a single control signal is supplied to the 18th input of the j-th BDSA 23 of the i-th antenna and then to the control input of the key 22-3 (see Fig. 17). Under the influence of a single control signal, the key 22-3 passes a discrete signal of the reference of the auto tracking channel with a lag to the data output of the 4th jth BDSA of the i-th antenna and then to the data input of the data bus 13, from the data input of which the discrete reference signal of the auto tracking channel with the lag of the jth BDSA of the i-th antenna arrives at the data input of the memory 15, where under the influence of the address signal supplied from the address bus, data and control of the computer 16 to the address bus of the memory 15, this discrete signal is recorded in the indexed mass cell va i-th antenna to the current index k autotracking reference channel with a delay (see. Fig. 16).

In parallel, at the output of 3 delayed pulses in the delay block of the sequence of pulses BZPI 20 under the influence of phasing pulses with a repetition rate f _f from the GTI 11, arriving at the 10th input of the BZPI 20, and sampling pulses from the output of the counter-divider 19 with a repetition rate f _d , arriving at the 11th input BZPI 20, form a sequence of pulses, delayed with respect to the sampling pulses output from the counter-divider 19 to start processing delay time of readout of the wave front in the information channels dt _zobrI selected th according to the equation (17), and fed pulses of the delayed sequence to the counting input of the counter 34.

In parallel with the output 4 of the BZPI 20, an impulse index signal with the next value of k is supplied to the data input of the key 21, and the output of the interrupt signal 5 of the BZPI 20 provides an interrupt signal to the 2nd input of the interrupt signal of the computer 16.

Under the influence of the interrupt signal at its 2nd input of the interrupt signal about readiness of counting, the UEM 16 generates a signal with the value 2 on its first address bus, which is input to the decoder 12, from the 2nd output of which a single control signal is supplied to the control input of the key 21 . Under the influence of a single control signal, the key 21 passes the signal of the reference index with a value of k to the data input of the data bus 13, from the output of the data input of which the signal of the reference index with the value of k goes to the data input of the memory 15, where Using the address signal supplied from the address bus, data and control of the UEM 16 to the address bus of the memory 15, this discrete signal is recorded in the cell of the current index of the total information count of the antenna array.

Further, UEVM 16 generates on its bus addresses, data and control a sequence of address signals and command signals, under the influence of which the memory 15 sequentially outputs digital sine quadrature signals from cells with index k of the index arrays of antennas No.i, i = 0 , 1, ..., N - 1. At the same time, the UEM 16 provides, through its control output, to the control input of the beamforming processor PFDN 14 a sequence of signals of addition commands, under the influence of which PFDN 14 sequentially enters numbers equal sine quadrature signals with an index k of information channels of antennas No.i, i = 0, 1, ..., N - 1, and generates a digital sine quadrature signal of index k with a total value

(71)

(71)

At the end of the summing cycle, PFDN 14 generates a total digital sine-square signal S _k to its data output, from where it is fed to the data input of the receiver 17.

Further, the UEUM 16 generates on its bus addresses, data and control a sequence of address signals and command signals, under the influence of which the memory 15 sequentially outputs digital cosine quadrature signals from cells with index k of the index arrays of antennas No. i, i = 0 , 1, ..., N - 1. At the same time, the UEM computer 16 issues a sequence of signals of addition commands through its control output to the control input of the beamforming processor PFDN 14, under the influence of which PFDN 14 sequentially enters numbers new cosine quadrature signals with index k of information channels of antennas No.i, i = 0, 1, ..., N - 1, and generates a digital cosine quadrature signal of index k with the total value

(72)

(72)

At the end of the summation cycle, PFDN 14 generates a total digital cosine square signal S _90k to its data output, from where it goes to the data input of receiver 17.

The counter 34 counts the pulses delayed at the time Дt _zОБИ from the output 3 of the БЗПИ 20, arriving at its counting input until the value of the digital signal at its output matches the value of the digital signal at the output of the signal register of the auto tracking period 36. If the digital values coincide signals from the counter 34 and the signal register of the auto tracking period 36 at its inputs, the comparison circuit 35 generates a single pulse at its output, which is fed to the first input of the OR circuit 37 and to the first input of the interruption of the computer 16. From the output of the circuit we OR 37 a single signal is fed to the input of zeroing the counter of the auto tracking period 34 and sets a digital signal in it with a zero value, thereby preparing for the next auto tracking period.

Under the influence of a single signal at its first interrupt input, the computer 16 extracts from the corresponding memory cell 15 the current index of the total information count of the antenna array k and transfers control to the auto tracking (AC) program for processing the samples of the auto tracking channels of all antenna antennas. The AC program sequentially introduces from the memory 15 digital signals of sine (S _ik– and S _{ik +} ) and cosine (S _90ik– and S _{90ik +} ) quadratures with the index k of auto-tracking channels ahead of and behind the antennas No.i, i = 0, 1, ... , N - 1, and in accordance with expressions (20) ÷ (70) generates digital control signals Δu _{ACΦk of} pointing the antennas in elevation angle C and Δu _{ACΨk of} pointing the antennas in azimuth W, as well as digital signals Dt _сi0k of the time shift of the radio signal arrival between antennas A _i and A ₀ and in accordance with formulas (1), (3), (4) generates digital signals with current values E delays the sampling pulse in the information channels dt _zik, in channels autotracking ahead _zikAS1 dt = dt _zik - dt and _none in autotracking channels with a delay dt = dt _{zikAS2 zik} + dt _none for all antennas №i, i = 0, 1, ... , N - 1.

Then, the UUVM 16 initiates the generation of the antenna guidance signals of the array in elevation and azimuth, for which it generates a digital signal with a cell address value on its bus address, data and control, where the digital control signal Δu _ACΨk of antenna guidance in azimuth Sh is stored. Under the influence of this address signal storage memory 15 generates at its output a second digital data signal with a value Δu _ASΨk which is input to the data output bus 13, output from the data output wherein the digital control signal Δu induced _ASΨk I antennas in azimuth W enters including antenna pointing signal register data input azimuth 24 (see. Fig. 16). Next, the UEWM 16 generates on its first address bus a digital signal with the value 9, which is fed to the input of the decoder 12, from the 9th output of which a single control signal is fed to the control input of the antenna guidance signal register in azimuth 24. Under the influence of a single control signal the control input register of the antenna guidance signal in azimuth 24 enters data from its input and stores the digital control signal Δu _ACΨk of antenna guidance in azimuth W, which is received from the output of register 24 to the input of the digital a transducer 26, which converts the antenna pointing signal in elevation into an analog form. Through the low-pass filter 28, the analog signal of guiding the antennas in azimuth enters the inputs of the machine amplifiers 30 and, after amplification, enters the drives in azimuth of 32 antennas 1.

Next, the UEWM 16 generates a digital signal on its bus of the address, data, and control with the value of the cell address where the digital control signal Δu _{ACΦk of} pointing the antennas along the elevation angle C is stored. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the value Δu _ACΦk , which is input to the data output input of bus 13, from the output of the data output of which the digital control signal Δu _{ACΦk of} pointing the antennas along the elevation angle C is received, including the signal register data input antenna at an elevation angle of 25 (see FIG. 16). Next, the UUVM 16 generates on its first address bus a digital signal with a value of 10, which is input to the decoder 12, from the 10th output of which a single control signal is fed to the control input of the antenna guidance signal register at elevation angle 25. Under the influence of a single control signal register antenna pointing signal its control input 25, elevation input from its data input and stores the digital control signal Δu _ASΦk guidance antennas at the corner space D, which is output from the register 25 to the input ifroanalogovogo converter 27 which converts antenna pointing signal in elevation in analog form. Through the low-pass filter 29, the analogue antenna pointing signal is elevated along the elevation angle to the inputs of the machine amplifiers 31 and, after amplification, is fed to the actuators along the elevation angle of the 33 antennas 1.

After that, the UUVM 16 initiates the procedure of replacing the digital signals of the sampling pulse delay time in the digital information channel and both auto-tracking channels of each BDSA with signals with the previously calculated values of Dt _zik , Dt _zikAC1 and Dt _zikAC2 , for which, for each i-th antenna, i = 0, 1, ..., N - 1, a series of the following steps:

Step 1: WUEM 16 generates on its bus address, data and control a digital signal with a cell address value, where a digital signal with a sampling delay time value Dt _zik in the information channel of the ith antenna is stored. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the current value of the sampling pulse delay time Дt _zik in the digital information channel of the ith antenna, which is fed to the data output input of the bus 13, from the data output output of which is digital a signal with a delay value of the sampling pulse in the information channel of the i-th antenna is fed to the data input 5 of the first and second sampling units of the signal signal BDSA 23 in the path of each i-th antenna, i = 0, 1, , N – 1 (see FIG. 16), in each BDSA block to input 8 of the data input bus BZPI 20-1, 20-2, 20-3 (see Fig. 17) and then to the input 6 of the new delay code signal block delay pulses BZI 40-1 (see Fig. 18), from which it enters the data input of the buffer register of the delay period 47 (see Fig. 19).

Step 2: WUEM 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 3], which is input to the decoder 12, from the [10 + 18 · i + 3] -th output of which a single control signal is received to the input 13 of the first BDSA 23 in the path of the i-th antenna (see Fig. 16), in the BDSA block it enters the input 1 of the BZPI 20-1, (see Fig. 17) and then to the input 5 of the pulse delay block of the BZI 40- 1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer regis p 47 introduces a delay period to its data input a digital signal and stores the current value of the sampling pulse delay time dt _zik in an information channel i-th antenna.

After that, the computer 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 9 + 3], which is fed to the input of the decoder 12, with a single [10 + 18 · i + 9 + 3] -th output of which the control signal is fed to input 13 of the second BDSA 23 in the path of the i-th antenna (see Fig. 16), in the BDSA block it is fed to input 1 of the BZPI 20-1, (see Fig. 17) and then to input 5 of the pulse delay unit BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer The seventh delay period register 47 inputs data from its input and stores a digital signal with the current value of the sampling pulse delay time Дt _zik in the information channel of the ith antenna.

Step 3: WUEM 16 generates a digital signal with a cell address value on its bus address, data and control, where a digital signal with a sampling delay time value Dt _{zikAC1 is stored} in the auto tracking channel ahead of the ith antenna. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the current value of the sampling pulse delay time Дt _zikAC1 in the auto tracking channel ahead of the ith antenna, which is fed to the data output input of bus 13, from the data output output of which a digital signal with a sampling delay time value in the auto tracking channel ahead of the ith antenna is fed to the data input 5 of the first and second sampling units of the BDSA 23 antenna signal cte of each i-th antenna, i = 0, 1, ..., N – 1 (see Fig. 16), in each BDSA unit, input 8 of the data input bus BZPI 20-1, 20-2, 20-3 ( see Fig. 17) and then to the input 6 of the code signal of the new delay of the delay block of the impulse delay BZI 40-1 (see Fig. 18), from which it enters the buffer data register of the delay period 47 (see Fig. 19).

Step 4: UEM 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 6], which is input to the decoder 12, with the [10 + 18 · i + 6] -th output of which a single control signal is received to the input 16 of the first BDSA 23 in the path of the i-th antenna, in the BDSA block it enters the input 1 of the BZPI 20-2, (see Fig. 17) then to the input 5 of the pulse delay block BZI 40-1 (see Fig. 18) , from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the period z Delay 47 enters data from its input and stores a digital signal with the current value of the sampling pulse delay time Дt _zikAC1 in the auto tracking channel ahead of the ith antenna.

After that, the computer 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 9 + 6], which is input to the decoder 12, with a single [10 + 18 · i + 9 + 6] -th output the control signal is fed to input 16 of the second BDSA 23 in the path of the i-th antenna, in the BDSA block it is fed to input 1 of the BZPI 20-2, (see Fig. 17) and then to input 5 of the pulse delay block of the BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register 47 introduces a delay period from its data input a digital signal and stores the current value of the sampling pulse delay time dt _zikAS1 channel autotracking ahead i-th antenna.

Step 5: WUEM 16 generates a digital signal with a cell address value on its bus address, data and control, where a digital signal with a sampling delay time value Dt _{zikAC2 is stored} in the auto tracking channel with the ith antenna lagging. Under the influence of this address signal, the memory device 15 generates a digital signal on its second data output with the current value of the sampling pulse delay time Дt _zikAC2 in the auto tracking channel with the lag of the ith antenna, which is fed to the data output input of bus 13, from the data output output of which a digital signal with a sampling delay time value in the auto tracking channel with the lag of the i-th antenna is fed to the data input 5 of the first and second sampling units of the BDSA 23 antenna signal in tr kte of each i-th antenna, i = 0, 1, ..., N – 1, in each BDSA block to input 8 of the data input bus BZPI 20-1, 20-2, 20-3 (see Fig. 17) and further to the input 6 of the signal code of the new delay of the delay block of the pulse BZI 40-1 (see Fig. 18), from which it enters the data input of the buffer register delay period 47 (see Fig. 19).

Step 6: UEM 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 9], which is input to the decoder 12, from the [10 + 18 · i + 9] -th output of which a single control signal is received to the input 19 of the first BDSA 23 in the path of the i-th antenna, in the BDSA block it enters the input 1 of the BZPI 20-3, (see Fig. 17) and then to the input 5 of the pulse delay unit BZI 40-1 (see Fig. 18 ), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register of the period Delay 47 enters data from its input and stores a digital signal with the current value of the sampling pulse delay time Дt _zikAC2 in the auto tracking channel with the ith antenna lagging.

After that, the computer 16 generates on its first address bus a digital signal with the value [10 + 18 · i + 9 + 9], which is input to the decoder 12, with a single [10 + 18 · i + 9 + 9] -th output the control signal is fed to input 19 of the second BDSA 23 in the path of the i-th antenna, in the BDSA block it is fed to input 1 of the BZPI 20-3, (see Fig. 17) and then to input 5 of the pulse delay block of the BZI 40-1 (see Fig. 18), from which it arrives (see Fig. 19) to the control input of the buffer register of the delay period 47. Under the influence of a single control signal at its control input, the buffer register 47 introduces a delay period from its data input a digital signal and stores the current value of the sampling pulse delay time dt _zikAS2 channel autotracking with a lag i-th antenna.

After performing the above steps for each i-th antenna, i = 0, 1, ..., N - 1, the UVA repeats the spacecraft auto-tracking cycle.

In the process of UVA operation, each block of delay in the pulse sequence delay BZPI generates at its output 3 a pulse sequence delayed relative to the pulse sequence at the output of the counter-divider 19 for a given time interval, measured in microtacts of the GTI 11. This happens as follows.

In each BZPI (see Fig. 18), the pulse delay block BZI 40-1 delays the pulse from the output of the counter-divider 19 for a given time interval. Starting from this delayed pulse, the BZI 40-3 generates a sequence of pulses with a sampling period of Dt _d , which is delayed relative to the sequence of pulses at the output of the counter-divider 19 for the same specified time interval.

The pulses of the delayed sequence are output 3 BZPI.

In parallel, the counter 42 counts the number of generated sampling pulses and generates a digital signal with the value of the readout index at the output 4 of the BZPI.

In the process of auto tracking, the UEUVM 16 changes the value of the digital signal of the delay time, therefore, the next pulse delayed by the BZI 40-1 unit from the output of the counter-divider 19 may not coincide in time with the next pulse, which forms the BZI 40-3 based on the previously received pulse from the BZI 40-1. Starting from this time-offset pulse, the BZI 40-3 begins to form a new sequence of sampling pulses delayed relative to the sequence of pulses at the output of the counter-divider 19 to a new time interval specified by the value of the digitally updated signal in the buffer register of the delay period 47 BZI 40-1.

BZI 40-2 serves to prevent the double of the sampling pulse when changing delayed pulse sequences when the next pulse delayed in the BZI 40-1 arrives at the BZI 40-3 with some delay relative to the next sampling pulse generated in the BZI 40-3. In this case, the BZI 40-2 during a certain protective period of time generates a zero signal at its output 7, which prohibits the And 41-2 circuit to pass a new delayed pulse coming from the OR 38-3 circuit from the output of the BZI 40-1. Thus, if the next delayed pulse from the output of 3 BZI 40-1 arrives at the first input of the And 41-2 circuit somewhat earlier than the next pulse at the 3rd output of the BZI 40-3, then a new sequence of sampling pulses begins with this newly arrived delayed pulse with output 3 of the BZI 40-1, and if the next delayed pulse from the output 3 of the BZI 40-1 arrives at the first input of the And 41-2 circuit somewhat later than the next pulse at the 3rd output of the BZI 40-3, then a new sequence of sampling pulses begins through the interval sampling time Dt _d pos of this next delayed pulse from the output 3 of the BZI 40-1.

Such an organization of the work of the BZI 40-1, 40-2 and 40-3 prevents the violation of the synchronization of sampling pulses in the paths of various antennas.

Finally, the BZI 40-4 performs the output of the 5 BZPI interrupt on the formation of the next count of the received antenna signal with a delay for the time of the ADC operation relative to the time of the output of the BZPI output 3 of the delayed sampling pulse.

Block delay sequence of pulses BZPI works as follows. After entering to the input 12 of the BZPI a single signal of the beginning of the session, which translates the trigger 39 into a single state, under the influence of a single signal from the single output of the trigger 39 at its second input, the And 41-1 circuit passes to the input 9 of the input pulse of the BZI 40-1 the pulse closest in time received at the input 11 of the sampling pulses of the block БЗПИ from the counter-divider 19. Under the influence of the input pulse from the input 9 БЗИ 40-1 (see Fig. 19) at its single input, the trigger 44 goes into a single state and produces a single signal from its single on the output to the first input of the And 43 circuit and to the output 10 of the resolution state of counting the BSI 40-1. A single signal from the output 10 of the state of the resolution of counting is fed to the zero input of the trigger 39 (see Fig. 18) and puts it in the zero state. In this case, the zero signal from the single output of the trigger 39 enters the second input of the And 41-1 circuit and prevents the passage of subsequent pulses from the input 11 of the sampling pulses through the And 41-1 circuit to the input 9 of the input pulse of the BZI 40-1. A single signal from a single output of flip-flop 48 at the second input of AND 43 circuit allows phasing pulses to pass through it from the 1st input of the BZI 40-1 to the counting input of the counter 44 (see Fig. 19). Counter 44 counts the phasing pulses arriving at its counter input until the value of the digital signal at its output matches the value of the digital signal at the output of the delay period register 46. If the values of the digital signals from the counter 44 and the delay period register 46 match at its inputs, the comparison circuit 45 generates a single pulse at its output, which is fed to the output 3 of the delayed pulse BZI 40-1 (see Fig. 18), from which it goes to the second input of the OR circuit 38-2, to the second input of the OR circuit 38-1, at first in od OR circuit 38-3 and input to 9 input pulse Bzi 40-3. From the output of the OR 38-1 circuit, a single signal is fed to the input of the zeroing pulse 2 of the BZI 40-1, from which it goes to the zeroing input of the counter 44 (see Fig. 19) and sets a digital signal with a zero value in it. In addition, from the output of the OR 38-1 circuit, a single control signal is fed to the input 4 of the input signal of the current delay code BZI 40-1, 40-2, 40-3, 40-4 (see Fig. 18) and in each of these BZI arrives at the control input of the register of the delay period 46 (see Fig. 19) and enters into it a digital signal with the current value of the delay period from the output of the buffer register of the delay period 47, into which this signal was previously entered from the UEM 16. In addition, a single the control signal from the output of the OR 38-1 circuit is supplied to the single input of the trigger 39 and translates it into a single state. From the output of the OR 38-2 circuit, a single signal is fed to input 8 of the prohibition of counting the BZI 40-1 (see Fig. 18) and sets the trigger 48 to the zero state (see Fig. 19). The zero signal from the single output of trigger 48 is fed to the second input of the And 43 circuit and prohibits the passage of phasing pulses from the first input of the BZI 40-1 to the counting input of its counter 44 until the next sampling pulse arrives from the output of the divider counter to the input 11 of the considered BZPI and then to the first input of the I 41-1 circuit and to the input 9 of the input pulse of the BZI 40-1 and then to the single input of the trigger 48, which goes into a single state and the unit signal from its single output goes to the second input of the And 43 circuit and allows the passage of pulses fazir from the 1st input of the BZI 40-1 to the counting input of the counter 44. From this moment, the next sampling delay delay cycle starts for the number of microtacts GTI 11, which is set by a digital signal from UEM 16 in the buffer register of the delay period 47 and rewritten in the register of the delay period 46 on a single control signal from input 4 of the BZI 40-1.

The pulse from output 3 of the delayed pulse BZI 40-1 is the first pulse in the delayed sequence of sampling pulses. It arrives at the first input of the OR 38-3 circuit, passing it, goes to the first input of the And 41-2 circuit and from its output to the output of 3 delayed sampling pulses of the BZPI, as well as to the counting input of the counter 42 and to the input 9 of the input pulse of the BZI 40 -4 and then to the single input of trigger 48 (see Fig. 19), which goes into a single state and a single signal from its single output is fed to the second input of the And 43 circuit and allows the passage of phasing pulses from the 1st input of the BZI 40-4 to the counting input of the counter 44, starting the process of generating an interrupt pulse with a delay n ADC operating time, which signal has a digital value stored in the register 46 in the delay period Bzi 40-4. At the same time, the first pulse of the delayed sequence of sampling pulses arrives at input 2 of zeroing the BZI 40-3 and from it to the input of zeroing the counter 44 (see Fig. 19) and sets a digital signal in it with a zero value, thereby preparing the BSI 40-3 for a delay the received first pulse of the delayed sequence is delayed by a sampling period, the value of which has a digital signal stored in the register of the delay period 46 in the BZI 40-3. At the same time, the first pulse of the delayed sequence of sampling pulses is fed to input 9 of the input pulse of the BZI 40-3 (see Fig. 18) and from it to the single input of the trigger 48 (see Fig. 19), translating it into a single state. A single signal from the single output of flip-flop 48 is fed to the second input of the And 43 circuit and allows the passage of phasing pulses from the 1st input of the BZI 40-1 to the counting input of the counter 44. The counter 44 counts the phasing pulses arriving at its counting input, until , while the value of the digital signal at its output does not coincide with the value of the digital signal at the output of the delay period register 46. When the values of the digital signals from the counter 44 and the delay period register 46 at their inputs match, the comparison circuit 45 generates a single the personal impulse, which enters the output 3 of the delayed impulse BZI 40-3, from which it enters the second input of the OR 38-3 circuit (see Fig. 18), passing it, goes to the first input of the I 41-2 circuit and from its output output 3 delayed sampling pulses BZPI. This produces a second pulse in the sequence of delayed sampling pulses. The process is repeated cyclically with a sampling period until a new impulse arrives from output 3 of the delayed pulse BZI 40-1, which will give rise to the formation of the next delayed pulse sequence.

Each pulse in a delayed sequence of pulses from the output of the And 41-2 circuit goes to the input 9 of the input pulse of the BZI 40-2 and starts the process of generating at the output 7 of the ban state of the BZI 40-2 of a zero signal that goes to the second input of the And 41-2 circuit and prevents the AND 41-2 circuit from passing a new delayed pulse arriving through the OR 38-3 circuit from the output of the BZI 40-1 for a certain protective period of time, the value of which has a digital signal in the register of the delay period 46 in the BZI 40-2.

When a single pulse of the delayed sequence arrives at input 9 of the input pulse of the BZI 40-2, its trigger 48 goes into a single state (see Fig. 19) and the zero signal from its zero output through the output 7 of the state of the counting inhibit goes to the second output of the And 41- circuit 2 (see Fig. 18), prohibiting the passage of pulses to its output from its first input while maintaining a zero signal value at the zero output of trigger 48 (see Fig. 19). A single signal from a single output of flip-flop 48 at the second input of And 43 circuit allows phasing pulses to pass through it from the 1st input of the BZI 40-2 to the counting input of counter 44. Counter 44 counts the phasing pulses arriving at its counting input, until , while the value of the digital signal at its output does not match the value of the digital signal of the inhibit time at the output of the delay period register 46. When the values of the digital signals from the counter 44 and the delay period register 46 at their inputs match, the comparison circuit 45 generates in its output, a single pulse, which is fed to output 3 of the delayed pulse of the BSI 40-2, from which it is fed to the second input of the OR 38-4 circuit and through it to the input 2 of the zeroing pulse and to input 8 of the prohibition of calculating the BSI 40-2 (see Fig. . eighteen). Under the influence of a single signal at input 8 of the prohibition of counting the BZI 40-2, the trigger 48 goes to the zero state (see Fig. 19) and a single signal from its zero output goes to the output 7 of the BZI 40-2, from where it goes to the second input of the And 41 circuit -2, allowing the passage through it of single pulses from its first input (see Fig. 18). At the same time, the zero signal from the single output of trigger 48 is fed to the first input of circuit I 43 (see Fig. 19) and prohibits the passage through it from input 1 of phasing pulses BZI 40-2 to the counting input of counter 44. At the same time, a single signal from input 2 of the reset pulse BZI 40-2 enters the zeroing input of the counter 44 (see Fig. 19) and sets a digital signal with a zero value in it, preparing for the next operation cycle of the BZI 40-2.

When a single pulse of the delayed sequence arrives at input 9 of the input pulse of the BZI 40-4, its trigger 48 goes into a single state (see Fig. 19) and a single signal from its single output at the second input of the And 43 circuit allows phasing pulses from 1 to pass through it -th input of BZI 40-4 to the counting input of counter 44. Counter 44 counts the phasing pulses arriving at its counting input until the value of the digital signal at its output matches the value of the digital signal of the response delay time A The CPU at the output of the register of the delay period 46. When the values of the digital signals from the counter 44 and the register of the period of the delay 46 match at their inputs, the comparison circuit 45 generates a single pulse at its output, which is fed to the output 3 of the delayed pulse BZI 40-4, from which it is supplied the output 5 of the interruption of the BZPI (see Fig. 18), to the input 8 of the prohibition of calculating the BZI 40-4 and to the second input of the OR 38-5 circuit and through it to the input 2 of the pulse of resetting the BZI 40-4. Under the influence of a single signal at input 8 of the prohibition of counting the BZI 40-4, trigger 48 goes to the zero state (see Fig. 19) and the zero signal from the single output of trigger 48 goes to the first input of circuit I 43 and prevents the passage of pulses through it from input 1 phasing of the BZI 40-4 to the counting input of the counter 44. At the same time, a single signal from the input 2 of the zeroing pulse BZI 40-4 is fed to the input of the zeroing of the counter 44 (see Fig. 19) and sets a digital signal in it with a zero value, preparing for the next cycle BZI 40-4 work.

As a result, the phasing and auto-tracking of the signal is carried out schematically, through the use of a counter-divider 19, sampling units of the antenna signal 23, a delay unit for the pulse train 20, a key 21, a counter for the auto tracking period 34, a comparison circuit 35, a register for the auto tracking period 36, the OR circuit 37, register of the antenna pointing signal in azimuth 24, register of the antenna pointing signal in elevation 25, digital-to-analog converter of the guidance signal in azimuth 26, digital-to-analog converter of the pointing signal of the elevation 27, the lower filter guidance signal frequency azimuth 28, low-pass filter frequency tracking signal 29 elevation, electro-machine azimuth guidance amplifiers 30, amplifiers Electrical machine guidance elevation 31, drives the azimuth guidance 32; elevation guidance drives 33 and indexed memory arrays. The speed of the phasing device is ensured by reducing the load on the beamforming processor 14, which only selects from the array and adds the signal samples previously recorded in the memory 15 and does not have to multiply complex numbers, as in the analogue. Due to the proper delay of the sampling pulses individually for each antenna, it is possible to receive and phasing broadband signals.

Thus, a method and devices have been proposed that will provide reception, processing and auto-tracking of broadband signals without distortion while maintaining the speed of the phasing device for antenna field antennas when receiving broadband signals from the antenna field that carry, for example, telemetric information about the state of onboard systems of spacecraft.

Claims (153)

1. The method of phasing and equal-difference auto tracking non-equidistant digital antenna array for receiving broadband signals, and the signal is received by antennas that are part of the antenna array, characterized in that for each of the two quadrature signals in the information channel and in the two auto-tracking channels of each antenna, digital (discrete) samples of the received signal are generated at time instants related to the same edge of the corresponding signal, with the subsequent summation of digital (discrete) samples of the corresponding channel and the corresponding front of the corresponding quadrature signal from the array antennas, and in each auto-tracking channel, for each antenna, samples formed ahead of the curve precede sampling, and samples formed behind, respectively, lag behind the signal from the corresponding antenna in the information channel by the deviation time interval, why the sampling pulses of the signal of the reference antenna and each driven antenna delay (shift) for a given time interval of the stand relative to the time of arrival of the front of the corresponding signal of the corresponding antenna to the phasing and auto tracking device, the generated digital (discrete) samples of the received signals from the antennas are recorded in the corresponding indexed memory arrays with indices that relate to the current wavefront of the received signal, after the time interval of the stand after recording digital (discrete) samples of each of the two quadratures of the reference antenna, select from the corresponding arrays and summarize information digital (discrete) samples for each quadrature, one from each antenna with an index related to the current signal wavefront, and write the resulting total information sample of each quadrature into the corresponding array with the corresponding index, in each auto tracking cycle for the current sample index, the phase of the vector of the information signal is calculated from the total values of the information samples of the corresponding quadrature, for each antenna and each of the two quadratures, a differential digital auto-tracking signal is generated with the value of the difference of the values of the samples in the auto-tracking channels of each of the two quadratures taken ahead of the curve and behind the corresponding sample of the information channel, for each quadrature, a total digital auto-tracking signal is generated for the near or far part of the array with a value equal to the sum of the difference signals of the antennas of the corresponding quadrature, respectively, of the part of the antenna field near or far to the moving object relative to the phase center of the array, for each quadrature, a differential digital lattice auto-tracking signal is generated along the elevation angle with the value of the difference of the total values of the difference signals of the antenna near and far to the moving object parts of the antenna field relative to the phase center of the array, by quadratures of the difference digital signal of the lattice auto tracking according to the elevation angle, the module and phase of the vector of the difference digital signal of the lattice auto tracking along the elevation angle are determined, determine the sign of the digital signal of the lattice auto tracking by the elevation angle as the cosine sign of the phase difference of the vector of the difference digital lattice auto tracking signal by the elevation angle and the information signal vector, determining the elevation angle of the antenna array pattern for the next auto tracking cycle by adding to the elevation angle value of the array antennas radiation pattern for the current auto tracking cycle a value proportional to the magnitude of the vector module of the differential digital lattice auto tracking signal at elevation with the sign of the digital lattice auto tracking signal at elevation angle, for each quadrature, a total digital auto-tracking signal is generated for the left or right side of the array with a value equal to the sum of the difference signals of the antennas of the corresponding quadrature, respectively, left or right relative to the direction of the moving part of the antenna field relative to the phase center of the array, for each quadrature, a differential digital auto-tracking signal is generated in azimuth with the difference value of the total values of the difference signals of the left and right antennas relative to the direction of the parts of the antenna field relative to the phase center of the array to the moving object, the quadratures of the differential digital signal of the lattice auto tracking in azimuth determine the module and phase of the vector of the difference digital signal of the lattice auto tracking in azimuth, determine the sign of the digital signal of the lattice auto tracking in azimuth as the cosine sign of the phase difference of the vector of the difference digital lattice auto tracking signal in azimuth and the information signal vector, determine the azimuth of the antenna array radiation pattern for the next auto tracking cycle by adding to the azimuth value of the antenna array radiation pattern for the current auto tracking cycle a value proportional to the magnitude of the vector module of the differential digital lattice auto tracking signal in azimuth with the sign of the digital automatic tracking antenna signal in azimuth, determine the directional cosines of the radiation patterns of the antennas of the antenna array at the next step of auto tracking in the local coordinate system, determine the difference in the path of the rays from the direction of the antenna pattern at the next step of auto tracking between each driven antenna and the reference antenna array, determine the shift in time of arrival of the radio signal at the next step of auto tracking between each driven antenna and the reference antenna array, replace the digital signals of the time shift of the arrival of the radio signal between each slave antenna and the reference antenna array at the current auto tracking step by the digital signals of the shift by the time of arrival of the radio signal between each driven antenna and the reference antenna array at the next auto tracking step, after which they proceed to the next auto tracking step. 2. The method according to claim 1, characterized in that the sampling pulses of the signal of the reference antenna delay (shift) by the time interval of the stand, which should be more than the time interval equal to the difference between the maximum and minimum time intervals of signal propagation in the feeders of the antenna paths from the phase center of the antenna to the phasing and auto tracking device, plus the maximum time interval of signal propagation in free space along the antenna array, plus the time interval of the deviation of the sampling moment in the auto tracking channel relative to the information channel, plus the response time of the analog-to-digital converter, and the sampling pulses of the signal of each driven antenna delay (shift) the stand time interval, plus the difference of the signal propagation time intervals from the phase centers of the slave and reference antennas to the phasing and auto tracking device, plus the shift time of the moment of arrival of the wavefront of the received signal at the phase center of the driven antenna relative to the moment of arrival of the same wavefront of the received signal at the phase center of the reference antenna. 3. The method according to claim 1, characterized in that the generated differential digital signal of the auto-tracking of the lattice in elevation or azimuth is converted into analog form, filtered on a low-pass filter, amplified by electric amplifiers and fed to the antenna drives of the array, respectively, in angle places either in azimuth. 4. A phasing device and equal-difference differential auto-tracking of a nonequidistant digital antenna array for receiving broadband signals, comprising a receiver, a beamforming processor, a memory device, a data bus, a computer, an address decoder, a clock generator, a local oscillator, and a set of signal paths from the antennas, being part of the antenna array, and each of the signal paths is connected to the data bus, and the control computer, the address signal decoder and the clock generator are common for each of the signal paths, characterized in that said signal reception path includes two antenna signal sampling units associated with an address decoder that controls the computer, the receiver and the antenna control paths of the array in azimuth and elevation, blocks of delay of the pulse sequence are connected to the address decoder controlling the computer, the receiver — one for each sampling channel. 5. The device according to claim 4, characterized in that it includes counter divider, said pulse train delay unit, index signal key, register of the antenna pointing signal in azimuth, register of the antenna pointing signal in elevation, digital-to-analog converter of the guidance signal in azimuth, digital-analog converter of the pointing signal in elevation; low-pass filter of the azimuth guidance signal, low-pass filter of the elevation guidance signal, electric machine amplification guidance for the azimuth of each antenna, electromachine guidance amplifiers for the elevation angle of each antenna, azimuth guidance actuators for each antenna, guidance actuators for the elevation angle of each antenna, auto tracking period counter; auto tracking period comparison circuit, auto tracking period signal register, OR circuit, and the output of the clock generator is connected to the counting input of the counter-divider and to the input of the phasing pulses of the delay block of the pulse sequence, the output of the counter-divider is connected to the synchronization input of the control computer and to the input of the sampling pulses of the delay block of the pulse sequence, the first address bus of the control computer is connected to the input of the address decoder, the address, data and control bus of the control computer is connected to the address, data and control bus of the storage device, the control output of the control computer is connected to the control input of the beamforming processor, the data input of the beamforming processor is connected to the first data output of the storage device, the data output of the beamforming processor is connected to the receiver data input, the second data output of the storage device is connected to the input of the data output of the bus, the data input output of which is connected to the data input of the storage device, the output of the data bus data output is connected to the input of the data input bus of the pulse train delay unit, to the data input of the signal register of the auto tracking period, to the data input of the antenna guidance signal register in azimuth and to the antenna input of the antenna signal signal register in elevation, the first output of the address decoder is connected to the control input of the signal register of the auto tracking period, the second output of the address decoder is connected to the control input of the key, the third output of the address decoder is connected to the input of the signal of the beginning of the session of the delay unit of the pulse sequence and to the second input of the OR circuit, the fourth output of the address decoder is connected to the input of the signal of the end of the session of the delay unit of the pulse sequence, the fifth output of the address decoder is connected to the input of the input signal of the code of the sampling period of the pulse sequence delay block, the sixth output of the address decoder is connected to the input signal input delay code analog-to-digital Converter block delay sequence of pulses, the seventh output of the address decoder is connected to the input of the signal input of the time code of the pulse inhibit block delay sequence of pulses, the eighth output of the address decoder is connected to the input signal input delay code block delay sequence of pulses, the ninth output of the address decoder is connected to the control input of the register of the antenna guidance signal in azimuth, the tenth output of the address decoder is connected to the control input of the antenna pointing signal register by elevation, the output of the delayed sampling pulses of the delay block of the pulse sequence is connected to the counting input of the counter of the auto tracking period, the signal output of the reference number of the pulse sequence delay block is connected to the key data input, the output of which is connected to the data bus data input, the output signal of the interruption of the reference block delay sequence of pulses is connected to the second input of the interruption of the control computer, the output of the auto tracking period counter is connected to the first input of the auto tracking period comparison circuit, the second input of which is connected to the output of the auto tracking period signal register, and the output is connected to the first input of the OR circuit and to the first interrupt input of the host computer, the output of the OR circuit is connected to the input of zeroing the counter of the auto tracking period. 6. The device according to claim 4, characterized in that the output of the register of the antenna guidance signal in azimuth is connected to the input of the digital-analog converter of the azimuth guidance signal, the output of which is connected to the low-pass filter input of the azimuth guidance signal, the output of the antenna pointing signal register in elevation is connected to the input of the digital-analog converter of the elevation signal in elevation, the output of which is connected to the low-pass filter of the elevation signal in elevation, the low-pass filter output of the azimuth guidance signal is connected to the input of each azimuth guidance electric machine amplifier, low-pass filter output of the elevation signal of the elevation signal is connected to the input of each electromachine guidance amplifier of elevation, the output of each electrical machine azimuth guidance amplifier is connected to the input of the corresponding drive in the azimuth of the corresponding antenna, the output of each electromachine guidance amplifier in elevation is connected to the input of the corresponding drive in elevation of the corresponding antenna. 7. The device according to claim 4, characterized in that each of the signal reception paths includes two of the aforementioned antenna signal sampling units, one for each of the two quadrature signals, and the output of the first intermediate frequency amplifier with a bandpass filter is connected through a divider, second mixers, the second intermediate frequency amplifiers with a bandpass filter with a signal input - the first contact of the corresponding unit for sampling the antenna signal, the second local oscillator is connected directly to one of the second mixers, and to the second second mixer through a constant phase shifter 90 °, the output of the clock generator is connected to the input of the phasing pulses - the second contact of each antenna signal sampling unit, the output of the counter-divider is connected to the input of the sampling pulses - the third contact of each block of sampling of the antenna signal, the fourth output of each block of sampling the signal of the antenna is connected to the data input input of the data bus, the output of the data bus data output is connected to the data input - the fifth pin of each antenna signal sampling unit, the third output of the address decoder is connected to the input of the session start signal, the sixth contact of each antenna signal sampling unit, the fourth output of the address decoder is connected to the input of the signal of the end of the session - the seventh contact of each block of sampling of the antenna signal, the fifth output of the address decoder is connected to the input of the sampling period code input signal - the eighth pin of each antenna signal sampling unit, the sixth output of the address decoder is connected to the input of the input signal of the delay code of the analog-to-digital converter - the ninth contact of each block of sampling of the antenna signal, the seventh output of the address decoder is connected to the input of the signal input of the pulse inhibit time code - the tenth contact of each block of sampling of the antenna signal, the output [10 + 18 · i + 9 · (j – 1) +1] of the address decoder is connected to the input of the signal output of the digital signal of the reference number of the information channel — the eleventh contact of the j-th block of the signal sampling of the i-th antenna, j = 1, 2 ; i = 0, 1, ..., N - 1, where N is the number of antennas in the array, the output of [10 + 18 · i + 9 · (j – 1) +2] of the address decoder is connected to the input of the output signal of the digital signal of reading the information channel — the twelfth contact of the j-th block of signal sampling of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +3] of the address decoder is connected to the input of the signal input signal delay code channel - the thirteenth pin of the j-th block of the signal sampling block of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +4] of the address decoder is connected to the input of the digital signal output signal of the reference number of the auto tracking channel ahead of the fourteenth pin of the j-th sampling block of the signal of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +5] of the address decoder is connected to the input of the output signal of the digital signal of the reference signal of the auto tracking channel ahead of the fifteenth pin of the j-th signal sampling block of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +6] of the address decoder is connected to the input of the auto-tracking channel delay code input signal ahead of the sixteenth pin of the j-th signal sampling block of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +7] of the address decoder is connected to the input of the digital signal output signal of the reference number of the auto tracking channel with a lag - the seventeenth pin of the j-th signal sampling block of the i-th antenna, the output of [10 + 18 · i + 9 · (j – 1) +8] of the address decoder is connected to the input of the output signal of the digital signal of the reference signal of the auto tracking channel with a lag - the eighteenth pin of the j-th sampling block of the signal of the i-th antenna, the output [10 + 18 · i + 9 · (j – 1) +9] of the address decoder is connected to the input of the auto-tracking channel delay code input signal with a lag - the nineteenth pin of the j-th signal sampling block of the i-th antenna, the output of the interrupt signal from the readout of the information channel — the twentieth contact of the j-th sampling block of the signal of the i-th antenna is connected to the input [2 + 6 · i + 3 · (j – 1) +1] of the interrupt of the control computer, the output of the signal of the interruption of the reference of the auto-tracking channel ahead of the curve — the twenty-first contact of the j-th sampling block of the signal of the i-th antenna is connected to the input [2 + 6 · i + 3 · (j – 1) +2] of the interrupt of the control computer, the output of the signal of the interruption of the countdown of the auto-tracking channel with a lag - the twenty-second contact of each j-th block of sampling the signal of the i-th antenna is connected to the input [2 + 6 · i + 3 · (j – 1) +3] of the control computer interrupt. 8. The device according to p. 4, characterized in that the sampling unit of the antenna signal contains three sampling channels, that is, an information channel and two auto-tracking channels with sampling ahead and behind, which contain three analog-to-digital converters, three delay blocks of the pulse sequence, three keys of the index signal and three keys of the reference signal, that is, one block (circuit element) in each sampling channel, and signal input - the first contact of the antenna signal sampling unit is connected to the signal input of each analog-to-digital converter, phasing pulse input - the second contact of the antenna signal discretization unit is connected to the phasing pulse input - the tenth contact of each pulse sequence delay block, the input of the sampling pulses - the third contact of the sampling unit of the antenna signal is connected to the input of the sampling pulses - the eleventh contact of each delay block of the pulse sequence, output of delayed sampling pulses - the third contact of each delay block of the pulse sequence is connected to the input of the sampling pulses of the analog-to-digital converter of the corresponding sampling channel of the antenna signal sampling unit, in each sampling channel, the output of the corresponding analog-to-digital converter is connected to the data input of the corresponding reference signal key, and the output of each of these keys is connected to the data output - the fourth contact of the antenna signal sampling unit, in each block of the pulse sequence delay, the output of the signal of the reference number — the fourth contact is connected to the data input of the corresponding index signal key, and the output of each of these keys is connected to the data output — the fourth contact of the antenna signal sampling unit, the output of the interruption signal - the fifth contact of the delay block of the pulse sequence of the information channel is connected to the output of the interruption signal counting information channel - the twentieth contact of the sampling unit of the antenna signal, reference interruption signal output - the fifth contact of the delay block of the pulse sequence of the auto-tracking channel ahead of the connected to the output of the interruption signal of the reference channel of the auto-tracking channel ahead of the twenty-first contact of the antenna signal sampling block, reference interrupt signal output - the fifth contact of the delay block of the pulse sequence of the auto-tracking channel with a lag is connected to the output of the reference interrupt signal - twenty-second contact of the auto-tracking channel with a lag of the antenna signal sampling unit, data input - the fifth contact of the antenna signal sampling unit is connected to the input of the data input bus - the eighth contact of each pulse sequence delay unit, the input of the session start signal - the sixth contact of the antenna signal sampling unit is connected to the input of the session start signal - the twelfth contact of each pulse sequence delay block, the input of the signal of the end of the session is the seventh contact of the block sampling the signal of the antenna is connected to the input of the signal of the end of the session is the ninth contact of each block delay sequence of pulses, the input of the sampling period code input signal - the eighth contact of the antenna signal sampling unit is connected to the input of the sampling period code input signal - the seventh contact of each pulse sequence delay unit, input signal input delay code analog-to-digital Converter - the ninth contact in the block sampling the signal of the antenna is connected to the input signal input delay code analog-to-digital Converter - the sixth contact in each block delay sequence of pulses, pulse inhibit time code input signal input - the tenth contact of the antenna signal sampling block is connected to the pulse inhibit time code input signal input - the second contact of each pulse train delay unit, the input signal is the output of the digital signal of the reference number of the information channel - the eleventh contact of the sampling unit of the antenna signal is connected to the control input of the first key of the index signal, the input signal is the output of the digital reference signal of the information channel - the twelfth contact of the sampling unit of the antenna signal is connected to the control input of the first key of the reference signal, the input signal signal delay code channel information - the thirteenth contact of the sampling unit of the antenna signal is connected to the input signal input delay code - the first contact of the first delay unit of the pulse sequence, the input signal is the digital signal of the reference number of the auto-tracking channel ahead of the curve — the fourteenth contact of the antenna signal sampling unit is connected to the control input of the second index signal key, the input signal is the output of the digital reference signal of the auto-tracking channel ahead of the curve — the fifteenth contact of the antenna signal sampling unit is connected to the control input of the second reference signal key, the input signal of the delay code of the auto-tracking channel delay is the sixteenth contact of the antenna signal sampling unit is connected to the input of the delay code input signal signal is the first contact of the second delay block of the pulse sequence, the input signal of the digital signal of the reference number of the reference channel of the auto tracking lag — the seventeenth contact of the antenna signal sampling unit is connected to the control input of the third key of the index signal, input signal of the digital reference signal of the reference channel of the auto tracking lag - the eighteenth contact of the discretization block of the antenna signal is connected to the control input of the third key of the reference signal, input signal delay code delay channel auto tracking channel - the nineteenth contact block of the discretization of the antenna signal is connected to the input signal input delay code - the first input of the third block delay pulse sequence. 9. The device according to claim 4, characterized in that the pulse sequence delay unit contains five OR circuits, a trigger, two AND circuits, four pulse delay units, a counter, and input signal input delay code - the first contact of the delay unit of the pulse sequence is connected to the input of the input signal of the new delay - the fifth contact of the first block delay pulse the input signal input code time inhibit the pulse is the second contact of the delay unit of the pulse train is connected to the input signal of the input of the new delay - the fifth contact of the second block delay pulse input of the input signal of the delay code of the analog-to-digital converter - the sixth contact in the delay block of the pulse sequence is connected to the input of the input signal of the delay of the new delay - the fifth contact of the fourth block of the pulse delay, the input signal input code of the sampling period - the seventh contact of the delay unit of the pulse sequence is connected to the input of the input signal of the new delay - the fifth contact of the third block delay pulse input of the data input bus - the eighth contact of the delay block of the pulse sequence is connected to the input of the signal code of the new delay - the sixth contact of each of the four blocks of the pulse delay, the signal input of the end of the session - the ninth contact of the delay block of the pulse sequence is connected to the input of the prohibition of counting - the eighth contact of the third block of the delay of the pulse used to delay the sampling pulses, and with the first input of the second OR circuit, phasing pulse input — the tenth contact of the pulse sequence delay unit is connected to the phasing pulse input — the first contact of each pulse delay unit, sampling pulse input - the eleventh contact of the pulse train delay unit is connected to the first input of the first AND circuit, the input of the session start signal — the twelfth contact of the pulse sequence delay block is connected to the counter zeroing input, to the first inputs of the fourth and fifth OR circuits and to the first input of the first OR circuit, whose output is connected to the zeroing pulse input — the second contact of the first pulse delay block, with the input signal input code of the current delay - the fourth contact of each of the four blocks of the delay pulse and with a single input of the trigger, a single output of which is connected to the second input of the first circuit And, the output of which, in in turn, connected to the input pulse input - the ninth contact of the first pulse delay unit, delayed pulse output - the third contact of the first pulse delay block is connected to the second input of the first OR circuit, with the second input of the second OR circuit, with the first input of the third OR circuit and with the input pulse input - the ninth contact of the third pulse delay block, the output of the state of counting resolution - the tenth contact of the first block of the delay pulse is connected to the zero input of the trigger, the output of the second OR circuit is connected to the input of the prohibition of counting - the eighth contact of the first block delay pulse, delayed pulse output - the third contact of the third pulse delay block is connected to the second input of the third OR circuit, the output of which is connected to the zero pulse input - the second contact of the third pulse delay block and to the first input of the second AND circuit, delayed pulse output - the third contact of the second pulse delay block is connected to the second input of the fourth OR circuit, the output of the fourth OR circuit is connected to the input of the zeroing pulse - the second contact of the second pulse delay unit and to the counting inhibit input - the eighth contact of the second pulse delay unit, counting inhibit status output - the seventh contact of the second pulse delay unit is connected to the second input of the second And circuit, the output of which is connected to the counter input of the counter, the input pulse input is the ninth contact of the second pulse delay unit, and the input pulse input is the ninth contact of the fourth pulse delay unit and with the output of the delayed sampling pulses, the third contact of the pulse train delay unit, delayed pulse output - the third contact of the fourth pulse delay block is connected to the second input of the fifth OR circuit, with the counting inhibit input - the eighth contact of the fourth BZI and with the output of the index interrupt signal - the fifth contact of the pulse sequence delay block, the output of the fifth OR circuit is connected to the input of the reset pulse — the second contact of the fourth pulse delay unit, the counter output is connected to the output of the index signal - the fourth contact of the pulse sequence delay block. 10. The device according to claim 4, characterized in that the pulse delay unit comprises an AND circuit, a counter, a comparison circuit, a delay period register, a buffer register of the delay period, a trigger, moreover phasing pulse input - the first contact of the pulse delay unit is connected to the first input of the AND circuit, zeroing pulse input - the second contact of the pulse delay block is connected to the counter zeroing input, current delay code input signal input - the fourth contact of the pulse delay unit is connected to the control input of the delay period register, input signal input code new delay - the fifth contact of the pulse delay unit is connected to the control input of the buffer register of the delay period, new delay code signal input - the sixth contact of the pulse delay block is connected to the data input of the buffer register of the delay period, counting inhibit input - the eighth contact of the pulse delay block is connected to the zero input of the trigger, input pulse input - the ninth contact of the pulse delay unit is connected to a single trigger input, the trigger single output is connected to the second input of the AND circuit and to the output of the counting resolution state — the tenth contact of the pulse delay unit, the trigger zero output is connected to the output of the count prohibition state - the seventh contact of the pulse delay unit, circuit output AND is connected to the counter input of the counter, the output of which is connected to the first input of the comparison circuit, the output of the delay period register is connected to the second input of the comparison circuit, the output of which is connected to the output of the delayed pulse — the third contact of the pulse delay block.

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